[llvm] 8d06a70 - [NFCI][AArch64] Use DAG Helper Functions
Archibald Elliott via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 3 06:25:59 PST 2023
Author: Archibald Elliott
Date: 2023-03-03T14:25:49Z
New Revision: 8d06a7098588a7375d727a3bf826b2aa2e8f75c1
URL: https://github.com/llvm/llvm-project/commit/8d06a7098588a7375d727a3bf826b2aa2e8f75c1
DIFF: https://github.com/llvm/llvm-project/commit/8d06a7098588a7375d727a3bf826b2aa2e8f75c1.diff
LOG: [NFCI][AArch64] Use DAG Helper Functions
This commit is a cleanup of a few things in the SelectionDAG
implementation:
- to have more places use `splitInt128`, rather than duplicating that
functionality when they are turning a 128-bit value into two 64-bit
values,
- to refactor `splitInt128` to use EXTRACT_ELEMENT which is for
splitting wide integers in two (rather than the equivalent with shifts
and truncs), and
- to use the concise helpers for INSERT_/EXTRACT_SUBREG in more places.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 7fed41882f15e..401543f50416e 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -961,10 +961,7 @@ static SDValue narrowIfNeeded(SelectionDAG *CurDAG, SDValue N) {
return N;
SDLoc dl(N);
- SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
- MachineSDNode *Node = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
- dl, MVT::i32, N, SubReg);
- return SDValue(Node, 0);
+ return CurDAG->getTargetExtractSubreg(AArch64::sub_32, dl, MVT::i32, N);
}
// Returns a suitable CNT/INC/DEC/RDVL multiplier to calculate VSCALE*N.
@@ -1237,12 +1234,10 @@ bool AArch64DAGToDAGISel::SelectAddrModeUnscaled(SDValue N, unsigned Size,
static SDValue Widen(SelectionDAG *CurDAG, SDValue N) {
SDLoc dl(N);
- SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
SDValue ImpDef = SDValue(
CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::i64), 0);
- MachineSDNode *Node = CurDAG->getMachineNode(
- TargetOpcode::INSERT_SUBREG, dl, MVT::i64, ImpDef, N, SubReg);
- return SDValue(Node, 0);
+ return CurDAG->getTargetInsertSubreg(AArch64::sub_32, dl, MVT::i64, ImpDef,
+ N);
}
/// Check if the given SHL node (\p N), can be used to form an
@@ -2615,9 +2610,9 @@ bool AArch64DAGToDAGISel::tryBitfieldExtractOp(SDNode *N) {
CurDAG->getTargetConstant(Imms, dl, MVT::i64)};
SDNode *BFM = CurDAG->getMachineNode(Opc, dl, MVT::i64, Ops64);
- SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
- ReplaceNode(N, CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl,
- MVT::i32, SDValue(BFM, 0), SubReg));
+ SDValue Inner = CurDAG->getTargetExtractSubreg(AArch64::sub_32, dl,
+ MVT::i32, SDValue(BFM, 0));
+ ReplaceNode(N, Inner.getNode());
return true;
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 554733cd84b16..aa1049cf09a08 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -4364,10 +4364,7 @@ SDValue AArch64TargetLowering::LowerBITCAST(SDValue Op,
Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
- return SDValue(
- DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, OpVT, Op,
- DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
- 0);
+ return DAG.getTargetExtractSubreg(AArch64::hsub, DL, OpVT, Op);
}
static EVT getExtensionTo64Bits(const EVT &OrigVT) {
@@ -5726,6 +5723,15 @@ SDValue AArch64TargetLowering::LowerSTORE(SDValue Op,
return SDValue();
}
+static std::pair<SDValue, SDValue> splitInt128(SDValue N, SelectionDAG &DAG) {
+ SDLoc DL(N);
+ SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i64, N,
+ DAG.getConstant(0, DL, MVT::i64));
+ SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i64, N,
+ DAG.getConstant(1, DL, MVT::i64));
+ return std::make_pair(Lo, Hi);
+}
+
/// Lower atomic or volatile 128-bit stores to a single STP instruction.
SDValue AArch64TargetLowering::LowerStore128(SDValue Op,
SelectionDAG &DAG) const {
@@ -5745,15 +5751,12 @@ SDValue AArch64TargetLowering::LowerStore128(SDValue Op,
? StoreNode->getOperand(1)
: StoreNode->getOperand(2);
SDLoc DL(Op);
- SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i64, Value,
- DAG.getConstant(0, DL, MVT::i64));
- SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i64, Value,
- DAG.getConstant(1, DL, MVT::i64));
-
+ auto StoreValue = splitInt128(Value, DAG);
unsigned Opcode = IsStoreRelease ? AArch64ISD::STILP : AArch64ISD::STP;
SDValue Result = DAG.getMemIntrinsicNode(
Opcode, DL, DAG.getVTList(MVT::Other),
- {StoreNode->getChain(), Lo, Hi, StoreNode->getBasePtr()},
+ {StoreNode->getChain(), StoreValue.first, StoreValue.second,
+ StoreNode->getBasePtr()},
StoreNode->getMemoryVT(), StoreNode->getMemOperand());
return Result;
}
@@ -6144,16 +6147,11 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
SDValue Chain = Op.getOperand(0);
SDValue SysRegName = Op.getOperand(1);
- SDValue Pair = Op.getOperand(2);
-
- SDValue PairLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i64, Pair,
- DAG.getConstant(0, DL, MVT::i32));
- SDValue PairHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i64, Pair,
- DAG.getConstant(1, DL, MVT::i32));
+ std::pair<SDValue, SDValue> Pair = splitInt128(Op.getOperand(2), DAG);
// chain = MSRR(chain, sysregname, lo, hi)
SDValue Result = DAG.getNode(AArch64ISD::MSRR, DL, MVT::Other, Chain,
- SysRegName, PairLo, PairHi);
+ SysRegName, Pair.first, Pair.second);
return Result;
}
@@ -9358,25 +9356,16 @@ SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
// If we are lowering a f16 and we do not have fullf16, convert to a f32 in
// order to use FCSELSrrr
if ((Ty == MVT::f16 || Ty == MVT::bf16) && !Subtarget->hasFullFP16()) {
- TVal = SDValue(
- DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
- DAG.getUNDEF(MVT::f32), TVal,
- DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
- 0);
- FVal = SDValue(
- DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
- DAG.getUNDEF(MVT::f32), FVal,
- DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
- 0);
+ TVal = DAG.getTargetInsertSubreg(AArch64::hsub, DL, MVT::f32,
+ DAG.getUNDEF(MVT::f32), TVal);
+ FVal = DAG.getTargetInsertSubreg(AArch64::hsub, DL, MVT::f32,
+ DAG.getUNDEF(MVT::f32), FVal);
}
SDValue Res = LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
if ((Ty == MVT::f16 || Ty == MVT::bf16) && !Subtarget->hasFullFP16()) {
- Res = SDValue(
- DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, Ty, Res,
- DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
- 0);
+ return DAG.getTargetExtractSubreg(AArch64::hsub, DL, Ty, Res);
}
return Res;
@@ -22092,11 +22081,8 @@ void AArch64TargetLowering::ReplaceBITCASTResults(
if (VT != MVT::i16 || (SrcVT != MVT::f16 && SrcVT != MVT::bf16))
return;
- Op = SDValue(
- DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
- DAG.getUNDEF(MVT::i32), Op,
- DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
- 0);
+ Op = DAG.getTargetInsertSubreg(AArch64::hsub, DL, MVT::f32,
+ DAG.getUNDEF(MVT::i32), Op);
Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
}
@@ -22162,15 +22148,6 @@ static void ReplaceReductionResults(SDNode *N,
Results.push_back(SplitVal);
}
-static std::pair<SDValue, SDValue> splitInt128(SDValue N, SelectionDAG &DAG) {
- SDLoc DL(N);
- SDValue Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i64, N);
- SDValue Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i64,
- DAG.getNode(ISD::SRL, DL, MVT::i128, N,
- DAG.getConstant(64, DL, MVT::i64)));
- return std::make_pair(Lo, Hi);
-}
-
void AArch64TargetLowering::ReplaceExtractSubVectorResults(
SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
SDValue In = N->getOperand(0);
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