[PATCH] D145236: [AArch64] Improve codegen for vectorised loops with two active lane masks

[David Sherwood via Phabricator via llvm-commits]

david-arm created this revision.
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When vectorising loops using tail-folding and interleaving we end up
with two back-to-back active.lane.mask intrinsic calls. Unfortunately,
this leads to poor codegen like this:

.LBB0_1:

  ...
  whilelo p1.b, x11, x1
  csetw13, mi
  whilelo p0.b, x12, x1
  tbnzw13, #0, .LBB0_1

This is because in AArch64InstrInfo::optimizeCondBranch we bail out if
we find a flag-setting operation between a CSINC and a TBNZW machine
node. However, in these cases nothing depends upon the flags set by
the second whilelo and it's safe to move it above the first whilelo.

I've changed AArch64InstrInfo::optimizeCondBranch to support having
a single flag-setting operation between CSINC and TBNZW, provided
we can prove it's safe to move it above the first flag-setting op.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D145236

Files:
  llvm/lib/CodeGen/PeepholeOptimizer.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/test/CodeGen/AArch64/active_lane_mask.ll
  llvm/test/CodeGen/AArch64/sve-loop-two-whiles1.mir
  llvm/test/CodeGen/AArch64/sve-loop-two-whiles2.mir
  llvm/test/CodeGen/AArch64/sve-loop-two-whiles3.mir
  llvm/test/CodeGen/AArch64/sve-loop-two-whiles4.mir
  llvm/test/CodeGen/AArch64/sve-loop-two-whiles5.mir

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