[llvm] 6121190 - [NFC] Refine tests by adding `:` to checks
Mariya Podchishchaeva via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 3 02:23:55 PST 2023
Author: Mariya Podchishchaeva
Date: 2023-03-03T05:23:21-05:00
New Revision: 6121190b8ccca293632a0ba24a3344938dc2d705
URL: https://github.com/llvm/llvm-project/commit/6121190b8ccca293632a0ba24a3344938dc2d705
DIFF: https://github.com/llvm/llvm-project/commit/6121190b8ccca293632a0ba24a3344938dc2d705.diff
LOG: [NFC] Refine tests by adding `:` to checks
The tests can fail if working directory where the tests were launched
has a `error` substring in its path.
Reviewed By: jhenderson, foad
Differential Revision: https://reviews.llvm.org/D144562
Added:
Modified:
llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
llvm/test/MC/AMDGPU/gfx11_asm_vop3_err.s
llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s
llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s
llvm/test/MC/ARM/thumb-branches.s
llvm/test/MC/ARM/thumb2-branch-ranges.s
llvm/test/MC/Hexagon/PacketRules/hvx_vshuff_vdeal.s
llvm/test/MC/Hexagon/c4_newval.s
llvm/test/MC/Hexagon/multiple-pc4.s
llvm/test/MC/Hexagon/zreg-post-inc.s
llvm/test/TableGen/GICombinerEmitter/defs-invalid.td
llvm/test/TableGen/GICombinerEmitter/match-invalid.td
llvm/test/tools/llvm-dwarfdump/X86/debug_tls_relocs.s
Removed:
################################################################################
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
index f18fdf367638f..2ebb06fb7f907 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
v_ceil_f16_e32 v128, 0xfe0b
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
index c226280a286da..d4bf86f64e60f 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
v_add_f16_e32 v255, v1, v2
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_err.s
index 14c27d53df114..f1189d0580859 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_err.s
@@ -1,5 +1,5 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1]
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s
index aa58d3ac016b2..d3de2cbf12b83 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopc_t16_err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
v_cmp_class_f16_e32 vcc, v1, v255
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s
index ae959d6a8b767..0cea363b42d97 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vopcx_t16_err.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s
v_cmpx_class_f16_e32 v1, v255
// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
diff --git a/llvm/test/MC/ARM/thumb-branches.s b/llvm/test/MC/ARM/thumb-branches.s
index 68bf550118d1b..c9e1660e1cdb6 100644
--- a/llvm/test/MC/ARM/thumb-branches.s
+++ b/llvm/test/MC/ARM/thumb-branches.s
@@ -11,7 +11,7 @@
bl shortend
.space 0x3fffff
shortend:
-// CHECKSHORT-NOT: error
+// CHECKSHORT-NOT: error:
// CHECKSHORT: [[@LINE+1]]:{{[0-9]}}: error: Relocation out of range
bl shortend2
.space 0x400000
@@ -31,8 +31,8 @@ end2:
.global end3
end3:
-// CHECK-NOT: error
-// CHECKSHORT-NOT: error
+// CHECK-NOT: error:
+// CHECKSHORT-NOT: error:
// CHECKSHORT: [[@LINE+2]]:{{[0-9]}}: error: Relocation out of range
// CHECK: [[@LINE+1]]:{{[0-9]}}: error: Relocation out of range
bl end4
@@ -63,7 +63,7 @@ start3:
.space 0xfffffd
bl start3
-// CHECK-NOT: error
+// CHECK-NOT: error:
start4:
.space 0xfffffd
// CHECK: [[@LINE+2]]:{{[0-9]}}: error: Relocation out of range
diff --git a/llvm/test/MC/ARM/thumb2-branch-ranges.s b/llvm/test/MC/ARM/thumb2-branch-ranges.s
index 83cb0259d7412..fc8044acde8a3 100644
--- a/llvm/test/MC/ARM/thumb2-branch-ranges.s
+++ b/llvm/test/MC/ARM/thumb2-branch-ranges.s
@@ -25,7 +25,7 @@ end3: bx lr
.thumb
// branch to thumb function is resolved at assembly time
-// CHECK-NOT: error
+// CHECK-NOT: error:
// CHECK: [[@LINE+2]]:{{[0-9]}}: error: Relocation out of range
// CHECK-LABEL: b.w end4
b.w end4
@@ -46,7 +46,7 @@ end6: bx lr
.thumb
// conditional branch to thumb function resolved at assembly time
-// CHECK-NOT: error
+// CHECK-NOT: error:
// CHECK: [[@LINE+2]]:{{[0-9]}}: error: Relocation out of range
// CHECK-LABEL: beq.w end7
beq.w end7
@@ -69,7 +69,7 @@ start2:
start3:
.space 0x1000000
// branch to thumb function resolved at assembly time
-// CHECK-NOT: error
+// CHECK-NOT: error:
// CHECK: [[@LINE+2]]:{{[0-9]}}: error: Relocation out of range
// CHECK-LABEL: b.w start3
b.w start3
@@ -90,7 +90,7 @@ start5:
start6:
.space 0x100000
// branch to thumb function resolved at assembly time
-// CHECK-NOT: error
+// CHECK-NOT: error:
// CHECK: [[@LINE+2]]:{{[0-9]}}: error: Relocation out of range
// CHECK-LABEL: beq.w start6
beq.w start6
diff --git a/llvm/test/MC/Hexagon/PacketRules/hvx_vshuff_vdeal.s b/llvm/test/MC/Hexagon/PacketRules/hvx_vshuff_vdeal.s
index fc8a42477389c..028062f260f7a 100644
--- a/llvm/test/MC/Hexagon/PacketRules/hvx_vshuff_vdeal.s
+++ b/llvm/test/MC/Hexagon/PacketRules/hvx_vshuff_vdeal.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -mv65 -mhvx -filetype=obj -o %t %s 2>&1 | FileCheck --implicit-check-not=error %s
+# RUN: not llvm-mc -arch=hexagon -mv65 -mhvx -filetype=obj -o %t %s 2>&1 | FileCheck --implicit-check-not=error: %s
{ v1 = v2; vshuff(v1,v3,r0) }
# CHECK: error: register `V1' modified more than once
diff --git a/llvm/test/MC/Hexagon/c4_newval.s b/llvm/test/MC/Hexagon/c4_newval.s
index f569aec7d49b1..356a3695c58d1 100644
--- a/llvm/test/MC/Hexagon/c4_newval.s
+++ b/llvm/test/MC/Hexagon/c4_newval.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon %s 2>%t; FileCheck --implicit-check-not=error %s <%t
+# RUN: not llvm-mc -arch=hexagon %s 2>%t; FileCheck --implicit-check-not=error: %s <%t
.Lfoo:
{ p3:0 = r0
diff --git a/llvm/test/MC/Hexagon/multiple-pc4.s b/llvm/test/MC/Hexagon/multiple-pc4.s
index d5eb9887dd147..697991961a5dd 100644
--- a/llvm/test/MC/Hexagon/multiple-pc4.s
+++ b/llvm/test/MC/Hexagon/multiple-pc4.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck --implicit-check-not=error %s <%t
+# RUN: llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck --implicit-check-not=error: %s <%t
# Check that multiple changes to a predicate in a packet are caught.
diff --git a/llvm/test/MC/Hexagon/zreg-post-inc.s b/llvm/test/MC/Hexagon/zreg-post-inc.s
index 346bec1b0fddb..696e18d9ea7b4 100644
--- a/llvm/test/MC/Hexagon/zreg-post-inc.s
+++ b/llvm/test/MC/Hexagon/zreg-post-inc.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -arch=hexagon -filetype=obj -mhvx -mcpu=hexagonv66 %s 2> %t; FileCheck --implicit-check-not=error %s <%t
+# RUN: not llvm-mc -arch=hexagon -filetype=obj -mhvx -mcpu=hexagonv66 %s 2> %t; FileCheck --implicit-check-not=error: %s <%t
{
if (p0) memb(r14+#8)=r4.new
diff --git a/llvm/test/TableGen/GICombinerEmitter/defs-invalid.td b/llvm/test/TableGen/GICombinerEmitter/defs-invalid.td
index fe11ef4673ec2..b2d2f95678e8e 100644
--- a/llvm/test/TableGen/GICombinerEmitter/defs-invalid.td
+++ b/llvm/test/TableGen/GICombinerEmitter/defs-invalid.td
@@ -1,6 +1,6 @@
// RUN: not llvm-tblgen -I %p/../../../include -gen-global-isel-combiner \
// RUN: -combiners=MyCombiner %s 2>&1 | \
-// RUN: FileCheck -implicit-check-not=error %s
+// RUN: FileCheck -implicit-check-not=error: %s
include "llvm/Target/Target.td"
include "llvm/Target/GlobalISel/Combine.td"
diff --git a/llvm/test/TableGen/GICombinerEmitter/match-invalid.td b/llvm/test/TableGen/GICombinerEmitter/match-invalid.td
index 8d7ed8006c99e..c69018bb362de 100644
--- a/llvm/test/TableGen/GICombinerEmitter/match-invalid.td
+++ b/llvm/test/TableGen/GICombinerEmitter/match-invalid.td
@@ -1,6 +1,6 @@
// RUN: not llvm-tblgen -I %p/../../../include -gen-global-isel-combiner \
// RUN: -combiners=MyCombiner %s 2>&1 | \
-// RUN: FileCheck -implicit-check-not=error %s
+// RUN: FileCheck -implicit-check-not=error: %s
include "llvm/Target/Target.td"
include "llvm/Target/GlobalISel/Combine.td"
diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_tls_relocs.s b/llvm/test/tools/llvm-dwarfdump/X86/debug_tls_relocs.s
index d432ecf2baf97..769113a34885e 100644
--- a/llvm/test/tools/llvm-dwarfdump/X86/debug_tls_relocs.s
+++ b/llvm/test/tools/llvm-dwarfdump/X86/debug_tls_relocs.s
@@ -1,7 +1,7 @@
# RUN: llvm-mc %s -filetype obj -triple x86_64-pc-linux -o %t.o
# RUN: llvm-dwarfdump -v %t.o | FileCheck %s
-# CHECK-NOT: error
+# CHECK-NOT: error:
# CHECK: DW_AT_location [DW_FORM_exprloc] (DW_OP_const8u 0x0, DW_OP_GNU_push_tls_address)
# CHECK: DW_AT_location [DW_FORM_exprloc] (DW_OP_const4u 0x0, DW_OP_GNU_push_tls_address)
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