[PATCH] D145175: [ASAN] Support memory checks on scalable vector typed loads and stores

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp:1425
+  if (!TypeStoreSize.isScalable() &&
+      (TypeStoreSize == 8 || TypeStoreSize == 16 || TypeStoreSize == 32 ||
+       TypeStoreSize == 64 || TypeStoreSize == 128) &&
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reames wrote:
> craig.topper wrote:
> > Should we call TypeStoreSize.getFixedValue() while we're here instead of using implicit conversion to unsigned?
> Honestly, it should probably be a switch inside a condition.  Mind if I do that as a separate post commit?   I'd like to keep the change isolated here.  
Sure.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145175/new/

https://reviews.llvm.org/D145175