[PATCH] D145163: Add support for vectorization of interleaved memory accesses for scalable VF

[Luke Lau via Phabricator via llvm-commits]

luke added a comment.

Thanks for adding this! I'm currently plugging in the hooks for RISC-V and will let you know what I run into.



================
Comment at: llvm/lib/IR/IRBuilder.cpp:587
+  if (Factor != 2)
+    return nullptr;
+  assert(Ty->isVectorTy() && "Type should be vector");
----------------
Maybe this should be an assertion


================
Comment at: llvm/lib/Transforms/Vectorize/LoopVectorize.cpp:2721
+        // Check if we can create target specific interleaving load.
+        if (TTI->hasInterleavedLoad(VecTy, AddrParts[Part], Group->getFactor(),
+                                    false))
----------------
Need to check that `Group->getFactor() == 2` here or that the call to CreateMaskedInterleavedLoad succeeds


================
Comment at: llvm/lib/Transforms/Vectorize/LoopVectorize.cpp:2809
+    // Check if we can create target specific interleaving store.
+    if (TTI->hasInterleavedStore(StoredVecs, AddrParts[Part],
+                                 Group->getFactor(), false)) {
----------------
Need to check `Group->getFactor() == 2` here too


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  https://reviews.llvm.org/D145163/new/

https://reviews.llvm.org/D145163