[PATCH] D145071: [clang][RISCV] Set HasLegalHalfType to true if zfh is enabled

[Zahira Ammarguellat via Phabricator via llvm-commits]

zahiraam added a comment.

> HasFloat16 is unconditionally true for Arm and only gated on SSE2 support for X86

My understanding of that is because all aarch64 implementations support ARMv8 FP which makes half type for this target legal. Setting both HasLegalHalfType and HasFloat16 makes sense.  
That's not the case for x86. HasLegalHalfType needs the avx512fp16 feature to be set.



================
Comment at: clang/lib/Basic/Targets/RISCV.cpp:319
+  if (ISAInfo->hasExtension("zfh"))
+    HasLegalHalfType = true;
+
----------------
If your goal is to avoid excess precision with the target having this feature, then this is the right thing to do. 
https://github.com/llvm/llvm-project/blob/main/clang/lib/Basic/Targets/RISCV.h#L43 will set HasFloat16=true.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145071/new/

https://reviews.llvm.org/D145071