[llvm] c546f13 - [DAGCombiner] Replace LegalOperations check in visitSIGN_EXTEND with LegalTypes.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-03-02T07:52:53-08:00
New Revision: c546f13f1f43e34a6a39ac70d3cf70adab4d05f4

URL: https://github.com/llvm/llvm-project/commit/c546f13f1f43e34a6a39ac70d3cf70adab4d05f4
DIFF: https://github.com/llvm/llvm-project/commit/c546f13f1f43e34a6a39ac70d3cf70adab4d05f4.diff

LOG: [DAGCombiner] Replace LegalOperations check in visitSIGN_EXTEND with LegalTypes.

This is guarding a check for isTypeLegal so it should check is
LegalTypes.

Fixes PR61111.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D145139

Added: 
    llvm/test/CodeGen/AArch64/pr61111.ll

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index e29f26f6991c..54c088bae8f8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -12856,7 +12856,8 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
   if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
     SDValue N00 = N0.getOperand(0);
     EVT ExtVT = cast<VTSDNode>(N0->getOperand(1))->getVT();
-    if (N00.getOpcode() == ISD::TRUNCATE && (!LegalOperations || TLI.isTypeLegal(ExtVT))) {
+    if (N00.getOpcode() == ISD::TRUNCATE &&
+        (!LegalTypes || TLI.isTypeLegal(ExtVT))) {
       SDValue T = DAG.getNode(ISD::TRUNCATE, DL, ExtVT, N00.getOperand(0));
       return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, T);
     }

diff  --git a/llvm/test/CodeGen/AArch64/pr61111.ll b/llvm/test/CodeGen/AArch64/pr61111.ll
new file mode 100644
index 000000000000..d2c72921a922
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr61111.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
+
+define i62 @f(i1 %0) {
+; CHECK-LABEL: f:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT:    and x8, x0, #0x1
+; CHECK-NEXT:    sub x8, x8, #1
+; CHECK-NEXT:    tst x8, #0x3fffffffffffffff
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
+  %2 = zext i1 %0 to i59
+  %3 = call { i59, i1 } @llvm.umul.with.overflow.i59(i59 %2, i59 -1)
+  %4 = extractvalue { i59, i1 } %3, 0
+  %5 = trunc i59 %4 to i21
+  %6 = trunc i59 %4 to i21
+  %7 = ashr i21 %5, %6
+  %8 = sext i21 %7 to i62
+  %9 = icmp ugt i62 -1, %8
+  %10 = zext i1 %9 to i62
+  ret i62 %10
+}
+
+declare { i59, i1 } @llvm.umul.with.overflow.i59(i59, i59)