[PATCH] D145159: [AMDGPU] Match med3 for (max (min ..))

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/saddsat.ll:17
+; GFX6-NEXT:    v_mov_b32_e32 v1, 0x7f
+; GFX6-NEXT:    v_med3_i32 v0, v0, s4, v1
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
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Pierre-vh wrote:
> Seems like med3 cannot take immediate operands. Should a pattern be added to fall back to v_min/v_max if both operands are ext'd constants? 
VOP3 instructions couldn't take a literal operand until gfx10.


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Comment at: llvm/test/CodeGen/AMDGPU/saddsat.ll:27
+; GFX8-NEXT:    v_mov_b32_e32 v1, 0x7f
+; GFX8-NEXT:    v_med3_i32 v0, v0, s4, v1
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
----------------
Pierre-vh wrote:
> Another example, this time it's 2 more instructions so it's a bit worse even.
The extra one is because you're using v_med3_i32 for a 16-bit operation. v_med3_i16 was introduced in gfx9.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D145159/new/

https://reviews.llvm.org/D145159