[PATCH] D145143: [DAGCombiner] Add fold for `~x & x` -> `0`

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

Did you look at performing this inside SimplifyDemandedBits instead?



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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6630
+    return Op0.getOpcode() == ISD::XOR && Op0.getOperand(0) == Op1 &&
+           isAllOnesOrAllOnesSplat(Op0.getOperand(1));
+  };
----------------
Use isBitwiseNot / getBitwiseNotOperand ?


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  https://reviews.llvm.org/D145143/new/

https://reviews.llvm.org/D145143