[PATCH] D143283: [AArch64][SVE]: custom lower AVGFloor/AVGCeil.

Thu Mar 2 00:21:56 PST 2023

dmgreen added inline comments.

================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:13399
+  KnownBits Known = DAG.computeKnownBits(Node, 0);
+  APInt RequiredZero(SzInBits, 0);
+  RequiredZero.setBitsFrom(SzInBits/2);
----------------
hassnaa-arm wrote:
> dmgreen wrote:
> > I believe this only needs 1 bit to be zero, so it could probably use Known.Zero.isSignBitSet()?
> > There is a proof in https://alive2.llvm.org/ce/z/cEtdJa for rhadd.
> Is that because the sign bit will be known to be zero ONLY for zero-extend case ?
> 
Oh right. I was assuming that it would use `if (!IsSigned && IsZeroExtended(OpA) && IsZeroExtended(OpB))` and `if (IsSigned && IsSignExtended(OpA) && IsSignExtended(OpB))`

An hadd / rhadd is defined as converting into a arbitrary wide integer before doing the add/shift and then converting back. It just happens that it only needs 1 bit extra for that to be equivalent to any other type sizes. So we only need to check the top bit is known to be 0. (isSignBitSet doesnt really have anything to do with signedness here, its just a way of checking the top bit).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143283/new/

https://reviews.llvm.org/D143283