[PATCH] D145143: [DAGCombiner] Add fold for `~x & x` -> `0`

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n created this revision.
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This is generally done by the InstCombine, but can be emitted as an
intermediate step and is cheap to handle.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D145143

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/X86/andn-x-x.ll


Index: llvm/test/CodeGen/X86/andn-x-x.ll
===================================================================
--- llvm/test/CodeGen/X86/andn-x-x.ll
+++ llvm/test/CodeGen/X86/andn-x-x.ll
@@ -4,7 +4,7 @@
 define <2 x i64> @andnp_xx(<2 x i64> %v0) nounwind {
 ; CHECK-LABEL: andnp_xx:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    andnps %xmm0, %xmm0
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %x = xor <2 x i64> %v0, <i64 -1, i64 -1>
   %y = and <2 x i64> %v0, %x
@@ -14,7 +14,7 @@
 define <2 x i64> @andnp_xx_2(<2 x i64> %v0) nounwind {
 ; CHECK-LABEL: andnp_xx_2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    andnps %xmm0, %xmm0
+; CHECK-NEXT:    xorps %xmm0, %xmm0
 ; CHECK-NEXT:    retq
   %x = xor <2 x i64> %v0, <i64 -1, i64 -1>
   %y = and <2 x i64> %x, %v0
@@ -24,9 +24,7 @@
 define i64 @andn_xx(i64 %v0) nounwind {
 ; CHECK-LABEL: andn_xx:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movq %rdi, %rax
-; CHECK-NEXT:    notq %rax
-; CHECK-NEXT:    andq %rdi, %rax
+; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    retq
   %x = xor i64 %v0, -1
   %y = and i64 %v0, %x
@@ -36,9 +34,7 @@
 define i64 @andn_xx_2(i64 %v0) nounwind {
 ; CHECK-LABEL: andn_xx_2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movq %rdi, %rax
-; CHECK-NEXT:    notq %rax
-; CHECK-NEXT:    andq %rdi, %rax
+; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    retq
   %x = xor i64 %v0, -1
   %y = and i64 %x, %v0
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -6625,6 +6625,14 @@
       !DAG.isConstantIntBuildVectorOrConstantInt(N1))
     return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
 
+  auto IsAndnXX = [](SDValue Op0, SDValue Op1) {
+    return Op0.getOpcode() == ISD::XOR && Op0.getOperand(0) == Op1 &&
+           isAllOnesOrAllOnesSplat(Op0.getOperand(1));
+  };
+  if (IsAndnXX(N0, N1) || IsAndnXX(N1, N0))
+    return DAG.getConstant(APInt::getZero(N1.getScalarValueSizeInBits()),
+                           SDLoc(N), N1.getValueType());
+
   // fold vector ops
   if (VT.isVector()) {
     if (SDValue FoldedVOp = SimplifyVBinOp(N, SDLoc(N)))


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