[PATCH] D143283: [AArch64][SVE]: custom lower AVGFloor/AVGCeil.

[hassnaaHamdi via Phabricator via llvm-commits]

hassnaa-arm marked 5 inline comments as done.
hassnaa-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:13399
+  KnownBits Known = DAG.computeKnownBits(Node, 0);
+  APInt RequiredZero(SzInBits, 0);
+  RequiredZero.setBitsFrom(SzInBits/2);
----------------
dmgreen wrote:
> I believe this only needs 1 bit to be zero, so it could probably use Known.Zero.isSignBitSet()?
> There is a proof in https://alive2.llvm.org/ce/z/cEtdJa for rhadd.
Is that because the sign bit will be known to be zero ONLY for zero-extend case ?



================
Comment at: llvm/test/CodeGen/AArch64/sve-hadd.ll:75
   %m = add nsw <vscale x 2 x i64> %s0s, %s1s
-  %s = lshr <vscale x 2 x i64> %m, shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
+  %s = ashr <vscale x 2 x i64> %m, shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
   %s2 = trunc <vscale x 2 x i64> %s to <vscale x 2 x i32>
----------------
dmgreen wrote:
> This ideally shouldn't change. Because the top bit isn't demanded instcombine will transform ashr into lshr, and we should be testing what the backend will see: https://godbolt.org/z/bvof8j7cc. I guess the lshr version isn't transformed after it gets promoted? It might be OK in this case.
But for some cases, using lshr in the IR cause generating extra AND instruction.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143283/new/

https://reviews.llvm.org/D143283