[PATCH] D145002: [DAGCombiner] Make `(zext (sgt X, -1))` -> `(srl (not X), N-1)` work if typeof(zext)!=typeof(X)

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:12706
+  // to do this if we are directly returning the result of the setcc which goes
+  // into i1/i8.
+  if (CC == ISD::SETGT && isAllOnesConstant(Ones) &&
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This is a somewhat x86 specific statement. i8 isn't a legal type on ARM/AArch64/RISC-V so setcc never has i8 type. It will be i1, i32, or i64 on those targets.

So what's special about i8 setcc on x86 that's different than the larger i32, i64 types on other targets?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145002/new/

https://reviews.llvm.org/D145002