[PATCH] D143283: [AArch64][SVE]: custom lower AVGFloor/AVGCeil.

[hassnaaHamdi via Phabricator via llvm-commits]

hassnaa-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:13402
+    APInt ApintTemp;
+    if (ISD::isConstantSplatVector(OpA.getOperand(1).getNode(), ApintTemp)) {
+      SDValue Add = DAG.getNode(ISD::ADD, dl, VT, OpA, OpB);
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sdesmalen wrote:
> This is missing a check to ensure that the `and` value is a mask, and that the masked 'type' is smaller than the size of the current type.
> Perhaps you can get some inspiration from `isExtendOrShiftOperand` which checks whether the operation is zero or sign-extended.
> 
> In either case, it would be nice to have this logic in separate `isSignedExtended()` and `isZeroExtended()` functions.
I used DAG.ComputeNumSignBits instead of computeKnownBits, because computeKnownBits doesn't get any known bits for SIGN_EXTEND_INREG


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Comment at: llvm/test/CodeGen/AArch64/sve-hadd.ll:104
 
 define <vscale x 4 x i32> @hadds_v4i32(<vscale x 4 x i32> %s0, <vscale x 4 x i32> %s1) {
+; SVE-LABEL: hadds_v4i32:
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@dmgreen I tried to get alive proofs for this transform,
https://alive2.llvm.org/ce/
but it seems there is something wrong.
I'm not sure if the problem related to my equivalent IR to the generated code or the problem is because the transform is not correct.


Repository:
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  https://reviews.llvm.org/D143283/new/

https://reviews.llvm.org/D143283