[PATCH] D145022: [RISCV] Add vsseg intrinsic for fixed length vectors

[Luke Lau via Phabricator via llvm-commits]

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These intrinsics are equivalent to the regular @llvm.riscv.vssegNF
intrinsics, only they accept fixed length vectors in their overloaded
types: The regular intrinsics only operate on scalable vectors.
These intrinsics convert the fixed length vectors to scalable ones, and
then lower it on to the regular scalable intrinsic.

This mirrors the intrinsics added in 0803dba7dd998ad073d75a32b65296734c10ae70 <https://reviews.llvm.org/rG0803dba7dd998ad073d75a32b65296734c10ae70>
This will be used in a later patch with the Interleaved Access pass.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D145022

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-segN-store.ll

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