[llvm] 3083b65 - [X86] Revise Alderlake P-Core schedule model
Haohai Wen via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 28 15:39:40 PST 2023
Author: Haohai Wen
Date: 2023-03-01T07:39:30+08:00
New Revision: 3083b65c3494b912e622a006a1b563a7e9f1d508
URL: https://github.com/llvm/llvm-project/commit/3083b65c3494b912e622a006a1b563a7e9f1d508
DIFF: https://github.com/llvm/llvm-project/commit/3083b65c3494b912e622a006a1b563a7e9f1d508.diff
LOG: [X86] Revise Alderlake P-Core schedule model
The previous Alderlake P-Core model prefer data from uops.info than intel doc.
Some measures latency from uops.info is larger than real latency. e.g. addpd
latency is 3 in uops.info while 2 in intel doc. This patch adjust the priority
of those two data source so that intel doc is more preferable.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D144388
Added:
Modified:
llvm/lib/Target/X86/X86SchedAlderlakeP.td
llvm/test/tools/llvm-mca/X86/AlderlakeP/independent-load-stores.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-aes.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx1.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx2.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avxgfni.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avxvnni.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi1.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi2.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clflushopt.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clwb.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-cmov.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-f16c.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-fma.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-lea.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-mmx.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-pclmul.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse1.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse2.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse3.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse41.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse42.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-ssse3.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-vaes.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-vpclmulqdq.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_64.s
llvm/test/tools/llvm-mca/X86/AlderlakeP/zero-idioms.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86SchedAlderlakeP.td b/llvm/lib/Target/X86/X86SchedAlderlakeP.td
index 2cf5c6fe9f46..3817eb0fc326 100644
--- a/llvm/lib/Target/X86/X86SchedAlderlakeP.td
+++ b/llvm/lib/Target/X86/X86SchedAlderlakeP.td
@@ -54,6 +54,7 @@ def ADLPPort00_01_05 : ProcResGroup<[ADLPPort00, ADLPPort01, ADLPPort05]>;
def ADLPPort00_01_05_06 : ProcResGroup<[ADLPPort00, ADLPPort01, ADLPPort05, ADLPPort06]>;
def ADLPPort00_05 : ProcResGroup<[ADLPPort00, ADLPPort05]>;
def ADLPPort00_05_06 : ProcResGroup<[ADLPPort00, ADLPPort05, ADLPPort06]>;
+def ADLPPort00_05_06_10 : ProcResGroup<[ADLPPort00, ADLPPort05, ADLPPort06, ADLPPort10]>;
def ADLPPort00_06 : ProcResGroup<[ADLPPort00, ADLPPort06]>;
def ADLPPort01_05 : ProcResGroup<[ADLPPort01, ADLPPort05]>;
def ADLPPort01_05_10 : ProcResGroup<[ADLPPort01, ADLPPort05, ADLPPort10]>;
@@ -123,66 +124,66 @@ multiclass ADLPWriteResPair<X86FoldableSchedWrite SchedRW,
// Infered SchedWrite definition.
def : WriteRes<WriteADC, [ADLPPort00_06]>;
defm : X86WriteRes<WriteADCLd, [ADLPPort00_01_05_06_10, ADLPPort00_06], 11, [1, 1], 2>;
-defm : ADLPWriteResPair<WriteAESDecEnc, [ADLPPort00_01], 5, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteAESIMC, [ADLPPort00_01], 8, [2], 2, 7>;
+defm : ADLPWriteResPair<WriteAESDecEnc, [ADLPPort00_01], 3, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteAESIMC, [ADLPPort00_01], 6, [2], 2, 8>;
defm : X86WriteRes<WriteAESKeyGen, [ADLPPort00, ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05, ADLPPort05], 7, [4, 1, 1, 2, 3, 3], 14>;
defm : X86WriteRes<WriteAESKeyGenLd, [ADLPPort00, ADLPPort00_01, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05], 12, [4, 1, 2, 3, 1, 3], 14>;
def : WriteRes<WriteALU, [ADLPPort00_01_05_06_10]>;
def : WriteRes<WriteALULd, [ADLPPort00_01_05_06_10]> {
- let Latency = 11;
+ let Latency = 6;
}
-defm : ADLPWriteResPair<WriteBEXTR, [ADLPPort00_06, ADLPPort01], 6, [1, 1], 2>;
-defm : ADLPWriteResPair<WriteBLS, [ADLPPort01_05_10], 2, [1]>;
+defm : ADLPWriteResPair<WriteBEXTR, [ADLPPort00_06, ADLPPort01], 2, [1, 1], 2>;
+defm : ADLPWriteResPair<WriteBLS, [ADLPPort01_05_10], 1, [1]>;
defm : ADLPWriteResPair<WriteBSF, [ADLPPort01], 3, [1]>;
defm : ADLPWriteResPair<WriteBSR, [ADLPPort01], 3, [1]>;
-def : WriteRes<WriteBSWAP32, [ADLPPort01]>;
+def : WriteRes<WriteBSWAP32, [ADLPPort00_01_05_06_10]>;
defm : X86WriteRes<WriteBSWAP64, [ADLPPort00_06, ADLPPort01], 2, [1, 1], 2>;
-defm : ADLPWriteResPair<WriteBZHI, [ADLPPort01], 3, [1]>;
+defm : ADLPWriteResPair<WriteBZHI, [ADLPPort01], 1, [1]>;
def : WriteRes<WriteBitTest, [ADLPPort01]>;
defm : X86WriteRes<WriteBitTestImmLd, [ADLPPort01, ADLPPort02_03_11], 6, [1, 1], 2>;
defm : X86WriteRes<WriteBitTestRegLd, [ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11], 11, [4, 2, 1, 2, 1], 10>;
def : WriteRes<WriteBitTestSet, [ADLPPort01]>;
def : WriteRes<WriteBitTestSetImmLd, [ADLPPort01]> {
- let Latency = 11;
+ let Latency = 6;
}
defm : X86WriteRes<WriteBitTestSetRegLd, [ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10], 17, [3, 2, 1, 2], 8>;
-defm : ADLPWriteResPair<WriteBlend, [ADLPPort01_05], 1, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteBlendY, [ADLPPort00_01_05], 1, [1], 1, 8>;
-defm : ADLPWriteResPair<WriteCLMul, [ADLPPort05], 3, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteCMOV, [ADLPPort00_06], 1, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteBlend, [ADLPPort01_05], 1, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteBlendY, [ADLPPort00_01_05], 1, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteCLMul, [ADLPPort05], 3, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteCMOV, [ADLPPort00_06], 2, [2], 1, 4>;
defm : X86WriteRes<WriteCMPXCHG, [ADLPPort00_01_05_06_10, ADLPPort00_06], 3, [3, 2], 5>;
defm : X86WriteRes<WriteCMPXCHGRMW, [ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08], 12, [1, 2, 1, 1, 1], 6>;
defm : ADLPWriteResPair<WriteCRC32, [ADLPPort01], 3, [1]>;
defm : X86WriteRes<WriteCvtI2PD, [ADLPPort00_01, ADLPPort05], 5, [1, 1], 2>;
-defm : X86WriteRes<WriteCvtI2PDLd, [ADLPPort00_01, ADLPPort02_03_11], 11, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtI2PDLd, [ADLPPort00_01, ADLPPort02_03_11], 10, [1, 1], 2>;
defm : X86WriteRes<WriteCvtI2PDY, [ADLPPort00_01, ADLPPort05], 7, [1, 1], 2>;
defm : X86WriteRes<WriteCvtI2PDYLd, [ADLPPort00_01, ADLPPort02_03_11], 12, [1, 1], 2>;
defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
-defm : ADLPWriteResPair<WriteCvtI2PS, [ADLPPort00_01], 4, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteCvtI2PSY, [ADLPPort00_01], 4, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteCvtI2PS, [ADLPPort00_01], 4, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteCvtI2PSY, [ADLPPort00_01], 4, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
defm : X86WriteRes<WriteCvtI2SD, [ADLPPort00_01, ADLPPort05], 7, [1, 1], 2>;
defm : X86WriteRes<WriteCvtI2SDLd, [ADLPPort00_01, ADLPPort02_03_11], 11, [1, 1], 2>;
defm : X86WriteRes<WriteCvtI2SS, [ADLPPort00_01, ADLPPort05], 7, [1, 1], 2>;
defm : X86WriteRes<WriteCvtI2SSLd, [ADLPPort00_01, ADLPPort02_03_11], 11, [1, 1], 2>;
-defm : ADLPWriteResPair<WriteCvtPD2I, [ADLPPort00_01, ADLPPort05], 5, [1, 1], 2, 7>;
-defm : ADLPWriteResPair<WriteCvtPD2IY, [ADLPPort00_01, ADLPPort05], 7, [1, 1], 2, 8>;
+defm : ADLPWriteResPair<WriteCvtPD2I, [ADLPPort00_01, ADLPPort05], 5, [1, 1], 2, 6>;
+defm : ADLPWriteResPair<WriteCvtPD2IY, [ADLPPort00_01, ADLPPort05], 7, [1, 1], 2, 7>;
defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
defm : ADLPWriteResPair<WriteCvtPD2PS, [ADLPPort00_01, ADLPPort05], 5, [1, 1], 2, 7>;
-defm : ADLPWriteResPair<WriteCvtPD2PSY, [ADLPPort00_01, ADLPPort05], 7, [1, 1], 2, 8>;
+defm : ADLPWriteResPair<WriteCvtPD2PSY, [ADLPPort00_01, ADLPPort05], 7, [1, 1], 2, 7>;
defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
defm : X86WriteRes<WriteCvtPH2PS, [ADLPPort00_01, ADLPPort05], 6, [1, 1], 2>;
-defm : X86WriteRes<WriteCvtPH2PSLd, [ADLPPort00_01, ADLPPort02_03_11], 12, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtPH2PSLd, [ADLPPort00_01, ADLPPort02_03_11], 11, [1, 1], 2>;
defm : X86WriteRes<WriteCvtPH2PSY, [ADLPPort00_01, ADLPPort05], 8, [1, 1], 2>;
defm : X86WriteRes<WriteCvtPH2PSYLd, [ADLPPort00_01, ADLPPort02_03_11], 12, [1, 1], 2>;
defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>;
-defm : ADLPWriteResPair<WriteCvtPS2I, [ADLPPort00_01], 4, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteCvtPS2IY, [ADLPPort00_01], 4, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteCvtPS2I, [ADLPPort00_01], 4, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteCvtPS2IY, [ADLPPort00_01], 4, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
defm : X86WriteRes<WriteCvtPS2PD, [ADLPPort00_01, ADLPPort05], 5, [1, 1], 2>;
-defm : X86WriteRes<WriteCvtPS2PDLd, [ADLPPort00_01, ADLPPort02_03_11], 11, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtPS2PDLd, [ADLPPort00_01, ADLPPort02_03_11], 10, [1, 1], 2>;
defm : X86WriteRes<WriteCvtPS2PDY, [ADLPPort00_01, ADLPPort05], 7, [1, 1], 2>;
-defm : X86WriteRes<WriteCvtPS2PDYLd, [ADLPPort00_01, ADLPPort02_03_11], 12, [1, 1], 2>;
+defm : X86WriteRes<WriteCvtPS2PDYLd, [ADLPPort00_01, ADLPPort02_03_11], 11, [1, 1], 2>;
defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
defm : X86WriteRes<WriteCvtPS2PH, [ADLPPort00_01, ADLPPort05], 6, [1, 1], 2>;
defm : X86WriteRes<WriteCvtPS2PHSt, [ADLPPort00_01, ADLPPort04_09, ADLPPort07_08], 12, [1, 1, 1], 3>;
@@ -195,105 +196,112 @@ defm : ADLPWriteResPair<WriteCvtSD2SS, [ADLPPort00_01, ADLPPort05], 5, [1, 1], 2
defm : ADLPWriteResPair<WriteCvtSS2I, [ADLPPort00, ADLPPort00_01], 7, [1, 1], 2>;
defm : X86WriteRes<WriteCvtSS2SD, [ADLPPort00_01, ADLPPort05], 5, [1, 1], 2>;
defm : X86WriteRes<WriteCvtSS2SDLd, [ADLPPort00_01, ADLPPort02_03_11], 11, [1, 1], 2>;
-defm : ADLPWriteResPair<WriteDPPD, [ADLPPort00_01, ADLPPort01_05], 9, [2, 1], 3, 7>;
+defm : ADLPWriteResPair<WriteDPPD, [ADLPPort00_01, ADLPPort01_05], 9, [2, 1], 3, 6>;
defm : ADLPWriteResPair<WriteDPPS, [ADLPPort00_01, ADLPPort00_06, ADLPPort01_05, ADLPPort05], 14, [2, 1, 2, 1], 6, 7>;
defm : ADLPWriteResPair<WriteDPPSY, [ADLPPort00_01, ADLPPort00_06, ADLPPort01_05, ADLPPort05], 14, [2, 1, 2, 1], 6, 8>;
defm : ADLPWriteResPair<WriteDiv16, [ADLPPort00_01_05_06_10, ADLPPort01], 16, [1, 3], 4, 4>;
defm : ADLPWriteResPair<WriteDiv32, [ADLPPort00_01_05_06_10, ADLPPort01], 15, [1, 3], 4, 4>;
-defm : ADLPWriteResPair<WriteDiv64, [ADLPPort01], 18, [3], 3>;
-defm : X86WriteRes<WriteDiv8, [ADLPPort01], 17, [3], 3>;
-defm : X86WriteRes<WriteDiv8Ld, [ADLPPort01], 22, [3], 3>;
+defm : X86WriteRes<WriteDiv64, [ADLPPort00_01_05_06_10, ADLPPort01], 18, [1, 3], 5>;
+defm : X86WriteRes<WriteDiv64Ld, [ADLPPort00_01_05_06_10, ADLPPort01, ADLPPort02_03_11], 23, [1, 3, 1], 5>;
+defm : ADLPWriteResPair<WriteDiv8, [ADLPPort00_01_05_06_10, ADLPPort01], 17, [1, 3], 4>;
defm : X86WriteRes<WriteEMMS, [ADLPPort00, ADLPPort00_05, ADLPPort00_06], 10, [1, 8, 1], 10>;
def : WriteRes<WriteFAdd, [ADLPPort05]> {
let Latency = 3;
}
-defm : X86WriteRes<WriteFAddLd, [ADLPPort01_05, ADLPPort02_03_11], 10, [1, 1], 2>;
+defm : X86WriteRes<WriteFAddLd, [ADLPPort02_03, ADLPPort05], 10, [1, 1], 2>;
defm : ADLPWriteResPair<WriteFAdd64, [ADLPPort01_05], 3, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteFAdd64X, [ADLPPort01_05], 3, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteFAdd64Y, [ADLPPort01_05], 3, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteFAdd64X, [ADLPPort01_05], 2, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFAdd64Y, [ADLPPort01_05], 2, [1], 1, 8>;
defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
-defm : ADLPWriteResPair<WriteFAddX, [ADLPPort01_05], 3, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteFAddY, [ADLPPort01_05], 3, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteFAddX, [ADLPPort01_05], 2, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFAddY, [ADLPPort01_05], 2, [1], 1, 8>;
defm : X86WriteResPairUnsupported<WriteFAddZ>;
-defm : ADLPWriteResPair<WriteFBlend, [ADLPPort00_01_05], 1, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteFBlendY, [ADLPPort00_01_05], 1, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteFBlend, [ADLPPort00_01_05], 1, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteFBlendY, [ADLPPort00_01_05], 1, [1], 1, 7>;
def : WriteRes<WriteFCMOV, [ADLPPort01]> {
let Latency = 3;
}
defm : ADLPWriteResPair<WriteFCmp, [ADLPPort00_01], 4, [1], 1, 7>;
defm : ADLPWriteResPair<WriteFCmp64, [ADLPPort00_01], 4, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteFCmp64X, [ADLPPort00_01], 4, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteFCmp64Y, [ADLPPort00_01], 4, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteFCmp64X, [ADLPPort00_01], 4, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteFCmp64Y, [ADLPPort00_01], 4, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
-defm : ADLPWriteResPair<WriteFCmpX, [ADLPPort00_01], 4, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteFCmpY, [ADLPPort00_01], 4, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteFCmpX, [ADLPPort00_01], 4, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteFCmpY, [ADLPPort00_01], 4, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteFCmpZ>;
def : WriteRes<WriteFCom, [ADLPPort05]>;
defm : X86WriteRes<WriteFComLd, [ADLPPort02_03, ADLPPort05], 8, [1, 1], 2>;
-defm : ADLPWriteResPair<WriteFComX, [ADLPPort00], 3, [1]>;
-defm : ADLPWriteResPair<WriteFDiv, [ADLPPort00], 11, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFComX, [ADLPPort00], 3, [1], 1, 6>;
+def : WriteRes<WriteFDiv, [ADLPPort00]> {
+ let Latency = 11;
+}
+defm : X86WriteRes<WriteFDivLd, [ADLPPort00, ADLPPort02_03], 27, [1, 1], 2>;
defm : ADLPWriteResPair<WriteFDiv64, [ADLPPort00], 14, [1]>;
defm : ADLPWriteResPair<WriteFDiv64X, [ADLPPort00], 14, [1], 1, 6>;
defm : ADLPWriteResPair<WriteFDiv64Y, [ADLPPort00], 14, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
-defm : ADLPWriteResPair<WriteFDivX, [ADLPPort00], 11, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteFDivY, [ADLPPort00], 11, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteFDivX, [ADLPPort00], 11, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteFDivY, [ADLPPort00], 11, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteFDivZ>;
-defm : ADLPWriteResPair<WriteFHAdd, [ADLPPort01_05, ADLPPort05], 6, [1, 2], 3, 6>;
-defm : ADLPWriteResPair<WriteFHAddY, [ADLPPort01_05, ADLPPort05], 5, [1, 2], 3, 8>;
+defm : ADLPWriteResPair<WriteFHAdd, [ADLPPort01_05, ADLPPort05], 5, [1, 2], 3, 6>;
+defm : ADLPWriteResPair<WriteFHAddY, [ADLPPort01_05, ADLPPort05], 5, [1, 2], 3, 7>;
def : WriteRes<WriteFLD0, [ADLPPort00_05]>;
defm : X86WriteRes<WriteFLD1, [ADLPPort00_05], 1, [2], 2>;
defm : X86WriteRes<WriteFLDC, [ADLPPort00_05], 1, [2], 2>;
def : WriteRes<WriteFLoad, [ADLPPort02_03_11]> {
- let Latency = 7;
+ let Latency = 6;
}
def : WriteRes<WriteFLoadX, [ADLPPort02_03_11]> {
- let Latency = 7;
+ let Latency = 6;
}
def : WriteRes<WriteFLoadY, [ADLPPort02_03_11]> {
- let Latency = 8;
+ let Latency = 7;
}
-defm : ADLPWriteResPair<WriteFLogic, [ADLPPort00_01_05], 1, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteFLogicY, [ADLPPort00_01_05], 1, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteFLogic, [ADLPPort00_01_05], 1, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteFLogicY, [ADLPPort00_01_05], 1, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteFLogicZ>;
defm : ADLPWriteResPair<WriteFMA, [ADLPPort00_01], 4, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteFMAX, [ADLPPort00_01], 4, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteFMAY, [ADLPPort00_01], 4, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteFMAX, [ADLPPort00_01], 4, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteFMAY, [ADLPPort00_01], 4, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteFMAZ>;
def : WriteRes<WriteFMOVMSK, [ADLPPort00]> {
let Latency = 3;
}
-defm : X86WriteRes<WriteFMaskedLoad, [ADLPPort00_01_05, ADLPPort02_03_11], 8, [1, 1], 2>;
-defm : X86WriteRes<WriteFMaskedLoadY, [ADLPPort00_01_05, ADLPPort02_03_11], 9, [1, 1], 2>;
-defm : X86WriteRes<WriteFMaskedStore32, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;
-defm : X86WriteRes<WriteFMaskedStore32Y, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;
-defm : X86WriteRes<WriteFMaskedStore64, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;
-defm : X86WriteRes<WriteFMaskedStore64Y, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;
-defm : X86WriteRes<WriteFMoveX, [], 1, [], 0>;
-defm : X86WriteRes<WriteFMoveY, [], 1, [], 0>;
+defm : X86WriteRes<WriteFMaskedLoad, [ADLPPort00_01_05, ADLPPort02_03_11], 7, [1, 1], 2>;
+defm : X86WriteRes<WriteFMaskedLoadY, [ADLPPort00_01_05, ADLPPort02_03_11], 8, [1, 1], 2>;
+defm : X86WriteRes<WriteFMaskedStore32, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 3, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteFMaskedStore32Y, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 3, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteFMaskedStore64, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 3, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteFMaskedStore64Y, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 3, [1, 1, 1], 3>;
+def : WriteRes<WriteFMoveX, [ADLPPort00_01_05]> {
+ let Latency = 0;
+}
+def : WriteRes<WriteFMoveY, [ADLPPort00_01_05]> {
+ let Latency = 0;
+}
defm : X86WriteResUnsupported<WriteFMoveZ>;
defm : ADLPWriteResPair<WriteFMul, [ADLPPort00_01], 4, [1], 1, 7>;
defm : ADLPWriteResPair<WriteFMul64, [ADLPPort00_01], 4, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteFMul64X, [ADLPPort00_01], 4, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteFMul64Y, [ADLPPort00_01], 4, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteFMul64X, [ADLPPort00_01], 4, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteFMul64Y, [ADLPPort00_01], 4, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteFMul64Z>;
-defm : ADLPWriteResPair<WriteFMulX, [ADLPPort00_01], 4, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteFMulY, [ADLPPort00_01], 4, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteFMulX, [ADLPPort00_01], 4, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteFMulY, [ADLPPort00_01], 4, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteFMulZ>;
defm : ADLPWriteResPair<WriteFRcp, [ADLPPort00], 4, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteFRcpX, [ADLPPort00], 4, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteFRcpY, [ADLPPort00], 4, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteFRcpX, [ADLPPort00], 4, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteFRcpY, [ADLPPort00], 4, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteFRcpZ>;
-defm : ADLPWriteResPair<WriteFRnd, [ADLPPort00_01], 8, [2], 2, 7>;
-defm : ADLPWriteResPair<WriteFRndY, [ADLPPort00_01], 8, [2], 2, 8>;
+defm : ADLPWriteResPair<WriteFRnd, [ADLPPort00_01], 8, [2], 2, 6>;
+defm : ADLPWriteResPair<WriteFRndY, [ADLPPort00_01], 8, [2], 2, 7>;
defm : X86WriteResPairUnsupported<WriteFRndZ>;
defm : ADLPWriteResPair<WriteFRsqrt, [ADLPPort00], 4, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteFRsqrtX, [ADLPPort00], 4, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteFRsqrtY, [ADLPPort00], 4, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteFRsqrtX, [ADLPPort00], 4, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteFRsqrtY, [ADLPPort00], 4, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
-defm : ADLPWriteResPair<WriteFShuffle, [ADLPPort05], 1, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteFShuffle256, [ADLPPort05], 3, [1], 1, 8>;
-defm : ADLPWriteResPair<WriteFShuffleY, [ADLPPort05], 1, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteFShuffle, [ADLPPort05], 1, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteFShuffle256, [ADLPPort05], 3, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFShuffleY, [ADLPPort05], 1, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
def : WriteRes<WriteFSign, [ADLPPort00]>;
defm : ADLPWriteResPair<WriteFSqrt, [ADLPPort00], 12, [1], 1, 7>;
@@ -305,32 +313,32 @@ def : WriteRes<WriteFSqrt80, [ADLPPortInvalid, ADLPPort00]> {
let ResourceCycles = [7, 1];
let Latency = 21;
}
-defm : ADLPWriteResPair<WriteFSqrtX, [ADLPPort00], 12, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteFSqrtY, [ADLPPort00], 12, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteFSqrtX, [ADLPPort00], 12, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteFSqrtY, [ADLPPort00], 12, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
-defm : X86WriteRes<WriteFStore, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;
+defm : X86WriteRes<WriteFStore, [ADLPPort04_09, ADLPPort07_08], 1, [1, 1], 2>;
defm : X86WriteResUnsupported<WriteFStoreNT>;
defm : X86WriteRes<WriteFStoreNTX, [ADLPPort04_09, ADLPPort07_08], 518, [1, 1], 2>;
defm : X86WriteRes<WriteFStoreNTY, [ADLPPort04_09, ADLPPort07_08], 542, [1, 1], 2>;
-defm : X86WriteRes<WriteFStoreX, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;
-defm : X86WriteRes<WriteFStoreY, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;
+defm : X86WriteRes<WriteFStoreX, [ADLPPort04_09, ADLPPort07_08], 1, [1, 1], 2>;
+defm : X86WriteRes<WriteFStoreY, [ADLPPort04_09, ADLPPort07_08], 1, [1, 1], 2>;
defm : ADLPWriteResPair<WriteFTest, [ADLPPort00], 3, [1]>;
defm : ADLPWriteResPair<WriteFTestY, [ADLPPort00], 5, [1], 1, 6>;
defm : ADLPWriteResPair<WriteFVarBlend, [ADLPPort00_01_05], 1, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteFVarBlendY, [ADLPPort00_01_05], 3, [3], 3, 7>;
+defm : ADLPWriteResPair<WriteFVarBlendY, [ADLPPort00_01_05], 3, [3], 3, 6>;
defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
-defm : ADLPWriteResPair<WriteFVarShuffle, [ADLPPort05], 1, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteFVarShuffle256, [ADLPPort05], 3, [1], 1, 8>;
-defm : ADLPWriteResPair<WriteFVarShuffleY, [ADLPPort05], 1, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteFVarShuffle, [ADLPPort05], 1, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteFVarShuffle256, [ADLPPort05], 3, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteFVarShuffleY, [ADLPPort05], 1, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
def : WriteRes<WriteFence, [ADLPPort00_06]> {
let Latency = 2;
}
defm : ADLPWriteResPair<WriteIDiv16, [ADLPPort00_01_05_06_10, ADLPPort01], 16, [1, 3], 4, 4>;
defm : ADLPWriteResPair<WriteIDiv32, [ADLPPort00_01_05_06_10, ADLPPort01], 15, [1, 3], 4, 4>;
-defm : ADLPWriteResPair<WriteIDiv64, [ADLPPort01], 18, [3], 3>;
-defm : X86WriteRes<WriteIDiv8, [ADLPPort01], 17, [3], 3>;
-defm : X86WriteRes<WriteIDiv8Ld, [ADLPPort01], 22, [3], 3>;
+defm : X86WriteRes<WriteIDiv64, [ADLPPort00_01_05_06_10, ADLPPort01], 18, [1, 3], 5>;
+defm : X86WriteRes<WriteIDiv64Ld, [ADLPPort00_01_05_06_10, ADLPPort01, ADLPPort02_03_11], 23, [1, 3, 1], 5>;
+defm : ADLPWriteResPair<WriteIDiv8, [ADLPPort00_01_05_06_10, ADLPPort01], 17, [1, 3], 4>;
defm : ADLPWriteResPair<WriteIMul16, [ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01], 5, [2, 1, 1], 4>;
defm : ADLPWriteResPair<WriteIMul16Imm, [ADLPPort00_01_05_06_10, ADLPPort01], 4, [1, 1], 2>;
defm : ADLPWriteResPair<WriteIMul16Reg, [ADLPPort01], 3, [1]>;
@@ -352,8 +360,8 @@ defm : X86WriteRes<WriteJumpLd, [ADLPPort00_06, ADLPPort02_03], 6, [1, 1], 2>;
def : WriteRes<WriteLAHFSAHF, [ADLPPort00_06]> {
let Latency = 3;
}
-defm : X86WriteRes<WriteLDMXCSR, [ADLPPort00, ADLPPort00_01_05, ADLPPort00_06, ADLPPort02_03_11], 7, [1, 1, 1, 1], 4>;
-def : WriteRes<WriteLEA, [ADLPPort01]>;
+defm : X86WriteRes<WriteLDMXCSR, [ADLPPort00, ADLPPort00_01_05, ADLPPort02_03_11, ADLPPort06], 7, [1, 1, 1, 1], 4>;
+def : WriteRes<WriteLEA, [ADLPPort00_01_05_06_10]>;
defm : ADLPWriteResPair<WriteLZCNT, [ADLPPort01], 3, [1]>;
def : WriteRes<WriteLoad, [ADLPPort02_03_11]> {
let Latency = 5;
@@ -361,8 +369,8 @@ def : WriteRes<WriteLoad, [ADLPPort02_03_11]> {
def : WriteRes<WriteMMXMOVMSK, [ADLPPort00]> {
let Latency = 3;
}
-defm : ADLPWriteResPair<WriteMPSAD, [ADLPPort01_05, ADLPPort05], 4, [1, 1], 2, 7>;
-defm : ADLPWriteResPair<WriteMPSADY, [ADLPPort01_05, ADLPPort05], 4, [1, 1], 2, 8>;
+defm : ADLPWriteResPair<WriteMPSAD, [ADLPPort01_05, ADLPPort05], 4, [1, 1], 2, 6>;
+defm : ADLPWriteResPair<WriteMPSADY, [ADLPPort01_05, ADLPPort05], 4, [1, 1], 2, 7>;
defm : ADLPWriteResPair<WriteMULX32, [ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01], 4, [1, 1, 1], 2>;
defm : ADLPWriteResPair<WriteMULX64, [ADLPPort01, ADLPPort05], 4, [1, 1]>;
def : WriteRes<WriteMicrocoded, [ADLPPort00_01_05_06]> {
@@ -376,75 +384,76 @@ defm : X86WriteRes<WritePCmpEStrM, [ADLPPort00, ADLPPort00_01_05, ADLPPort00_06,
defm : X86WriteRes<WritePCmpEStrMLd, [ADLPPort00, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05], 17, [3, 2, 1, 1, 1, 1], 9>;
defm : ADLPWriteResPair<WritePCmpIStrI, [ADLPPort00], 11, [3], 3, 20>;
defm : ADLPWriteResPair<WritePCmpIStrM, [ADLPPort00], 11, [3], 3>;
-defm : ADLPWriteResPair<WritePHAdd, [ADLPPort00_05, ADLPPort05], 3, [1, 2], 3, 8>;
-defm : ADLPWriteResPair<WritePHAddX, [ADLPPort00_01_05, ADLPPort01_05], 2, [1, 2], 3, 7>;
-defm : ADLPWriteResPair<WritePHAddY, [ADLPPort00_01_05, ADLPPort01_05], 2, [1, 2], 3, 8>;
+defm : ADLPWriteResPair<WritePHAdd, [ADLPPort00_05, ADLPPort05], 3, [1, 2], 3, 6>;
+defm : ADLPWriteResPair<WritePHAddX, [ADLPPort00_01_05, ADLPPort01_05], 2, [1, 2], 3, 6>;
+defm : ADLPWriteResPair<WritePHAddY, [ADLPPort00_01_05, ADLPPort01_05], 2, [1, 2], 3, 7>;
defm : ADLPWriteResPair<WritePHMINPOS, [ADLPPort00], 4, [1], 1, 7>;
-defm : ADLPWriteResPair<WritePMULLD, [ADLPPort00_01], 10, [2], 2, 8>;
-defm : ADLPWriteResPair<WritePMULLDY, [ADLPPort00_01], 10, [2], 2, 8>;
+defm : ADLPWriteResPair<WritePMULLD, [ADLPPort00_01], 10, [2], 2, 6>;
+defm : ADLPWriteResPair<WritePMULLDY, [ADLPPort00_01], 10, [2], 2, 7>;
defm : X86WriteResPairUnsupported<WritePMULLDZ>;
defm : ADLPWriteResPair<WritePOPCNT, [ADLPPort01], 3, [1]>;
-defm : ADLPWriteResPair<WritePSADBW, [ADLPPort05], 3, [1], 1, 8>;
-defm : ADLPWriteResPair<WritePSADBWX, [ADLPPort05], 3, [1], 1, 7>;
-defm : ADLPWriteResPair<WritePSADBWY, [ADLPPort05], 3, [1], 1, 8>;
+defm : ADLPWriteResPair<WritePSADBW, [ADLPPort05], 3, [1], 1, 6>;
+defm : ADLPWriteResPair<WritePSADBWX, [ADLPPort05], 3, [1], 1, 6>;
+defm : ADLPWriteResPair<WritePSADBWY, [ADLPPort05], 3, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WritePSADBWZ>;
defm : X86WriteRes<WriteRMW, [ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08], 1, [1, 1, 1], 3>;
defm : X86WriteRes<WriteRotate, [ADLPPort00_01_05_06_10, ADLPPort00_06], 2, [1, 2], 3>;
defm : X86WriteRes<WriteRotateLd, [ADLPPort00_01_05_06_10, ADLPPort00_06], 12, [1, 2], 3>;
-defm : X86WriteRes<WriteRotateCL, [ADLPPort00_06], 2, [2], 2>;
-defm : X86WriteRes<WriteRotateCLLd, [ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01], 19, [2, 3, 2], 7>;
-defm : X86WriteRes<WriteSETCC, [ADLPPort00_06], 2, [2], 2>;
-defm : X86WriteRes<WriteSETCCStore, [ADLPPort00_06, ADLPPort04_09, ADLPPort07_08], 13, [2, 1, 1], 4>;
+defm : X86WriteRes<WriteRotateCL, [ADLPPort00_06], 1, [2], 2>;
+defm : X86WriteRes<WriteRotateCLLd, [ADLPPort00_06], 7, [2], 2>;
+def : WriteRes<WriteSETCC, [ADLPPort00_06]>;
+defm : X86WriteRes<WriteSETCCStore, [ADLPPort00_06, ADLPPort04_09, ADLPPort07_08], 2, [1, 1, 1], 3>;
defm : X86WriteRes<WriteSHDmrcl, [ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08], 12, [1, 1, 1, 1, 1, 1], 6>;
defm : X86WriteRes<WriteSHDmri, [ADLPPort00_01_05_06_10, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08], 12, [1, 1, 1, 1, 1], 5>;
-defm : X86WriteRes<WriteSHDrrcl, [ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01], 5, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteSHDrrcl, [ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01], 4, [1, 1, 1], 3>;
def : WriteRes<WriteSHDrri, [ADLPPort01]> {
let Latency = 3;
}
-defm : X86WriteRes<WriteSTMXCSR, [ADLPPort00, ADLPPort00_06, ADLPPort04_09, ADLPPort07_08], 12, [1, 1, 1, 1], 4>;
+defm : X86WriteRes<WriteSTMXCSR, [ADLPPort00, ADLPPort04_09, ADLPPort06, ADLPPort07_08], 12, [1, 1, 1, 1], 4>;
def : WriteRes<WriteShift, [ADLPPort00_06]>;
def : WriteRes<WriteShiftLd, [ADLPPort00_06]> {
- let Latency = 12;
+ let Latency = 7;
}
-defm : X86WriteRes<WriteShiftCL, [ADLPPort00_06], 2, [2], 2>;
-defm : X86WriteRes<WriteShiftCLLd, [ADLPPort00_06], 12, [2], 2>;
-defm : ADLPWriteResPair<WriteShuffle, [ADLPPort05], 1, [1], 1, 8>;
-defm : ADLPWriteResPair<WriteShuffle256, [ADLPPort05], 3, [1], 1, 8>;
-defm : ADLPWriteResPair<WriteShuffleX, [ADLPPort01_05], 1, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteShuffleY, [ADLPPort01_05], 1, [1], 1, 8>;
+defm : X86WriteRes<WriteShiftCL, [ADLPPort00_06], 1, [2], 2>;
+defm : X86WriteRes<WriteShiftCLLd, [ADLPPort00_06], 7, [2], 2>;
+defm : ADLPWriteResPair<WriteShuffle, [ADLPPort05], 1, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteShuffle256, [ADLPPort05], 3, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteShuffleX, [ADLPPort01_05], 1, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteShuffleY, [ADLPPort01_05], 1, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteShuffleZ>;
-defm : X86WriteRes<WriteStore, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;
+defm : X86WriteRes<WriteStore, [ADLPPort02_03_07, ADLPPort04, ADLPPort05], 4, [1, 1, 1], 3>;
defm : X86WriteRes<WriteStoreNT, [ADLPPort04_09, ADLPPort07_08], 512, [1, 1], 2>;
def : WriteRes<WriteSystem, [ADLPPort00_01_05_06]> {
let Latency = AlderlakePModel.MaxLatency;
}
defm : ADLPWriteResPair<WriteTZCNT, [ADLPPort01], 3, [1]>;
-defm : ADLPWriteResPair<WriteVPMOV256, [ADLPPort05], 3, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteVPMOV256, [ADLPPort05], 3, [1], 1, 7>;
defm : ADLPWriteResPair<WriteVarBlend, [ADLPPort00_01_05], 1, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteVarBlendY, [ADLPPort00_01_05], 3, [3], 3, 7>;
+defm : ADLPWriteResPair<WriteVarBlendY, [ADLPPort00_01_05], 3, [3], 3, 6>;
defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
-defm : ADLPWriteResPair<WriteVarShuffle, [ADLPPort00, ADLPPort05], 3, [1, 1], 2, 8>;
-defm : ADLPWriteResPair<WriteVarShuffle256, [ADLPPort05], 3, [1], 1, 8>;
-defm : ADLPWriteResPair<WriteVarShuffleX, [ADLPPort01_05], 1, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteVarShuffleY, [ADLPPort01_05], 1, [1], 1, 8>;
+defm : X86WriteRes<WriteVarShuffle, [ADLPPort00, ADLPPort05], 3, [1, 1], 3>;
+defm : X86WriteRes<WriteVarShuffleLd, [ADLPPort00, ADLPPort02_03_11, ADLPPort05], 9, [1, 1, 1], 3>;
+defm : ADLPWriteResPair<WriteVarShuffle256, [ADLPPort05], 3, [1], 1, 7>;
+defm : ADLPWriteResPair<WriteVarShuffleX, [ADLPPort01_05], 1, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteVarShuffleY, [ADLPPort01_05], 1, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
-defm : ADLPWriteResPair<WriteVarVecShift, [ADLPPort00_01], 1, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteVarVecShiftY, [ADLPPort00_01], 1, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteVarVecShift, [ADLPPort00_01], 1, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteVarVecShiftY, [ADLPPort00_01], 1, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
-defm : ADLPWriteResPair<WriteVecALU, [ADLPPort00], 1, [1], 1, 8>;
-defm : ADLPWriteResPair<WriteVecALUX, [ADLPPort00_01], 1, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteVecALUY, [ADLPPort00_01], 1, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteVecALU, [ADLPPort00], 1, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteVecALUX, [ADLPPort00_01], 1, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteVecALUY, [ADLPPort00_01], 1, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteVecALUZ>;
defm : X86WriteRes<WriteVecExtract, [ADLPPort00, ADLPPort01_05], 4, [1, 1], 2>;
-defm : X86WriteRes<WriteVecExtractSt, [ADLPPort01_05, ADLPPort04_09, ADLPPort07_08], 19, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteVecExtractSt, [ADLPPort01_05, ADLPPort04_09, ADLPPort07_08], 2, [1, 1, 1], 3>;
defm : ADLPWriteResPair<WriteVecIMul, [ADLPPort00], 5, [1], 1, 8>;
-defm : ADLPWriteResPair<WriteVecIMulX, [ADLPPort00_01], 5, [1], 1, 8>;
-defm : ADLPWriteResPair<WriteVecIMulY, [ADLPPort00_01], 5, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteVecIMulX, [ADLPPort00_01], 5, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteVecIMulY, [ADLPPort00_01], 5, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
-defm : X86WriteRes<WriteVecInsert, [ADLPPort01_05, ADLPPort05], 4, [1, 1], 2>;
-defm : X86WriteRes<WriteVecInsertLd, [ADLPPort01_05, ADLPPort02_03_11], 8, [1, 1], 2>;
+defm : X86WriteRes<WriteVecInsert, [ADLPPort01_05, ADLPPort05], 2, [1, 1], 2>;
+defm : X86WriteRes<WriteVecInsertLd, [ADLPPort01_05, ADLPPort02_03_11], 7, [1, 1], 2>;
def : WriteRes<WriteVecLoad, [ADLPPort02_03_11]> {
- let Latency = 7;
+ let Latency = 6;
}
def : WriteRes<WriteVecLoadNT, [ADLPPort02_03_11]> {
let Latency = 7;
@@ -453,14 +462,14 @@ def : WriteRes<WriteVecLoadNTY, [ADLPPort02_03_11]> {
let Latency = 8;
}
def : WriteRes<WriteVecLoadX, [ADLPPort02_03_11]> {
- let Latency = 7;
+ let Latency = 6;
}
def : WriteRes<WriteVecLoadY, [ADLPPort02_03_11]> {
- let Latency = 8;
+ let Latency = 7;
}
-defm : ADLPWriteResPair<WriteVecLogic, [ADLPPort00_05], 1, [1], 1, 8>;
-defm : ADLPWriteResPair<WriteVecLogicX, [ADLPPort00_01_05], 1, [1], 1, 7>;
-defm : ADLPWriteResPair<WriteVecLogicY, [ADLPPort00_01_05], 1, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteVecLogic, [ADLPPort00_05], 1, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteVecLogicX, [ADLPPort00_01_05], 1, [1], 1, 6>;
+defm : ADLPWriteResPair<WriteVecLogicY, [ADLPPort00_01_05], 1, [1], 1, 7>;
defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
def : WriteRes<WriteVecMOVMSK, [ADLPPort00]> {
let Latency = 3;
@@ -469,23 +478,25 @@ def : WriteRes<WriteVecMOVMSKY, [ADLPPort00]> {
let Latency = 4;
}
defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>;
-defm : X86WriteRes<WriteVecMaskedLoad, [ADLPPort00_01_05, ADLPPort02_03_11], 8, [1, 1], 2>;
-defm : X86WriteRes<WriteVecMaskedLoadY, [ADLPPort00_01_05, ADLPPort02_03_11], 9, [1, 1], 2>;
-defm : X86WriteRes<WriteVecMaskedStore32, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;
-defm : X86WriteRes<WriteVecMaskedStore32Y, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;
-defm : X86WriteRes<WriteVecMaskedStore64, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;
-defm : X86WriteRes<WriteVecMaskedStore64Y, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 14, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteVecMaskedLoad, [ADLPPort00_01_05, ADLPPort02_03_11], 7, [1, 1], 2>;
+defm : X86WriteRes<WriteVecMaskedLoadY, [ADLPPort00_01_05, ADLPPort02_03_11], 8, [1, 1], 2>;
+defm : X86WriteRes<WriteVecMaskedStore32, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 3, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteVecMaskedStore32Y, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 3, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteVecMaskedStore64, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 3, [1, 1, 1], 3>;
+defm : X86WriteRes<WriteVecMaskedStore64Y, [ADLPPort00, ADLPPort04_09, ADLPPort07_08], 3, [1, 1, 1], 3>;
def : WriteRes<WriteVecMove, [ADLPPort00_05]>;
-def : WriteRes<WriteVecMoveFromGpr, [ADLPPort05]> {
- let Latency = 3;
-}
+def : WriteRes<WriteVecMoveFromGpr, [ADLPPort05]>;
def : WriteRes<WriteVecMoveToGpr, [ADLPPort00]> {
let Latency = 3;
}
-defm : X86WriteRes<WriteVecMoveX, [], 1, [], 0>;
-defm : X86WriteRes<WriteVecMoveY, [], 1, [], 0>;
+def : WriteRes<WriteVecMoveX, [ADLPPort00_01_05]> {
+ let Latency = 0;
+}
+def : WriteRes<WriteVecMoveY, [ADLPPort00_01_05]> {
+ let Latency = 0;
+}
defm : X86WriteResUnsupported<WriteVecMoveZ>;
-defm : ADLPWriteResPair<WriteVecShift, [ADLPPort00], 1, [1], 1, 8>;
+defm : ADLPWriteResPair<WriteVecShift, [ADLPPort00], 1, [1], 1, 6>;
def : WriteRes<WriteVecShiftImm, [ADLPPort00]>;
def : WriteRes<WriteVecShiftImmX, [ADLPPort00_01]>;
defm : X86WriteResUnsupported<WriteVecShiftImmXLd>;
@@ -493,15 +504,15 @@ def : WriteRes<WriteVecShiftImmY, [ADLPPort00_01]>;
defm : X86WriteResUnsupported<WriteVecShiftImmYLd>;
defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
defm : X86WriteRes<WriteVecShiftX, [ADLPPort00_01, ADLPPort01_05], 2, [1, 1], 2>;
-defm : X86WriteRes<WriteVecShiftXLd, [ADLPPort00_01, ADLPPort02_03_11], 8, [1, 1], 2>;
+defm : X86WriteRes<WriteVecShiftXLd, [ADLPPort00_01, ADLPPort02_03_11], 7, [1, 1], 2>;
defm : X86WriteRes<WriteVecShiftY, [ADLPPort00_01, ADLPPort05], 4, [1, 1], 2>;
-defm : X86WriteRes<WriteVecShiftYLd, [ADLPPort00_01, ADLPPort02_03_11], 9, [1, 1], 2>;
+defm : X86WriteRes<WriteVecShiftYLd, [ADLPPort00_01, ADLPPort02_03_11], 8, [1, 1], 2>;
defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
-defm : X86WriteRes<WriteVecStore, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;
+defm : X86WriteRes<WriteVecStore, [ADLPPort04_09, ADLPPort07_08], 1, [1, 1], 2>;
defm : X86WriteRes<WriteVecStoreNT, [ADLPPort04_09, ADLPPort07_08], 511, [1, 1], 2>;
defm : X86WriteRes<WriteVecStoreNTY, [ADLPPort04_09, ADLPPort07_08], 507, [1, 1], 2>;
-defm : X86WriteRes<WriteVecStoreX, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;
-defm : X86WriteRes<WriteVecStoreY, [ADLPPort04_09, ADLPPort07_08], 12, [1, 1], 2>;
+defm : X86WriteRes<WriteVecStoreX, [ADLPPort04_09, ADLPPort07_08], 1, [1, 1], 2>;
+defm : X86WriteRes<WriteVecStoreY, [ADLPPort04_09, ADLPPort07_08], 1, [1, 1], 2>;
defm : ADLPWriteResPair<WriteVecTest, [ADLPPort00, ADLPPort05], 4, [1, 1], 2>;
defm : ADLPWriteResPair<WriteVecTestY, [ADLPPort00, ADLPPort05], 6, [1, 1], 2, 6>;
defm : X86WriteRes<WriteXCHG, [ADLPPort00_01_05_06_10], 2, [3], 3>;
@@ -509,244 +520,231 @@ def : WriteRes<WriteZero, []>;
// Infered SchedWriteRes and InstRW definition.
-def ADLPWriteResGroup0 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort02_03, ADLPPort02_03_07, ADLPPort04]> {
- let Latency = 7;
- let NumMicroOps = 3;
-}
-def : InstRW<[ADLPWriteResGroup0], (instregex "^AA(D|N)D64mr$",
- "^A(X?)OR64mr$")>;
-
-def ADLPWriteResGroup1 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup0 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [2, 1, 1, 1, 1];
- let Latency = 12;
+ let Latency = 7;
let NumMicroOps = 6;
}
-def : InstRW<[ADLPWriteResGroup1, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(16|32|64)mr$")>;
+def : InstRW<[ADLPWriteResGroup0, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(8|16|32|64)mr$")>;
-def ADLPWriteResGroup2 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
+def ADLPWriteResGroup1 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup2], (instregex "^JMP(16|32|64)m((_NT)?)$",
+def : InstRW<[ADLPWriteResGroup1], (instregex "^JMP(16|32)m$",
+ "^JMP(16|32|64)m_NT$",
"^RET(16|32)$",
"^RORX(32|64)mi$")>;
-def : InstRW<[ADLPWriteResGroup2, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(8|16|32|64)rm$",
+def : InstRW<[ADLPWriteResGroup1, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^S(A|H)RX(32|64)rm$",
+ "^SHLX(32|64)rm$")>;
+def : InstRW<[ADLPWriteResGroup1, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(8|16|32|64)rm$",
"^AD(C|O)X(32|64)rm$")>;
-def ADLPWriteResGroup3 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup2 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 13;
let NumMicroOps = 5;
}
-def : InstRW<[ADLPWriteResGroup3], (instregex "^(ADC|SBB)8mi(8?)$")>;
-
-def ADLPWriteResGroup4 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
- let ResourceCycles = [2, 1, 1, 1, 1];
- let Latency = 13;
- let NumMicroOps = 6;
-}
-def : InstRW<[ADLPWriteResGroup4, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)8mr$")>;
+def : InstRW<[ADLPWriteResGroup2], (instregex "^(ADC|SBB)8mi(8?)$")>;
-def ADLPWriteResGroup5 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup3 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup5], (instregex "^CMP(8|16|32)mi$",
+def : InstRW<[ADLPWriteResGroup3], (instregex "^(CMP|TEST)(8|16|32)mi$",
"^CMP(8|16|32|64)mi8$",
- "^MOV(8|16)rm$",
- "^POP(16|32)r((mr)?)$")>;
-def : InstRW<[ADLPWriteResGroup5], (instrs CMP64mi32,
- MOV8rm_NOREX,
- MOVZX16rm8)>;
-def : InstRW<[ADLPWriteResGroup5, ReadAfterLd], (instregex "^(ADD|CMP|SUB)(8|16|32|64)rm$",
- "^AND(8|16|32)rm$",
- "^(X?)OR(8|16|32)rm$")>;
-def : InstRW<[ADLPWriteResGroup5, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^CMP(8|16|32|64)mr$")>;
-
-def ADLPWriteResGroup6 : SchedWriteRes<[]> {
- let NumMicroOps = 0;
-}
-def : InstRW<[ADLPWriteResGroup6], (instregex "^(ADD|SUB)64ri8$",
- "^(DE|IN)C64r$",
- "^MOV64rr((_REV)?)$")>;
-def : InstRW<[ADLPWriteResGroup6], (instrs CLC,
- JMP_2)>;
-
-def ADLPWriteResGroup7 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+ "^(CMP|TEST)64mi32$",
+ "^MOV(8|16)(rm|ao64)$",
+ "^MOVSX16rm(16|32)$",
+ "^MOVZX16rm(8|16)$",
+ "^POP32r((mr)?)$")>;
+def : InstRW<[ADLPWriteResGroup3], (instrs MOV8rm_NOREX)>;
+def : InstRW<[ADLPWriteResGroup3, ReadAfterLd], (instregex "^A(D|N)D(8|16|32|64)rm$",
+ "^(CMP|SUB)(8|16|32|64)rm$",
+ "^(X?)OR(8|16|32|64)rm$")>;
+def : InstRW<[ADLPWriteResGroup3, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(CMP|TEST)(8|16|32|64)mr$")>;
+
+def ADLPWriteResGroup4 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 13;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup7], (instregex "^A(D|N)D8mi(8?)$",
- "^(DE|IN)C8m$",
- "^N(EG|OT)8m$",
- "^(X?)OR8mi(8?)$",
- "^SUB8mi(8?)$")>;
-def : InstRW<[ADLPWriteResGroup7, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^A(D|N)D8mr$",
- "^(X?)OR8mr$")>;
-def : InstRW<[ADLPWriteResGroup7, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs SUB8mr)>;
+def : InstRW<[ADLPWriteResGroup4], (instregex "^A(D|N)D8mi8$",
+ "^(X?)OR8mi8$")>;
+def : InstRW<[ADLPWriteResGroup4], (instrs SUB8mi8)>;
-def ADLPWriteResGroup8 : SchedWriteRes<[ADLPPort01_05]> {
+def ADLPWriteResGroup5 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
+ let Latency = 10;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup5, ReadAfterVecXLd], (instregex "^(ADD|SUB)PSrm$")>;
+def : InstRW<[ADLPWriteResGroup5, ReadAfterVecLd], (instregex "^(V?)(ADD|SUB)SSrm$")>;
+
+def ADLPWriteResGroup6 : SchedWriteRes<[ADLPPort01_05]> {
let Latency = 3;
}
-def : InstRW<[ADLPWriteResGroup8], (instregex "^(V?)(ADD|SUB)SSrr((_Int)?)$")>;
+def : InstRW<[ADLPWriteResGroup6], (instregex "^(ADD|SUB)(P|S)Srr$",
+ "^V(ADD|SUB)SSrr$")>;
-def ADLPWriteResGroup9 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
- let Latency = 10;
+def ADLPWriteResGroup7 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
+ let Latency = 9;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup9], (instregex "^ADD_F(32|64)m$",
- "^ILD_F(16|32|64)m$",
- "^SUB(R?)_F(32|64)m$")>;
+def : InstRW<[ADLPWriteResGroup7, ReadAfterVecLd], (instregex "^(V?)(ADD|SUB)S(D|S)rm_Int$")>;
-def ADLPWriteResGroup10 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
+def ADLPWriteResGroup8 : SchedWriteRes<[ADLPPort01_05]> {
+ let Latency = 2;
+}
+def : InstRW<[ADLPWriteResGroup8], (instregex "^(V?)(ADD|SUB)S(D|S)rr_Int$")>;
+
+def ADLPWriteResGroup9 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
let ResourceCycles = [1, 2];
let Latency = 13;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup10], (instregex "^ADD_FI(16|32)m$",
- "^SUB(R?)_FI(16|32)m$")>;
+def : InstRW<[ADLPWriteResGroup9], (instregex "^ADD_FI(16|32)m$",
+ "^SUB(R?)_FI(16|32)m$")>;
-def ADLPWriteResGroup11 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
+def ADLPWriteResGroup10 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
let Latency = 2;
}
-def : InstRW<[ADLPWriteResGroup11], (instregex "^AND(8|16|32|64)r(r|i8)$",
- "^AND(8|16|32|64)rr_REV$",
- "^(AND|TEST)(32|64)i32$",
- "^(AND|TEST)(8|32)ri$",
- "^(AND|TEST)64ri32$",
- "^(AND|TEST)8i8$",
- "^(X?)OR(8|16|32|64)r(r|i8)$",
- "^(X?)OR(8|16|32|64)rr_REV$",
+def : InstRW<[ADLPWriteResGroup10], (instregex "^(AND|TEST)(32|64)i32$",
"^(X?)OR(32|64)i32$",
- "^(X?)OR(8|32)ri$",
- "^(X?)OR64ri32$",
- "^(X?)OR8i8$",
- "^TEST(8|16|32|64)rr$")>;
-def : InstRW<[ADLPWriteResGroup11], (instrs XOR8rr_NOREX)>;
+ "^(X?)OR8ri8$")>;
+def : InstRW<[ADLPWriteResGroup10], (instrs AND8ri8,
+ XOR8rr_NOREX)>;
-def ADLPWriteResGroup12 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
- let Latency = 7;
+def ADLPWriteResGroup11 : SchedWriteRes<[ADLPPort01_05_10, ADLPPort02_03_11]> {
+ let Latency = 6;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup12], (instregex "^TEST(8|16|32)mi$")>;
-def : InstRW<[ADLPWriteResGroup12], (instrs TEST64mi32)>;
-def : InstRW<[ADLPWriteResGroup12, ReadAfterLd], (instregex "^(X?)OR64rm$")>;
-def : InstRW<[ADLPWriteResGroup12, ReadAfterLd], (instrs AND64rm)>;
-def : InstRW<[ADLPWriteResGroup12, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^TEST(8|16|32|64)mr$")>;
+def : InstRW<[ADLPWriteResGroup11], (instrs MOVSX16rm8)>;
+def : InstRW<[ADLPWriteResGroup11, ReadAfterLd], (instregex "^ANDN(32|64)rm$")>;
-def ADLPWriteResGroup13 : SchedWriteRes<[ADLPPort01_05_10, ADLPPort02_03_11]> {
- let Latency = 7;
- let NumMicroOps = 2;
-}
-def : InstRW<[ADLPWriteResGroup13, ReadAfterLd], (instregex "^ANDN(32|64)rm$")>;
+def ADLPWriteResGroup12 : SchedWriteRes<[ADLPPort01_05_10]>;
+def : InstRW<[ADLPWriteResGroup12], (instregex "^ANDN(32|64)rr$",
+ "^C(DQ|WD)E$",
+ "^MOVSX(16|32|64)rr(8|32)$",
+ "^MOVSX(32|64)rr16$")>;
+def : InstRW<[ADLPWriteResGroup12], (instrs CBW,
+ MOVSX32rr8_NOREX)>;
-def ADLPWriteResGroup14 : SchedWriteRes<[ADLPPort01_05_10]> {
- let Latency = 2;
-}
-def : InstRW<[ADLPWriteResGroup14], (instregex "^ANDN(32|64)rr$")>;
+def ADLPWriteResGroup13 : SchedWriteRes<[ADLPPort01]>;
+def : InstRW<[ADLPWriteResGroup13], (instrs BSWAP32r,
+ LEA32r)>;
-def ADLPWriteResGroup15 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup14 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
let ResourceCycles = [5, 2, 1, 1];
let Latency = 10;
let NumMicroOps = 9;
}
-def : InstRW<[ADLPWriteResGroup15], (instrs BT64mr)>;
-
-def ADLPWriteResGroup16 : SchedWriteRes<[ADLPPort01]> {
- let Latency = 3;
-}
-def : InstRW<[ADLPWriteResGroup16], (instregex "^BT((C|R|S)?)64rr$",
- "^P(DEP|EXT)(32|64)rr$")>;
+def : InstRW<[ADLPWriteResGroup14], (instrs BT64mr)>;
-def ADLPWriteResGroup17 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup15 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [4, 2, 1, 1, 1, 1];
let Latency = 17;
let NumMicroOps = 10;
}
-def : InstRW<[ADLPWriteResGroup17], (instregex "^BT(C|R|S)64mr$")>;
+def : InstRW<[ADLPWriteResGroup15], (instregex "^BT(C|R|S)64mr$")>;
-def ADLPWriteResGroup18 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup16 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 7;
let NumMicroOps = 5;
}
-def : InstRW<[ADLPWriteResGroup18], (instregex "^CALL(16|32|64)m((_NT)?)$")>;
+def : InstRW<[ADLPWriteResGroup16], (instregex "^CALL(16|32)m$",
+ "^CALL(16|32|64)m_NT$")>;
-def ADLPWriteResGroup19 : SchedWriteRes<[ADLPPort00_06, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup17 : SchedWriteRes<[ADLPPort00_06, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 3;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup19], (instregex "^CALL(16|32|64)r((_NT)?)$")>;
+def : InstRW<[ADLPWriteResGroup17], (instregex "^CALL(16|32)r$",
+ "^CALL(16|32|64)r_NT$")>;
-def ADLPWriteResGroup20 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup18 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort06, ADLPPort07_08]> {
+ let Latency = 7;
+ let NumMicroOps = 5;
+}
+def : InstRW<[ADLPWriteResGroup18], (instrs CALL64m)>;
+
+def ADLPWriteResGroup19 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort06, ADLPPort07_08]> {
let Latency = 3;
- let NumMicroOps = 2;
+ let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup20], (instrs CALL64pcrel32,
- MFENCE)>;
+def : InstRW<[ADLPWriteResGroup19], (instrs CALL64pcrel32,
+ CALL64r)>;
-def ADLPWriteResGroup21 : SchedWriteRes<[ADLPPort01_05]>;
-def : InstRW<[ADLPWriteResGroup21], (instregex "^C(DQ|WD)E$",
- "^(V?)MOVS(H|L)DUPrr$",
- "^(V?)SHUFP(D|S)rri$",
- "^VMOVS(H|L)DUPYrr$",
- "^VSHUFP(D|S)Yrri$")>;
-def : InstRW<[ADLPWriteResGroup21], (instrs CBW,
- VPBLENDWYrri)>;
+def ADLPWriteResGroup20 : SchedWriteRes<[ADLPPort00_06]>;
+def : InstRW<[ADLPWriteResGroup20], (instregex "^C(DQ|QO)$",
+ "^(CL|ST)AC$",
+ "^ROL(8|16|32|64)ri$",
+ "^ROR(16|32|64)ri$")>;
-def ADLPWriteResGroup22 : SchedWriteRes<[ADLPPort00_06]>;
-def : InstRW<[ADLPWriteResGroup22], (instregex "^C(DQ|QO)$",
- "^(CL|ST)AC$")>;
+def ADLPWriteResGroup21 : SchedWriteRes<[]> {
+ let NumMicroOps = 0;
+}
+def : InstRW<[ADLPWriteResGroup21], (instrs CLC,
+ JMP_2)>;
-def ADLPWriteResGroup23 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+def ADLPWriteResGroup22 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
let Latency = 3;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup23], (instrs CLD)>;
+def : InstRW<[ADLPWriteResGroup22], (instrs CLD)>;
-def ADLPWriteResGroup24 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup23 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 3;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup24], (instrs CLDEMOTE)>;
+def : InstRW<[ADLPWriteResGroup23], (instrs CLDEMOTE)>;
-def ADLPWriteResGroup25 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup24 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 2;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup25], (instrs CLFLUSH)>;
+def : InstRW<[ADLPWriteResGroup24], (instrs CLFLUSH)>;
-def ADLPWriteResGroup26 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup25 : SchedWriteRes<[ADLPPort00_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 2;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup26], (instrs CLFLUSHOPT)>;
+def : InstRW<[ADLPWriteResGroup25], (instrs CLFLUSHOPT)>;
-def ADLPWriteResGroup27 : SchedWriteRes<[ADLPPort00_06, ADLPPort01]> {
- let ResourceCycles = [2, 1];
+def ADLPWriteResGroup26 : SchedWriteRes<[ADLPPort01, ADLPPort06]> {
+ let ResourceCycles = [1, 2];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup27], (instrs CLI)>;
+def : InstRW<[ADLPWriteResGroup26], (instrs CLI)>;
-def ADLPWriteResGroup28 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort05]> {
+def ADLPWriteResGroup27 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort05]> {
let ResourceCycles = [6, 1, 3];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 10;
}
-def : InstRW<[ADLPWriteResGroup28], (instrs CLTS)>;
+def : InstRW<[ADLPWriteResGroup27], (instrs CLTS)>;
-def ADLPWriteResGroup29 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup28 : SchedWriteRes<[ADLPPort00_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 5;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup29], (instregex "^MOV16o(16|32|64)a$")>;
-def : InstRW<[ADLPWriteResGroup29], (instrs CLWB)>;
+def : InstRW<[ADLPWriteResGroup28], (instrs CLWB)>;
-def ADLPWriteResGroup30 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup29 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
let ResourceCycles = [5, 2];
let Latency = 6;
let NumMicroOps = 7;
}
-def : InstRW<[ADLPWriteResGroup30], (instregex "^CMPS(B|L|Q|W)$")>;
+def : InstRW<[ADLPWriteResGroup29], (instregex "^CMPS(B|L|Q|W)$")>;
+
+def ADLPWriteResGroup30 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11]> {
+ let Latency = 10;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup30, ReadAfterVecLd], (instregex "^(V?)CMPS(D|S)rm_Int$",
+ "^(V?)CVTS(I|S)2SDrm_Int$",
+ "^(V?)CVTSI2SSrm_Int$",
+ "^(V?)CVTSI642SDrm_Int$",
+ "^(V?)M(AX|IN|UL)S(D|S)rm_Int$")>;
+def : InstRW<[ADLPWriteResGroup30, ReadAfterVecLd, ReadAfterVecLd], (instregex "^VF(N?)M(ADD|SUB)(132|213|231)S(D|S)m_Int$")>;
def ADLPWriteResGroup31 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [2, 7, 6, 2, 1, 1, 2, 1];
@@ -769,1708 +767,1870 @@ def ADLPWriteResGroup33 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06,
}
def : InstRW<[ADLPWriteResGroup33], (instrs CMPXCHG8rm)>;
-def ADLPWriteResGroup34 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup34 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
+ let Latency = 8;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup34, ReadAfterVecLd], (instregex "^((U|V|VU)?)COMIS(D|S)rm_Int$")>;
+
+def ADLPWriteResGroup35 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [2, 1, 10, 6, 1, 5, 1];
let Latency = 18;
let NumMicroOps = 26;
}
-def : InstRW<[ADLPWriteResGroup34], (instrs CPUID)>;
+def : InstRW<[ADLPWriteResGroup35], (instrs CPUID)>;
+
+def ADLPWriteResGroup36 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11]> {
+ let Latency = 11;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup36], (instregex "^VPDP(BU|WS)SD(S?)rm$")>;
+def : InstRW<[ADLPWriteResGroup36], (instrs CVTDQ2PDrm)>;
+def : InstRW<[ADLPWriteResGroup36, ReadAfterVecXLd], (instregex "^(V?)M(AX|IN)CP(D|S)rm$")>;
+def : InstRW<[ADLPWriteResGroup36, ReadAfterVecXLd], (instrs VGF2P8MULBrm)>;
+def : InstRW<[ADLPWriteResGroup36, ReadAfterVecYLd], (instregex "^VGF2P8AFFINE((INV)?)QBYrmi$")>;
+def : InstRW<[ADLPWriteResGroup36, ReadAfterVecYLd], (instrs VGF2P8MULBYrm)>;
-def ADLPWriteResGroup35 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup37 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11, ADLPPort05]> {
+ let Latency = 12;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup37], (instregex "^CVT(T?)PD2DQrm$")>;
+def : InstRW<[ADLPWriteResGroup37], (instrs CVTSI642SSrm)>;
+def : InstRW<[ADLPWriteResGroup37, ReadAfterVecLd], (instrs VCVTSI642SSrm)>;
+
+def ADLPWriteResGroup38 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort02_03_11]> {
let Latency = 26;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup35], (instregex "^(V?)CVT(T?)SD2SIrm((_Int)?)$")>;
+def : InstRW<[ADLPWriteResGroup38], (instregex "^(V?)CVT(T?)SD2SIrm$")>;
-def ADLPWriteResGroup36 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11, ADLPPort05]> {
- let Latency = 12;
+def ADLPWriteResGroup39 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11, ADLPPort05]> {
+ let Latency = 11;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup36], (instrs CVTSI642SSrm)>;
-def : InstRW<[ADLPWriteResGroup36, ReadAfterVecLd], (instregex "^(V?)CVTSI642SSrm_Int$")>;
-def : InstRW<[ADLPWriteResGroup36, ReadAfterVecLd], (instrs VCVTSI642SSrm)>;
+def : InstRW<[ADLPWriteResGroup39], (instrs VCVTPD2PSrm)>;
+def : InstRW<[ADLPWriteResGroup39, ReadAfterVecLd], (instregex "^(V?)CVTS(D|I64)2SSrm_Int$")>;
-def ADLPWriteResGroup37 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
+def ADLPWriteResGroup40 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
+ let Latency = 5;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup40, ReadDefault, ReadInt2Fpu], (instregex "^CVTSI((64)?)2SDrr_Int$")>;
+def : InstRW<[ADLPWriteResGroup40, ReadDefault, ReadInt2Fpu], (instrs CVTSI2SSrr_Int)>;
+
+def ADLPWriteResGroup41 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
let ResourceCycles = [1, 2];
let Latency = 8;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup37, ReadInt2Fpu], (instrs CVTSI642SSrr)>;
-def : InstRW<[ADLPWriteResGroup37, ReadDefault, ReadInt2Fpu], (instregex "^(V?)CVTSI642SSrr_Int$")>;
-def : InstRW<[ADLPWriteResGroup37, ReadDefault, ReadInt2Fpu], (instrs VCVTSI642SSrr)>;
+def : InstRW<[ADLPWriteResGroup41, ReadInt2Fpu], (instrs CVTSI642SSrr)>;
+def : InstRW<[ADLPWriteResGroup41, ReadDefault, ReadInt2Fpu], (instregex "^VCVTSI642SSrr((_Int)?)$")>;
+
+def ADLPWriteResGroup42 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
+ let ResourceCycles = [1, 2];
+ let Latency = 6;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup42, ReadDefault, ReadInt2Fpu], (instrs CVTSI642SSrr_Int)>;
-def ADLPWriteResGroup38 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort05]> {
+def ADLPWriteResGroup43 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort05]> {
let Latency = 8;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup38], (instregex "^(V?)CVT(T?)SS2SI64rr_Int$")>;
-def : InstRW<[ADLPWriteResGroup38, ReadDefault], (instregex "^(V?)CVT(T?)SS2SI64rr$")>;
+def : InstRW<[ADLPWriteResGroup43], (instregex "^(V?)CVT(T?)SS2SI64rr_Int$")>;
+def : InstRW<[ADLPWriteResGroup43, ReadDefault], (instregex "^(V?)CVT(T?)SS2SI64rr$")>;
-def ADLPWriteResGroup39 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+def ADLPWriteResGroup44 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
let Latency = 2;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup39], (instregex "^J(E|R)CXZ$")>;
-def : InstRW<[ADLPWriteResGroup39], (instrs CWD)>;
+def : InstRW<[ADLPWriteResGroup44], (instregex "^J(E|R)CXZ$")>;
+def : InstRW<[ADLPWriteResGroup44], (instrs CWD)>;
-def ADLPWriteResGroup40 : SchedWriteRes<[ADLPPort00_01_05_06]>;
-def : InstRW<[ADLPWriteResGroup40], (instregex "^(LD|ST)_Frr$",
+def ADLPWriteResGroup45 : SchedWriteRes<[ADLPPort00_01_05_06]>;
+def : InstRW<[ADLPWriteResGroup45], (instregex "^(LD|ST)_Frr$",
"^MOV16s(m|r)$",
"^MOV(32|64)sr$")>;
-def : InstRW<[ADLPWriteResGroup40], (instrs DEC16r_alt,
+def : InstRW<[ADLPWriteResGroup45], (instrs DEC16r_alt,
SALC,
ST_FPrr,
SYSCALL)>;
-def ADLPWriteResGroup41 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup46 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 7;
}
-def : InstRW<[ADLPWriteResGroup41], (instrs DEC32r_alt)>;
-
-def ADLPWriteResGroup42 : SchedWriteRes<[ADLPPort00, ADLPPort02_03]> {
- let Latency = 27;
- let NumMicroOps = 2;
-}
-def : InstRW<[ADLPWriteResGroup42], (instregex "^DIVR_F(32|64)m$")>;
+def : InstRW<[ADLPWriteResGroup46], (instrs DEC32r_alt)>;
-def ADLPWriteResGroup43 : SchedWriteRes<[ADLPPort00, ADLPPort02_03, ADLPPort05]> {
+def ADLPWriteResGroup47 : SchedWriteRes<[ADLPPort00, ADLPPort02_03, ADLPPort05]> {
let Latency = 30;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup43], (instregex "^DIVR_FI(16|32)m$")>;
+def : InstRW<[ADLPWriteResGroup47], (instregex "^DIVR_FI(16|32)m$")>;
-def ADLPWriteResGroup44 : SchedWriteRes<[ADLPPort00]> {
+def ADLPWriteResGroup48 : SchedWriteRes<[ADLPPort00]> {
let Latency = 15;
}
-def : InstRW<[ADLPWriteResGroup44], (instregex "^DIVR_F(P?)rST0$")>;
-def : InstRW<[ADLPWriteResGroup44], (instrs DIVR_FST0r)>;
+def : InstRW<[ADLPWriteResGroup48], (instregex "^DIVR_F(P?)rST0$")>;
+def : InstRW<[ADLPWriteResGroup48], (instrs DIVR_FST0r)>;
-def ADLPWriteResGroup45 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
+def ADLPWriteResGroup49 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
let Latency = 20;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup45, ReadAfterVecLd], (instregex "^(V?)DIVSDrm_Int$")>;
+def : InstRW<[ADLPWriteResGroup49, ReadAfterVecLd], (instregex "^(V?)DIVSDrm_Int$")>;
-def ADLPWriteResGroup46 : SchedWriteRes<[ADLPPort00, ADLPPort02_03]> {
+def ADLPWriteResGroup50 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
+ let Latency = 18;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup50, ReadAfterVecLd], (instregex "^(V?)DIVSSrm$",
+ "^(V?)SQRTSSm_Int$")>;
+
+def ADLPWriteResGroup51 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
+ let Latency = 17;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup51, ReadAfterVecLd], (instregex "^(V?)DIVSSrm_Int$")>;
+
+def ADLPWriteResGroup52 : SchedWriteRes<[ADLPPort00, ADLPPort02_03]> {
let Latency = 22;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup46], (instregex "^DIV_F(32|64)m$")>;
+def : InstRW<[ADLPWriteResGroup52], (instregex "^DIV_F(32|64)m$")>;
-def ADLPWriteResGroup47 : SchedWriteRes<[ADLPPort00, ADLPPort02_03, ADLPPort05]> {
+def ADLPWriteResGroup53 : SchedWriteRes<[ADLPPort00, ADLPPort02_03, ADLPPort05]> {
let Latency = 25;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup47], (instregex "^DIV_FI(16|32)m$")>;
+def : InstRW<[ADLPWriteResGroup53], (instregex "^DIV_FI(16|32)m$")>;
-def ADLPWriteResGroup48 : SchedWriteRes<[ADLPPort00]> {
+def ADLPWriteResGroup54 : SchedWriteRes<[ADLPPort00]> {
let Latency = 20;
}
-def : InstRW<[ADLPWriteResGroup48], (instregex "^DIV_F(P?)rST0$")>;
-def : InstRW<[ADLPWriteResGroup48], (instrs DIV_FST0r)>;
+def : InstRW<[ADLPWriteResGroup54], (instregex "^DIV_F(P?)rST0$")>;
+def : InstRW<[ADLPWriteResGroup54], (instrs DIV_FST0r)>;
-def ADLPWriteResGroup49 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup55 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [2, 21, 2, 14, 4, 9, 5];
let Latency = 126;
let NumMicroOps = 57;
}
-def : InstRW<[ADLPWriteResGroup49], (instrs ENTER)>;
+def : InstRW<[ADLPWriteResGroup55], (instrs ENTER)>;
-def ADLPWriteResGroup50 : SchedWriteRes<[ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
- let Latency = 12;
+def ADLPWriteResGroup56 : SchedWriteRes<[ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let Latency = 2;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup50], (instregex "^(V?)EXTRACTPSmr$")>;
-def : InstRW<[ADLPWriteResGroup50], (instrs SMSW16m)>;
+def : InstRW<[ADLPWriteResGroup56], (instregex "^(V?)EXTRACTPSmr$")>;
-def ADLPWriteResGroup51 : SchedWriteRes<[ADLPPort00, ADLPPort05]> {
+def ADLPWriteResGroup57 : SchedWriteRes<[ADLPPort00, ADLPPort05]> {
let Latency = 4;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup51], (instregex "^(V?)EXTRACTPSrr$")>;
-def : InstRW<[ADLPWriteResGroup51], (instrs MMX_PEXTRWrr)>;
+def : InstRW<[ADLPWriteResGroup57], (instregex "^(V?)EXTRACTPSrr$")>;
+def : InstRW<[ADLPWriteResGroup57], (instrs MMX_PEXTRWrr)>;
-def ADLPWriteResGroup52 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort02_03, ADLPPort02_03_07, ADLPPort04, ADLPPort06]> {
+def ADLPWriteResGroup58 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort02_03, ADLPPort02_03_07, ADLPPort04, ADLPPort06]> {
let Latency = 7;
let NumMicroOps = 5;
}
-def : InstRW<[ADLPWriteResGroup52], (instrs FARCALL64m)>;
+def : InstRW<[ADLPWriteResGroup58], (instrs FARCALL64m)>;
-def ADLPWriteResGroup53 : SchedWriteRes<[ADLPPort02_03, ADLPPort06]> {
+def ADLPWriteResGroup59 : SchedWriteRes<[ADLPPort02_03, ADLPPort06]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup53], (instrs FARJMP64m,
+def : InstRW<[ADLPWriteResGroup59], (instrs FARJMP64m,
JMP64m_REX)>;
-def ADLPWriteResGroup54 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04]> {
+def ADLPWriteResGroup60 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04]> {
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup54], (instregex "^(V?)MASKMOVDQU((64)?)$",
+def : InstRW<[ADLPWriteResGroup60], (instregex "^(V?)MASKMOVDQU((64)?)$",
"^ST_FP(32|64|80)m$")>;
-def : InstRW<[ADLPWriteResGroup54], (instrs FBSTPm,
+def : InstRW<[ADLPWriteResGroup60], (instrs FBSTPm,
VMPTRSTm)>;
-def ADLPWriteResGroup55 : SchedWriteRes<[ADLPPort00_05]> {
+def ADLPWriteResGroup61 : SchedWriteRes<[ADLPPort00_05]> {
let ResourceCycles = [2];
let Latency = 2;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup55], (instrs FDECSTP)>;
+def : InstRW<[ADLPWriteResGroup61], (instrs FDECSTP)>;
-def ADLPWriteResGroup56 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
+def ADLPWriteResGroup62 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
let ResourceCycles = [1, 2];
let Latency = 11;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup56], (instregex "^FICOM(P?)(16|32)m$")>;
+def : InstRW<[ADLPWriteResGroup62], (instregex "^FICOM(P?)(16|32)m$")>;
-def ADLPWriteResGroup57 : SchedWriteRes<[ADLPPort00_05]>;
-def : InstRW<[ADLPWriteResGroup57], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rr$")>;
-def : InstRW<[ADLPWriteResGroup57], (instrs FINCSTP,
+def ADLPWriteResGroup63 : SchedWriteRes<[ADLPPort00_05]>;
+def : InstRW<[ADLPWriteResGroup63], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rr$")>;
+def : InstRW<[ADLPWriteResGroup63], (instrs FINCSTP,
FNOP)>;
-def ADLPWriteResGroup58 : SchedWriteRes<[ADLPPort00, ADLPPort00_05, ADLPPort02_03]> {
+def ADLPWriteResGroup64 : SchedWriteRes<[ADLPPort00, ADLPPort00_05, ADLPPort02_03]> {
let Latency = 7;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup58], (instrs FLDCW16m)>;
+def : InstRW<[ADLPWriteResGroup64], (instrs FLDCW16m)>;
-def ADLPWriteResGroup59 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort02_03]> {
+def ADLPWriteResGroup65 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort02_03]> {
let ResourceCycles = [2, 39, 5, 10, 8];
let Latency = 62;
let NumMicroOps = 64;
}
-def : InstRW<[ADLPWriteResGroup59], (instrs FLDENVm)>;
+def : InstRW<[ADLPWriteResGroup65], (instrs FLDENVm)>;
-def ADLPWriteResGroup60 : SchedWriteRes<[ADLPPort00_01_05_06]> {
+def ADLPWriteResGroup66 : SchedWriteRes<[ADLPPort00_01_05_06]> {
let ResourceCycles = [4];
let Latency = 4;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup60], (instrs FNCLEX)>;
+def : InstRW<[ADLPWriteResGroup66], (instrs FNCLEX)>;
-def ADLPWriteResGroup61 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort05]> {
+def ADLPWriteResGroup67 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort05]> {
let ResourceCycles = [6, 3, 6];
let Latency = 75;
let NumMicroOps = 15;
}
-def : InstRW<[ADLPWriteResGroup61], (instrs FNINIT)>;
+def : InstRW<[ADLPWriteResGroup67], (instrs FNINIT)>;
-def ADLPWriteResGroup62 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04, ADLPPort06]> {
+def ADLPWriteResGroup68 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04, ADLPPort06]> {
let Latency = 2;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup62], (instrs FNSTCW16m)>;
+def : InstRW<[ADLPWriteResGroup68], (instrs FNSTCW16m)>;
-def ADLPWriteResGroup63 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06]> {
+def ADLPWriteResGroup69 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06]> {
let Latency = 3;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup63], (instrs FNSTSW16r)>;
+def : InstRW<[ADLPWriteResGroup69], (instrs FNSTSW16r)>;
-def ADLPWriteResGroup64 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_07, ADLPPort04]> {
+def ADLPWriteResGroup70 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_07, ADLPPort04]> {
let Latency = 3;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup64], (instrs FNSTSWm)>;
+def : InstRW<[ADLPWriteResGroup70], (instrs FNSTSWm)>;
-def ADLPWriteResGroup65 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_07, ADLPPort04, ADLPPort05, ADLPPort06]> {
+def ADLPWriteResGroup71 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_07, ADLPPort04, ADLPPort05, ADLPPort06]> {
let ResourceCycles = [9, 30, 21, 1, 11, 11, 16, 1];
let Latency = 106;
let NumMicroOps = 100;
}
-def : InstRW<[ADLPWriteResGroup65], (instrs FSTENVm)>;
+def : InstRW<[ADLPWriteResGroup71], (instrs FSTENVm)>;
-def ADLPWriteResGroup66 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03, ADLPPort06]> {
+def ADLPWriteResGroup72 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03, ADLPPort06]> {
let ResourceCycles = [4, 47, 1, 2, 1, 33, 2];
let Latency = 63;
let NumMicroOps = 90;
}
-def : InstRW<[ADLPWriteResGroup66], (instrs FXRSTOR)>;
+def : InstRW<[ADLPWriteResGroup72], (instrs FXRSTOR)>;
-def ADLPWriteResGroup67 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03, ADLPPort06]> {
+def ADLPWriteResGroup73 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03, ADLPPort06]> {
let ResourceCycles = [4, 45, 1, 2, 1, 31, 4];
let Latency = 63;
let NumMicroOps = 88;
}
-def : InstRW<[ADLPWriteResGroup67], (instrs FXRSTOR64)>;
+def : InstRW<[ADLPWriteResGroup73], (instrs FXRSTOR64)>;
-def ADLPWriteResGroup68 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup74 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [2, 5, 10, 10, 2, 38, 5, 38];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 110;
}
-def : InstRW<[ADLPWriteResGroup68], (instregex "^FXSAVE((64)?)$")>;
+def : InstRW<[ADLPWriteResGroup74], (instregex "^FXSAVE((64)?)$")>;
-def ADLPWriteResGroup69 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup75 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11]> {
let Latency = 12;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup69, ReadAfterVecXLd], (instregex "^(V?)GF2P8AFFINE((INV)?)QBrmi$",
- "^(V?)GF2P8MULBrm$")>;
-def : InstRW<[ADLPWriteResGroup69, ReadAfterVecYLd], (instregex "^VGF2P8AFFINE((INV)?)QBYrmi$")>;
-def : InstRW<[ADLPWriteResGroup69, ReadAfterVecYLd], (instrs VGF2P8MULBYrm)>;
+def : InstRW<[ADLPWriteResGroup75], (instregex "^VPDP(BU|WS)SD(S?)Yrm$")>;
+def : InstRW<[ADLPWriteResGroup75, ReadAfterVecXLd], (instregex "^GF2P8AFFINE((INV)?)QBrmi$")>;
+def : InstRW<[ADLPWriteResGroup75, ReadAfterVecXLd], (instrs GF2P8MULBrm)>;
+def : InstRW<[ADLPWriteResGroup75, ReadAfterVecYLd], (instregex "^VM(AX|IN)CP(D|S)Yrm$")>;
-def ADLPWriteResGroup70 : SchedWriteRes<[ADLPPort00_01]> {
+def ADLPWriteResGroup76 : SchedWriteRes<[ADLPPort00_01]> {
let Latency = 5;
}
-def : InstRW<[ADLPWriteResGroup70], (instregex "^(V?)GF2P8MULBrr$")>;
-def : InstRW<[ADLPWriteResGroup70], (instrs VGF2P8MULBYrr)>;
+def : InstRW<[ADLPWriteResGroup76], (instrs GF2P8MULBrr)>;
+
+def ADLPWriteResGroup77 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [1, 1, 2];
+ let Latency = 12;
+ let NumMicroOps = 4;
+}
+def : InstRW<[ADLPWriteResGroup77, ReadAfterVecXLd], (instregex "^(V?)H(ADD|SUB)PSrm$")>;
-def ADLPWriteResGroup71 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup78 : SchedWriteRes<[ADLPPort01_05, ADLPPort05]> {
+ let ResourceCycles = [1, 2];
+ let Latency = 6;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup78], (instregex "^H(ADD|SUB)PSrr$")>;
+
+def ADLPWriteResGroup79 : SchedWriteRes<[ADLPPort02_03, ADLPPort05]> {
+ let Latency = 10;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup79], (instregex "^ILD_F(16|32|64)m$")>;
+
+def ADLPWriteResGroup80 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [7, 5, 26, 19, 2, 7, 21];
let Latency = 35;
let NumMicroOps = 87;
}
-def : InstRW<[ADLPWriteResGroup71], (instrs IN16ri)>;
+def : InstRW<[ADLPWriteResGroup80], (instrs IN16ri)>;
-def ADLPWriteResGroup72 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup81 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [7, 1, 4, 26, 19, 3, 7, 20];
let Latency = 35;
let NumMicroOps = 87;
}
-def : InstRW<[ADLPWriteResGroup72], (instrs IN16rr)>;
+def : InstRW<[ADLPWriteResGroup81], (instrs IN16rr)>;
-def ADLPWriteResGroup73 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup82 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [7, 6, 28, 21, 2, 10, 20];
let Latency = 35;
let NumMicroOps = 94;
}
-def : InstRW<[ADLPWriteResGroup73], (instrs IN32ri)>;
+def : InstRW<[ADLPWriteResGroup82], (instrs IN32ri)>;
-def ADLPWriteResGroup74 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
- let ResourceCycles = [7, 9, 28, 21, 2, 11, 21];
- let NumMicroOps = 99;
+def ADLPWriteResGroup83 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
+ let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup74], (instrs IN32rr)>;
+def : InstRW<[ADLPWriteResGroup83], (instrs IN32rr)>;
-def ADLPWriteResGroup75 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup84 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [7, 6, 25, 19, 2, 8, 20];
let Latency = 35;
let NumMicroOps = 87;
}
-def : InstRW<[ADLPWriteResGroup75], (instrs IN8ri)>;
+def : InstRW<[ADLPWriteResGroup84], (instrs IN8ri)>;
-def ADLPWriteResGroup76 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup85 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [7, 6, 25, 19, 2, 7, 20];
let Latency = 35;
let NumMicroOps = 86;
}
-def : InstRW<[ADLPWriteResGroup76], (instrs IN8rr)>;
+def : InstRW<[ADLPWriteResGroup85], (instrs IN8rr)>;
-def ADLPWriteResGroup77 : SchedWriteRes<[ADLPPort00_06]> {
+def ADLPWriteResGroup86 : SchedWriteRes<[ADLPPort00_06]> {
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup77], (instrs INC16r_alt)>;
+def : InstRW<[ADLPWriteResGroup86], (instrs INC16r_alt)>;
-def ADLPWriteResGroup78 : SchedWriteRes<[ADLPPort02_03_11]> {
+def ADLPWriteResGroup87 : SchedWriteRes<[ADLPPort02_03_11]> {
let Latency = 7;
}
-def : InstRW<[ADLPWriteResGroup78], (instregex "^(V?)MOV(D|SH|SL)DUPrm$",
- "^VPBROADCAST(D|Q)rm$")>;
-def : InstRW<[ADLPWriteResGroup78], (instrs INC32r_alt,
- VBROADCASTSSrm)>;
+def : InstRW<[ADLPWriteResGroup87], (instregex "^(V?)MOV(D|SH|SL)DUPrm$",
+ "^(V?)MOVS(D|S)rm_alt$",
+ "^VBROADCAST(F|I)128$",
+ "^VBROADCASTS(D|S)Yrm$",
+ "^VMOV(D|SH|SL)DUPYrm$",
+ "^VPBROADCAST(D|Q)Yrm$")>;
+def : InstRW<[ADLPWriteResGroup87], (instrs INC32r_alt)>;
-def ADLPWriteResGroup79 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup88 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [7, 6, 24, 17, 8, 1, 19, 1];
let Latency = 20;
let NumMicroOps = 83;
}
-def : InstRW<[ADLPWriteResGroup79], (instrs INSB)>;
+def : InstRW<[ADLPWriteResGroup88], (instrs INSB)>;
-def ADLPWriteResGroup80 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup89 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+ let Latency = 8;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup89], (instregex "^VPBROADCAST(B|W)Yrm$")>;
+def : InstRW<[ADLPWriteResGroup89, ReadAfterVecXLd], (instrs INSERTPSrm)>;
+def : InstRW<[ADLPWriteResGroup89, ReadAfterVecYLd], (instrs VPALIGNRYrmi)>;
+
+def ADLPWriteResGroup90 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [7, 1, 5, 1, 27, 17, 11, 1, 21, 1];
let Latency = 20;
let NumMicroOps = 92;
}
-def : InstRW<[ADLPWriteResGroup80], (instrs INSL)>;
+def : InstRW<[ADLPWriteResGroup90], (instrs INSL)>;
-def ADLPWriteResGroup81 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup91 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [7, 1, 4, 1, 25, 17, 1, 9, 1, 19, 1];
let Latency = 20;
let NumMicroOps = 86;
}
-def : InstRW<[ADLPWriteResGroup81], (instrs INSW)>;
+def : InstRW<[ADLPWriteResGroup91], (instrs INSW)>;
-def ADLPWriteResGroup82 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup92 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [5, 4, 8, 6, 2, 5, 7, 5];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 42;
}
-def : InstRW<[ADLPWriteResGroup82], (instrs INVLPG)>;
+def : InstRW<[ADLPWriteResGroup92], (instrs INVLPG)>;
-def ADLPWriteResGroup83 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04, ADLPPort05]> {
- let Latency = 4;
- let NumMicroOps = 3;
+def ADLPWriteResGroup93 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort00_06]> {
+ let Latency = 2;
+ let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup83], (instregex "^IST(T?)_FP(16|32|64)m$",
- "^IST_F(16|32)m$")>;
+def : InstRW<[ADLPWriteResGroup93], (instrs JCXZ)>;
-def ADLPWriteResGroup84 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort00_06]> {
- let Latency = 2;
+def ADLPWriteResGroup94 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort06]> {
+ let Latency = 6;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup84], (instrs JCXZ)>;
+def : InstRW<[ADLPWriteResGroup94], (instrs JMP64m)>;
-def ADLPWriteResGroup85 : SchedWriteRes<[ADLPPort06]>;
-def : InstRW<[ADLPWriteResGroup85], (instrs JMP64r_REX)>;
+def ADLPWriteResGroup95 : SchedWriteRes<[ADLPPort06]>;
+def : InstRW<[ADLPWriteResGroup95], (instregex "^JMP64r((_REX)?)$")>;
-def ADLPWriteResGroup86 : SchedWriteRes<[]> {
+def ADLPWriteResGroup96 : SchedWriteRes<[ADLPPort06]> {
let Latency = 0;
- let NumMicroOps = 0;
}
-def : InstRW<[ADLPWriteResGroup86], (instregex "^JMP_(1|4)$")>;
-def : InstRW<[ADLPWriteResGroup86], (instrs VZEROUPPER)>;
+def : InstRW<[ADLPWriteResGroup96], (instregex "^JMP_(1|4)$")>;
-def ADLPWriteResGroup87 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup97 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [8, 2, 14, 3, 1];
let Latency = 198;
let NumMicroOps = 81;
}
-def : InstRW<[ADLPWriteResGroup87], (instrs LAR16rm)>;
+def : InstRW<[ADLPWriteResGroup97], (instrs LAR16rm)>;
-def ADLPWriteResGroup88 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup98 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [1, 3, 1, 8, 5, 1, 2, 1];
let Latency = 66;
let NumMicroOps = 22;
}
-def : InstRW<[ADLPWriteResGroup88], (instrs LAR16rr)>;
+def : InstRW<[ADLPWriteResGroup98], (instrs LAR16rr)>;
-def ADLPWriteResGroup89 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup99 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [1, 2, 2, 9, 5, 3, 1];
let Latency = 71;
let NumMicroOps = 85;
}
-def : InstRW<[ADLPWriteResGroup89], (instrs LAR32rm)>;
+def : InstRW<[ADLPWriteResGroup99], (instrs LAR32rm)>;
-def ADLPWriteResGroup90 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup100 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [1, 3, 1, 8, 5, 1, 2, 1];
let Latency = 65;
let NumMicroOps = 22;
}
-def : InstRW<[ADLPWriteResGroup90], (instregex "^LAR(32|64)rr$")>;
+def : InstRW<[ADLPWriteResGroup100], (instregex "^LAR(32|64)rr$")>;
-def ADLPWriteResGroup91 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup101 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [1, 2, 2, 9, 5, 3, 1];
let Latency = 71;
let NumMicroOps = 87;
}
-def : InstRW<[ADLPWriteResGroup91], (instrs LAR64rm)>;
+def : InstRW<[ADLPWriteResGroup101], (instrs LAR64rm)>;
-def ADLPWriteResGroup92 : SchedWriteRes<[ADLPPort02_03]> {
+def ADLPWriteResGroup102 : SchedWriteRes<[ADLPPort02_03]> {
let Latency = 7;
}
-def : InstRW<[ADLPWriteResGroup92], (instregex "^LD_F(32|64|80)m$")>;
+def : InstRW<[ADLPWriteResGroup102], (instregex "^LD_F(32|64|80)m$")>;
-def ADLPWriteResGroup93 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
+def ADLPWriteResGroup103 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
+ let ResourceCycles = [2];
let Latency = 2;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup93], (instrs LEA16r)>;
+def : InstRW<[ADLPWriteResGroup103], (instrs LEA16r)>;
-def ADLPWriteResGroup94 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup104 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
let ResourceCycles = [3, 1];
let Latency = 6;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup94], (instregex "^LODS(B|W)$",
- "^SCAS(B|L|Q|W)$")>;
-def : InstRW<[ADLPWriteResGroup94], (instrs LEAVE)>;
+def : InstRW<[ADLPWriteResGroup104], (instregex "^LODS(B|W)$",
+ "^SCAS(B|L|Q|W)$")>;
+def : InstRW<[ADLPWriteResGroup104], (instrs LEAVE)>;
-def ADLPWriteResGroup95 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup105 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
let ResourceCycles = [2, 1];
let Latency = 6;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup95], (instrs LEAVE64)>;
+def : InstRW<[ADLPWriteResGroup105], (instregex "^POP16r((mr)?)$")>;
+def : InstRW<[ADLPWriteResGroup105], (instrs LEAVE64)>;
-def ADLPWriteResGroup96 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup106 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [1, 2, 4, 3, 2, 1, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 14;
}
-def : InstRW<[ADLPWriteResGroup96], (instrs LGDT64m)>;
+def : InstRW<[ADLPWriteResGroup106], (instrs LGDT64m)>;
-def ADLPWriteResGroup97 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup107 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [1, 1, 5, 3, 2, 1, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 14;
}
-def : InstRW<[ADLPWriteResGroup97], (instrs LIDT64m)>;
+def : InstRW<[ADLPWriteResGroup107], (instrs LIDT64m)>;
-def ADLPWriteResGroup98 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup108 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [5, 3, 2, 1, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 12;
}
-def : InstRW<[ADLPWriteResGroup98], (instrs LLDT16m)>;
+def : InstRW<[ADLPWriteResGroup108], (instrs LLDT16m)>;
-def ADLPWriteResGroup99 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup109 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [1, 4, 3, 1, 1, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 11;
}
-def : InstRW<[ADLPWriteResGroup99], (instrs LLDT16r)>;
+def : InstRW<[ADLPWriteResGroup109], (instrs LLDT16r)>;
-def ADLPWriteResGroup100 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup110 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [1, 1, 2, 8, 3, 1, 2, 7, 2];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 27;
}
-def : InstRW<[ADLPWriteResGroup100], (instrs LMSW16m)>;
+def : InstRW<[ADLPWriteResGroup110], (instrs LMSW16m)>;
-def ADLPWriteResGroup101 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup111 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [5, 7, 1, 2, 5, 2];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 22;
}
-def : InstRW<[ADLPWriteResGroup101], (instrs LMSW16r)>;
+def : InstRW<[ADLPWriteResGroup111], (instrs LMSW16r)>;
-def ADLPWriteResGroup102 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup112 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
let ResourceCycles = [2, 1];
let Latency = 5;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup102], (instregex "^LODS(L|Q)$")>;
+def : InstRW<[ADLPWriteResGroup112], (instregex "^LODS(L|Q)$")>;
-def ADLPWriteResGroup103 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup113 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
let ResourceCycles = [2, 4, 1];
let Latency = 3;
let NumMicroOps = 7;
}
-def : InstRW<[ADLPWriteResGroup103], (instrs LOOP)>;
+def : InstRW<[ADLPWriteResGroup113], (instrs LOOP)>;
-def ADLPWriteResGroup104 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup114 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
let ResourceCycles = [4, 6, 1];
let Latency = 3;
let NumMicroOps = 11;
}
-def : InstRW<[ADLPWriteResGroup104], (instrs LOOPE)>;
+def : InstRW<[ADLPWriteResGroup114], (instrs LOOPE)>;
-def ADLPWriteResGroup105 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup115 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
let ResourceCycles = [4, 6, 1];
let Latency = 2;
let NumMicroOps = 11;
}
-def : InstRW<[ADLPWriteResGroup105], (instrs LOOPNE)>;
+def : InstRW<[ADLPWriteResGroup115], (instrs LOOPNE)>;
-def ADLPWriteResGroup106 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort02_03, ADLPPort06]> {
+def ADLPWriteResGroup116 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort02_03, ADLPPort06]> {
let Latency = 7;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup106], (instrs LRET64)>;
+def : InstRW<[ADLPWriteResGroup116], (instrs LRET64)>;
-def ADLPWriteResGroup107 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup117 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [1, 5, 3, 3, 1];
let Latency = 70;
let NumMicroOps = 13;
}
-def : InstRW<[ADLPWriteResGroup107], (instregex "^LSL(16|32|64)rm$")>;
+def : InstRW<[ADLPWriteResGroup117], (instregex "^LSL(16|32|64)rm$")>;
-def ADLPWriteResGroup108 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup118 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [1, 4, 4, 3, 2, 1];
let Latency = 63;
let NumMicroOps = 15;
}
-def : InstRW<[ADLPWriteResGroup108], (instregex "^LSL(16|32|64)rr$")>;
+def : InstRW<[ADLPWriteResGroup118], (instregex "^LSL(16|32|64)rr$")>;
-def ADLPWriteResGroup109 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11, ADLPPort05]> {
- let Latency = 24;
- let NumMicroOps = 3;
+def ADLPWriteResGroup119 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 3;
+ let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup109], (instregex "^MMX_CVT(T?)PD2PIrm$")>;
+def : InstRW<[ADLPWriteResGroup119], (instrs MFENCE)>;
-def ADLPWriteResGroup110 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
+def ADLPWriteResGroup120 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
let Latency = 8;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup110], (instregex "^MMX_CVT(T?)PD2PIrr$")>;
+def : InstRW<[ADLPWriteResGroup120], (instregex "^MMX_CVT(T?)PD2PIrr$")>;
-def ADLPWriteResGroup111 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
+def ADLPWriteResGroup121 : SchedWriteRes<[ADLPPort00_01, ADLPPort05]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup111], (instrs MMX_CVTPI2PDrr)>;
+def : InstRW<[ADLPWriteResGroup121], (instrs MMX_CVTPI2PDrr)>;
-def ADLPWriteResGroup112 : SchedWriteRes<[ADLPPort00, ADLPPort00_01]> {
- let Latency = 7;
+def ADLPWriteResGroup122 : SchedWriteRes<[ADLPPort00, ADLPPort00_01]> {
+ let Latency = 6;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup112], (instrs MMX_CVTPI2PSrr)>;
+def : InstRW<[ADLPWriteResGroup122], (instrs MMX_CVTPI2PSrr)>;
-def ADLPWriteResGroup113 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
- let Latency = 13;
+def ADLPWriteResGroup123 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
+ let Latency = 11;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup113], (instregex "^MMX_CVT(T?)PS2PIrm$")>;
+def : InstRW<[ADLPWriteResGroup123], (instregex "^MMX_CVT(T?)PS2PIrm$")>;
-def ADLPWriteResGroup114 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05]> {
+def ADLPWriteResGroup124 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05]> {
let Latency = 9;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup114], (instregex "^MMX_CVT(T?)PS2PIrr$")>;
+def : InstRW<[ADLPWriteResGroup124], (instregex "^MMX_CVT(T?)PS2PIrr$")>;
-def ADLPWriteResGroup115 : SchedWriteRes<[ADLPPort00, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup125 : SchedWriteRes<[ADLPPort00, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [2, 1, 1];
let Latency = 12;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup115], (instregex "^MMX_MASKMOVQ((64)?)$")>;
+def : InstRW<[ADLPWriteResGroup125], (instregex "^MMX_MASKMOVQ((64)?)$")>;
-def ADLPWriteResGroup116 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
- let Latency = 18;
+def ADLPWriteResGroup126 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_05]> {
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup116], (instrs MMX_MOVD64mr)>;
+def : InstRW<[ADLPWriteResGroup126], (instrs MMX_MOVDQ2Qrr)>;
-def ADLPWriteResGroup117 : SchedWriteRes<[ADLPPort02_03_11]> {
- let Latency = 8;
-}
-def : InstRW<[ADLPWriteResGroup117], (instregex "^MMX_MOV(D|Q)64rm$",
- "^VBROADCAST(F|I)128$",
- "^VBROADCASTS(D|S)Yrm$",
- "^VMOV(D|SH|SL)DUPYrm$",
- "^VPBROADCAST(D|Q)Yrm$")>;
-def : InstRW<[ADLPWriteResGroup117], (instrs MMX_MOVD64to64rm)>;
-
-def ADLPWriteResGroup118 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_05]> {
+def ADLPWriteResGroup127 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_05]> {
let Latency = 3;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup118], (instregex "^MMX_MOV(DQ|FR64)2Qrr$")>;
+def : InstRW<[ADLPWriteResGroup127], (instrs MMX_MOVFR642Qrr)>;
-def ADLPWriteResGroup119 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05]> {
+def ADLPWriteResGroup128 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05]> {
let Latency = 3;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup119], (instregex "^MMX_MOVQ2(DQ|FR64)rr$")>;
+def : InstRW<[ADLPWriteResGroup128], (instregex "^MMX_MOVQ2(DQ|FR64)rr$")>;
-def ADLPWriteResGroup120 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup129 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [1, 2];
- let Latency = 12;
+ let Latency = 10;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup120, ReadAfterVecLd], (instregex "^MMX_PACKSS(DW|WB)rm$")>;
-def : InstRW<[ADLPWriteResGroup120, ReadAfterVecLd], (instrs MMX_PACKUSWBrm)>;
+def : InstRW<[ADLPWriteResGroup129, ReadAfterVecLd], (instregex "^MMX_PACKSS(DW|WB)rm$")>;
+def : InstRW<[ADLPWriteResGroup129, ReadAfterVecLd], (instrs MMX_PACKUSWBrm)>;
-def ADLPWriteResGroup121 : SchedWriteRes<[ADLPPort05]> {
+def ADLPWriteResGroup130 : SchedWriteRes<[ADLPPort05]> {
let ResourceCycles = [2];
let Latency = 4;
- let NumMicroOps = 2;
+ let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup121], (instregex "^MMX_PACKSS(DW|WB)rr$")>;
-def : InstRW<[ADLPWriteResGroup121], (instrs MMX_PACKUSWBrr)>;
-def : InstRW<[ADLPWriteResGroup121, ReadDefault, ReadInt2Fpu], (instrs MMX_PINSRWrr)>;
+def : InstRW<[ADLPWriteResGroup130], (instregex "^MMX_PACKSS(DW|WB)rr$")>;
+def : InstRW<[ADLPWriteResGroup130], (instrs MMX_PACKUSWBrr)>;
-def ADLPWriteResGroup122 : SchedWriteRes<[ADLPPort00_05, ADLPPort02_03_11]> {
- let Latency = 9;
+def ADLPWriteResGroup131 : SchedWriteRes<[ADLPPort00_05, ADLPPort02_03_11]> {
+ let Latency = 7;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup122, ReadAfterVecLd], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rm$")>;
+def : InstRW<[ADLPWriteResGroup131, ReadAfterVecLd], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rm$")>;
-def ADLPWriteResGroup123 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup132 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [1, 1, 2];
let Latency = 11;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup123, ReadAfterVecLd], (instregex "^MMX_PH(ADD|SUB)SWrm$")>;
+def : InstRW<[ADLPWriteResGroup132, ReadAfterVecLd], (instregex "^MMX_PH(ADD|SUB)SWrm$")>;
-def ADLPWriteResGroup124 : SchedWriteRes<[ADLPPort00, ADLPPort05]> {
+def ADLPWriteResGroup133 : SchedWriteRes<[ADLPPort00, ADLPPort05]> {
let ResourceCycles = [1, 2];
let Latency = 3;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup124], (instregex "^MMX_PH(ADD|SUB)SWrr$")>;
+def : InstRW<[ADLPWriteResGroup133], (instregex "^MMX_PH(ADD|SUB)SWrr$")>;
-def ADLPWriteResGroup125 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
- let Latency = 9;
+def ADLPWriteResGroup134 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+ let Latency = 7;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup134], (instregex "^VPBROADCAST(B|W)rm$")>;
+def : InstRW<[ADLPWriteResGroup134, ReadAfterLd], (instrs MMX_PINSRWrm)>;
+def : InstRW<[ADLPWriteResGroup134, ReadAfterVecXLd], (instregex "^(V?)PALIGNRrmi$")>;
+
+def ADLPWriteResGroup135 : SchedWriteRes<[ADLPPort05]> {
+ let ResourceCycles = [2];
+ let Latency = 2;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup125], (instregex "^VPBROADCAST(B|W)Yrm$")>;
-def : InstRW<[ADLPWriteResGroup125, ReadAfterLd], (instrs MMX_PINSRWrm)>;
-def : InstRW<[ADLPWriteResGroup125, ReadAfterVecYLd], (instrs VPALIGNRYrmi)>;
+def : InstRW<[ADLPWriteResGroup135, ReadDefault, ReadInt2Fpu], (instrs MMX_PINSRWrr)>;
-def ADLPWriteResGroup126 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup136 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
let Latency = 5;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup126], (instregex "^MOV16ao(16|32|64)$")>;
+def : InstRW<[ADLPWriteResGroup136], (instregex "^MOV16ao(16|32)$",
+ "^POP64r((mr)?)$")>;
-def ADLPWriteResGroup127 : SchedWriteRes<[ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup137 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup137], (instregex "^MOV(8|16|32)mi$",
+ "^MOV(8|16|32|64)mr$")>;
+def : InstRW<[ADLPWriteResGroup137], (instrs MOV64mi32)>;
+
+def ADLPWriteResGroup138 : SchedWriteRes<[ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 12;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup127], (instregex "^PUSH(F|G)S(16|32)$")>;
-def : InstRW<[ADLPWriteResGroup127], (instrs MOV16ms,
+def : InstRW<[ADLPWriteResGroup138], (instregex "^PUSH(F|G)S(16|32)$")>;
+def : InstRW<[ADLPWriteResGroup138], (instrs MOV16ms,
MOVBE32mr)>;
-def ADLPWriteResGroup128 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
+def ADLPWriteResGroup139 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 5;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup139], (instregex "^MOV16o(16|32)a$")>;
+
+def ADLPWriteResGroup140 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 2;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup140], (instregex "^MOV(8|16|32|64)o64a$")>;
+
+def ADLPWriteResGroup141 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup128], (instregex "^MOV(16|32|64)rs$",
+def : InstRW<[ADLPWriteResGroup141], (instregex "^MOV(16|32|64)rs$",
"^S(TR|LDT)16r$")>;
-def ADLPWriteResGroup129 : SchedWriteRes<[ADLPPort02_03_11]>;
-def : InstRW<[ADLPWriteResGroup129], (instregex "^MOV32ao(16|32|64)$")>;
-def : InstRW<[ADLPWriteResGroup129], (instrs MOV64ao64)>;
+def ADLPWriteResGroup142 : SchedWriteRes<[ADLPPort02_03_11]>;
+def : InstRW<[ADLPWriteResGroup142], (instregex "^MOV32ao(16|32)$")>;
-def ADLPWriteResGroup130 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup143 : SchedWriteRes<[ADLPPort02_03_11]> {
+ let Latency = 5;
+}
+def : InstRW<[ADLPWriteResGroup143], (instregex "^MOV(32|64)ao64$")>;
+def : InstRW<[ADLPWriteResGroup143], (instrs MOV64ao32)>;
+
+def ADLPWriteResGroup144 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup130], (instregex "^MOV(8|32)o(16|32)a$",
- "^MOV(8|32|64)o64a$")>;
+def : InstRW<[ADLPWriteResGroup144], (instregex "^MOV(8|32)o(16|32)a$",
+ "^PUSH64r((mr)?)$")>;
-def ADLPWriteResGroup131 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
+def ADLPWriteResGroup145 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
let Latency = 0;
}
-def : InstRW<[ADLPWriteResGroup131], (instregex "^MOV32rr((_REV)?)$",
+def : InstRW<[ADLPWriteResGroup145], (instregex "^MOV(32|64)rr((_REV)?)$",
"^MOVZX(32|64)rr8$")>;
-def : InstRW<[ADLPWriteResGroup131], (instrs MOVZX32rr8_NOREX)>;
-
-def ADLPWriteResGroup132 : SchedWriteRes<[ADLPPort02_03_11]> {
- let Latency = 5;
-}
-def : InstRW<[ADLPWriteResGroup132], (instrs MOV64ao32)>;
+def : InstRW<[ADLPWriteResGroup145], (instrs MOVZX32rr8_NOREX)>;
-def ADLPWriteResGroup133 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup146 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [1, 2, 4, 16, 7, 2, 2, 12, 2];
let Latency = 217;
let NumMicroOps = 48;
}
-def : InstRW<[ADLPWriteResGroup133], (instrs MOV64dr)>;
+def : InstRW<[ADLPWriteResGroup146], (instrs MOV64dr)>;
-def ADLPWriteResGroup134 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup147 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 12;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup134], (instrs MOV64o32a)>;
+def : InstRW<[ADLPWriteResGroup147], (instregex "^PUSH(16|32)i8$",
+ "^PUSH32r((mr)?)$")>;
+def : InstRW<[ADLPWriteResGroup147], (instrs MOV64o32a,
+ MOVLPSmr,
+ PUSHi32)>;
-def ADLPWriteResGroup135 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort05]> {
+def ADLPWriteResGroup148 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort05]> {
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup135], (instrs MOV64rc)>;
+def : InstRW<[ADLPWriteResGroup148], (instrs MOV64rc)>;
-def ADLPWriteResGroup136 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort05]> {
+def ADLPWriteResGroup149 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort05]> {
let ResourceCycles = [3, 4, 8, 4, 2, 3];
let Latency = 181;
let NumMicroOps = 24;
}
-def : InstRW<[ADLPWriteResGroup136], (instrs MOV64rd)>;
+def : InstRW<[ADLPWriteResGroup149], (instrs MOV64rd)>;
-def ADLPWriteResGroup137 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup150 : SchedWriteRes<[ADLPPort05]> {
+ let Latency = 3;
+}
+def : InstRW<[ADLPWriteResGroup150], (instregex "^(V?)MOV64toSDrr$",
+ "^(V?)MOVDI2SSrr$",
+ "^(V?)PACK(S|U)S(DW|WB)rr$",
+ "^(V?)PCMPGTQrr$",
+ "^VPACK(S|U)S(DW|WB)Yrr$")>;
+def : InstRW<[ADLPWriteResGroup150], (instrs VPCMPGTQYrr)>;
+
+def ADLPWriteResGroup151 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup137], (instregex "^MOV8ao(16|32|64)$")>;
+def : InstRW<[ADLPWriteResGroup151], (instregex "^MOV8ao(16|32)$")>;
-def ADLPWriteResGroup138 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup152 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 13;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup138], (instregex "^MOV8m(i|r)$")>;
-def : InstRW<[ADLPWriteResGroup138], (instrs MOV8mr_NOREX)>;
+def : InstRW<[ADLPWriteResGroup152], (instrs MOV8mr_NOREX)>;
-def ADLPWriteResGroup139 : SchedWriteRes<[ADLPPort00_06, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup153 : SchedWriteRes<[ADLPPort00_06, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 12;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup139], (instrs MOVBE16mr)>;
+def : InstRW<[ADLPWriteResGroup153], (instrs MOVBE16mr)>;
-def ADLPWriteResGroup140 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11]> {
+def ADLPWriteResGroup154 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort02_03_11]> {
let Latency = 7;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup140], (instrs MOVBE16rm)>;
+def : InstRW<[ADLPWriteResGroup154], (instrs MOVBE16rm)>;
-def ADLPWriteResGroup141 : SchedWriteRes<[ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup155 : SchedWriteRes<[ADLPPort01, ADLPPort02_03_11]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup141], (instrs MOVBE32rm)>;
+def : InstRW<[ADLPWriteResGroup155], (instrs MOVBE32rm)>;
-def ADLPWriteResGroup142 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup156 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 12;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup142], (instrs MOVBE64mr,
- PUSHF16,
+def : InstRW<[ADLPWriteResGroup156], (instrs MOVBE64mr,
SLDT16m,
STRm)>;
-def ADLPWriteResGroup143 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup157 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
let Latency = 7;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup143], (instrs MOVBE64rm)>;
+def : InstRW<[ADLPWriteResGroup157], (instrs MOVBE64rm)>;
-def ADLPWriteResGroup144 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup158 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup144], (instregex "^MOVDIR64B(16|32|64)$")>;
+def : InstRW<[ADLPWriteResGroup158], (instregex "^MOVDIR64B(16|32|64)$")>;
-def ADLPWriteResGroup145 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup159 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 511;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup145], (instrs MOVDIRI32)>;
+def : InstRW<[ADLPWriteResGroup159], (instrs MOVDIRI32)>;
-def ADLPWriteResGroup146 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup160 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 514;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup146], (instrs MOVDIRI64)>;
+def : InstRW<[ADLPWriteResGroup160], (instrs MOVDIRI64)>;
-def ADLPWriteResGroup147 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
- let Latency = 8;
+def ADLPWriteResGroup161 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
+ let Latency = 7;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup147, ReadAfterVecXLd], (instregex "^(V?)MOVLP(D|S)rm$",
+def : InstRW<[ADLPWriteResGroup161, ReadAfterVecXLd], (instregex "^(V?)MOVLP(D|S)rm$",
"^(V?)SHUFP(D|S)rmi$")>;
-def ADLPWriteResGroup148 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup162 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 512;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup148], (instrs MOVNTDQmr)>;
+def : InstRW<[ADLPWriteResGroup162], (instrs MOVNTDQmr)>;
-def ADLPWriteResGroup149 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup163 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 518;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup149], (instrs MOVNTImr)>;
+def : InstRW<[ADLPWriteResGroup163], (instrs MOVNTImr)>;
-def ADLPWriteResGroup150 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup164 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [4, 1, 1, 1];
let Latency = 8;
let NumMicroOps = 7;
}
-def : InstRW<[ADLPWriteResGroup150], (instrs MOVSB)>;
+def : InstRW<[ADLPWriteResGroup164], (instrs MOVSB)>;
-def ADLPWriteResGroup151 : SchedWriteRes<[ADLPPort00_01_05]>;
-def : InstRW<[ADLPWriteResGroup151], (instregex "^(V?)MOVS(D|S)rr((_REV)?)$",
+def ADLPWriteResGroup165 : SchedWriteRes<[ADLPPort00_01_05]>;
+def : InstRW<[ADLPWriteResGroup165], (instregex "^(V?)MOVS(D|S)rr((_REV)?)$",
"^(V?)P(ADD|SUB)(B|D|Q|W)rr$",
"^VP(ADD|SUB)(B|D|Q|W)Yrr$")>;
-def : InstRW<[ADLPWriteResGroup151], (instrs VPBLENDDrri)>;
+def : InstRW<[ADLPWriteResGroup165], (instrs VPBLENDDrri)>;
-def ADLPWriteResGroup152 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup166 : SchedWriteRes<[ADLPPort01_05]>;
+def : InstRW<[ADLPWriteResGroup166], (instregex "^(V?)MOVS(H|L)DUPrr$",
+ "^(V?)SHUFP(D|S)rri$",
+ "^VMOVS(H|L)DUPYrr$",
+ "^VSHUFP(D|S)Yrri$")>;
+def : InstRW<[ADLPWriteResGroup166], (instrs VPBLENDWYrri)>;
+
+def ADLPWriteResGroup167 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [4, 1, 1, 1];
let Latency = 7;
let NumMicroOps = 7;
}
-def : InstRW<[ADLPWriteResGroup152], (instregex "^MOVS(L|Q|W)$")>;
+def : InstRW<[ADLPWriteResGroup167], (instregex "^MOVS(L|Q|W)$")>;
-def ADLPWriteResGroup153 : SchedWriteRes<[ADLPPort02_03_11]> {
+def ADLPWriteResGroup168 : SchedWriteRes<[ADLPPort02_03_11]> {
let Latency = 6;
}
-def : InstRW<[ADLPWriteResGroup153], (instregex "^MOVSX(16|32|64)rm(16|32)$",
- "^MOVSX(32|64)rm8$")>;
-def : InstRW<[ADLPWriteResGroup153], (instrs MOVSX32rm8_NOREX)>;
+def : InstRW<[ADLPWriteResGroup168], (instregex "^MOVSX(32|64)rm(8|16|32)$",
+ "^VPBROADCAST(D|Q)rm$")>;
+def : InstRW<[ADLPWriteResGroup168], (instrs MOVSX32rm8_NOREX,
+ VBROADCASTSSrm)>;
-def ADLPWriteResGroup154 : SchedWriteRes<[ADLPPort01_05_10, ADLPPort02_03_11]> {
- let Latency = 6;
- let NumMicroOps = 2;
-}
-def : InstRW<[ADLPWriteResGroup154], (instrs MOVSX16rm8)>;
-
-def ADLPWriteResGroup155 : SchedWriteRes<[ADLPPort01_05_10]>;
-def : InstRW<[ADLPWriteResGroup155], (instregex "^MOVSX(16|32|64)rr(8|16|32)$")>;
-def : InstRW<[ADLPWriteResGroup155], (instrs MOVSX32rr8_NOREX)>;
-
-def ADLPWriteResGroup156 : SchedWriteRes<[ADLPPort00, ADLPPort02_03]> {
+def ADLPWriteResGroup169 : SchedWriteRes<[ADLPPort00, ADLPPort02_03]> {
let Latency = 11;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup156], (instregex "^MUL_F(32|64)m$")>;
+def : InstRW<[ADLPWriteResGroup169], (instregex "^MUL_F(32|64)m$")>;
-def ADLPWriteResGroup157 : SchedWriteRes<[ADLPPort00, ADLPPort02_03, ADLPPort05]> {
+def ADLPWriteResGroup170 : SchedWriteRes<[ADLPPort00, ADLPPort02_03, ADLPPort05]> {
let Latency = 14;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup157], (instregex "^MUL_FI(16|32)m$")>;
+def : InstRW<[ADLPWriteResGroup170], (instregex "^MUL_FI(16|32)m$")>;
-def ADLPWriteResGroup158 : SchedWriteRes<[ADLPPort00]> {
+def ADLPWriteResGroup171 : SchedWriteRes<[ADLPPort00]> {
let Latency = 4;
}
-def : InstRW<[ADLPWriteResGroup158], (instregex "^MUL_F(P?)rST0$")>;
-def : InstRW<[ADLPWriteResGroup158], (instrs MUL_FST0r)>;
+def : InstRW<[ADLPWriteResGroup171], (instregex "^MUL_F(P?)rST0$")>;
+def : InstRW<[ADLPWriteResGroup171], (instrs MUL_FST0r)>;
-def ADLPWriteResGroup159 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort05, ADLPPort06]> {
+def ADLPWriteResGroup172 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort05, ADLPPort06]> {
let ResourceCycles = [7, 1, 2];
let Latency = 20;
let NumMicroOps = 10;
}
-def : InstRW<[ADLPWriteResGroup159], (instrs MWAITrr)>;
+def : InstRW<[ADLPWriteResGroup172], (instrs MWAITrr)>;
-def ADLPWriteResGroup160 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup173 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [6, 4, 1, 28, 15, 7, 1, 16, 1];
let Latency = 35;
let NumMicroOps = 79;
}
-def : InstRW<[ADLPWriteResGroup160], (instrs OUT16ir)>;
+def : InstRW<[ADLPWriteResGroup173], (instrs OUT16ir)>;
-def ADLPWriteResGroup161 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup174 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [6, 6, 27, 15, 7, 1, 16, 1];
let Latency = 35;
let NumMicroOps = 79;
}
-def : InstRW<[ADLPWriteResGroup161], (instrs OUT16rr)>;
+def : InstRW<[ADLPWriteResGroup174], (instrs OUT16rr)>;
-def ADLPWriteResGroup162 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup175 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [6, 4, 1, 30, 15, 9, 1, 18, 1];
let Latency = 35;
let NumMicroOps = 85;
}
-def : InstRW<[ADLPWriteResGroup162], (instrs OUT32ir)>;
+def : InstRW<[ADLPWriteResGroup175], (instrs OUT32ir)>;
-def ADLPWriteResGroup163 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup176 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [6, 6, 29, 15, 9, 1, 18, 1];
let Latency = 35;
let NumMicroOps = 85;
}
-def : InstRW<[ADLPWriteResGroup163], (instrs OUT32rr)>;
+def : InstRW<[ADLPWriteResGroup176], (instrs OUT32rr)>;
-def ADLPWriteResGroup164 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup177 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [5, 5, 1, 25, 15, 5, 1, 15, 1];
let Latency = 35;
let NumMicroOps = 73;
}
-def : InstRW<[ADLPWriteResGroup164], (instrs OUT8ir)>;
+def : InstRW<[ADLPWriteResGroup177], (instrs OUT8ir)>;
-def ADLPWriteResGroup165 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup178 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [5, 5, 26, 15, 5, 1, 15, 1];
let Latency = 35;
let NumMicroOps = 73;
}
-def : InstRW<[ADLPWriteResGroup165], (instrs OUT8rr)>;
+def : InstRW<[ADLPWriteResGroup178], (instrs OUT8rr)>;
-def ADLPWriteResGroup166 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup179 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [7, 6, 25, 16, 7, 1, 17, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 80;
}
-def : InstRW<[ADLPWriteResGroup166], (instrs OUTSB)>;
+def : InstRW<[ADLPWriteResGroup179], (instrs OUTSB)>;
-def ADLPWriteResGroup167 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup180 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [7, 6, 28, 16, 10, 1, 20, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 89;
}
-def : InstRW<[ADLPWriteResGroup167], (instrs OUTSL)>;
+def : InstRW<[ADLPWriteResGroup180], (instrs OUTSL)>;
-def ADLPWriteResGroup168 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup181 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [6, 1, 5, 27, 16, 8, 1, 18, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 83;
}
-def : InstRW<[ADLPWriteResGroup168], (instrs OUTSW)>;
+def : InstRW<[ADLPWriteResGroup181], (instrs OUTSW)>;
-def ADLPWriteResGroup169 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
- let Latency = 10;
+def ADLPWriteResGroup182 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+ let Latency = 9;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup169, ReadAfterVecXLd], (instregex "^(V?)PACK(S|U)S(DW|WB)rm$",
+def : InstRW<[ADLPWriteResGroup182, ReadAfterVecXLd], (instregex "^(V?)PACK(S|U)S(DW|WB)rm$",
"^(V?)PCMPGTQrm$")>;
-def ADLPWriteResGroup170 : SchedWriteRes<[ADLPPort05]> {
- let Latency = 3;
-}
-def : InstRW<[ADLPWriteResGroup170], (instregex "^(V?)PACK(S|U)S(DW|WB)rr$",
- "^(V?)PCMPGTQrr$",
- "^VPACK(S|U)S(DW|WB)Yrr$")>;
-def : InstRW<[ADLPWriteResGroup170], (instrs VPCMPGTQYrr)>;
-
-def ADLPWriteResGroup171 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
- let Latency = 8;
- let NumMicroOps = 2;
-}
-def : InstRW<[ADLPWriteResGroup171, ReadAfterVecXLd], (instregex "^(V?)P(ADD|SUB)(B|D|Q|W)rm$")>;
-def : InstRW<[ADLPWriteResGroup171, ReadAfterVecXLd], (instrs VPBLENDDrmi)>;
-
-def ADLPWriteResGroup172 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
- let Latency = 8;
+def ADLPWriteResGroup183 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
+ let Latency = 7;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup172], (instregex "^VPBROADCAST(B|W)rm$")>;
-def : InstRW<[ADLPWriteResGroup172, ReadAfterVecXLd], (instregex "^(V?)PALIGNRrmi$")>;
+def : InstRW<[ADLPWriteResGroup183, ReadAfterVecXLd], (instregex "^(V?)PADD(B|D|Q|W)rm$",
+ "^(V?)PSUB(B|D|W)rm$")>;
+def : InstRW<[ADLPWriteResGroup183, ReadAfterVecXLd], (instrs VPBLENDDrmi,
+ VPSUBQrm)>;
-def ADLPWriteResGroup173 : SchedWriteRes<[ADLPPort05]>;
-def : InstRW<[ADLPWriteResGroup173], (instregex "^(V?)PALIGNRrri$",
+def ADLPWriteResGroup184 : SchedWriteRes<[ADLPPort05]>;
+def : InstRW<[ADLPWriteResGroup184], (instregex "^(V?)PALIGNRrri$",
"^VPBROADCAST(B|D|Q|W)rr$")>;
-def : InstRW<[ADLPWriteResGroup173], (instrs VPALIGNRYrri)>;
+def : InstRW<[ADLPWriteResGroup184], (instrs VPALIGNRYrri)>;
-def ADLPWriteResGroup174 : SchedWriteRes<[ADLPPort00_06, ADLPPort05]> {
+def ADLPWriteResGroup185 : SchedWriteRes<[ADLPPort00_06, ADLPPort05]> {
let Latency = 4;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup174], (instrs PAUSE)>;
+def : InstRW<[ADLPWriteResGroup185], (instrs PAUSE)>;
-def ADLPWriteResGroup175 : SchedWriteRes<[ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup186 : SchedWriteRes<[ADLPPort01, ADLPPort02_03_11]> {
let Latency = 8;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup175, ReadAfterLd], (instregex "^P(DEP|EXT)(32|64)rm$")>;
+def : InstRW<[ADLPWriteResGroup186, ReadAfterLd], (instregex "^P(DEP|EXT)(32|64)rm$")>;
-def ADLPWriteResGroup176 : SchedWriteRes<[ADLPPort01_05, ADLPPort04_09, ADLPPort07_08]> {
- let Latency = 12;
+def ADLPWriteResGroup187 : SchedWriteRes<[ADLPPort01]> {
+ let Latency = 3;
+}
+def : InstRW<[ADLPWriteResGroup187], (instregex "^P(DEP|EXT)(32|64)rr$")>;
+
+def ADLPWriteResGroup188 : SchedWriteRes<[ADLPPort01_05, ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 19;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup176], (instregex "^(V?)PEXTR(D|Q)mr$")>;
+def : InstRW<[ADLPWriteResGroup188], (instrs PEXTRBmr)>;
-def ADLPWriteResGroup177 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup189 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_11]> {
let ResourceCycles = [1, 2, 1];
- let Latency = 9;
+ let Latency = 8;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup177, ReadAfterVecXLd], (instregex "^(V?)PH(ADD|SUB)SWrm$")>;
+def : InstRW<[ADLPWriteResGroup189, ReadAfterVecXLd], (instregex "^(V?)PH(ADD|SUB)SWrm$")>;
-def ADLPWriteResGroup178 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05]> {
+def ADLPWriteResGroup190 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05]> {
let ResourceCycles = [1, 2];
let Latency = 2;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup178], (instregex "^(V?)PH(ADD|SUB)SWrr$",
+def : InstRW<[ADLPWriteResGroup190], (instregex "^(V?)PH(ADD|SUB)SWrr$",
"^VPH(ADD|SUB)SWYrr$")>;
-def ADLPWriteResGroup179 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup191 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
+ let Latency = 8;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup191, ReadAfterLd], (instrs PINSRWrm)>;
+def : InstRW<[ADLPWriteResGroup191, ReadAfterVecXLd], (instrs PUNPCKLQDQrm)>;
+def : InstRW<[ADLPWriteResGroup191, ReadAfterVecYLd], (instregex "^VSHUFP(D|S)Yrmi$")>;
+def : InstRW<[ADLPWriteResGroup191, ReadAfterVecYLd], (instrs VPBLENDWYrmi)>;
+
+def ADLPWriteResGroup192 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 12;
+ let NumMicroOps = 4;
+}
+def : InstRW<[ADLPWriteResGroup192], (instregex "^P(OP|USH)16rmm$")>;
+
+def ADLPWriteResGroup193 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 12;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup179], (instregex "^POP(16|32|64)rmm$",
- "^PUSH(16|32)rmm$")>;
+def : InstRW<[ADLPWriteResGroup193], (instregex "^POP(32|64)rmm$")>;
+def : InstRW<[ADLPWriteResGroup193], (instrs PUSH32rmm)>;
-def ADLPWriteResGroup180 : SchedWriteRes<[ADLPPort02_03]> {
+def ADLPWriteResGroup194 : SchedWriteRes<[ADLPPort02_03]> {
let Latency = 5;
}
-def : InstRW<[ADLPWriteResGroup180], (instregex "^POPA(16|32)$",
- "^PREFETCHIT(0|1)$")>;
-def : InstRW<[ADLPWriteResGroup180], (instrs POPF32)>;
+def : InstRW<[ADLPWriteResGroup194], (instregex "^POPA(16|32)$")>;
+def : InstRW<[ADLPWriteResGroup194], (instrs POPF32)>;
-def ADLPWriteResGroup181 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup195 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
let ResourceCycles = [6, 2, 1, 1];
let Latency = 5;
let NumMicroOps = 10;
}
-def : InstRW<[ADLPWriteResGroup181], (instrs POPF16)>;
+def : InstRW<[ADLPWriteResGroup195], (instrs POPF16)>;
-def ADLPWriteResGroup182 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup196 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort02_03_11]> {
let ResourceCycles = [2, 1, 1];
let Latency = 5;
let NumMicroOps = 7;
}
-def : InstRW<[ADLPWriteResGroup182], (instrs POPF64)>;
+def : InstRW<[ADLPWriteResGroup196], (instrs POPF64)>;
-def ADLPWriteResGroup183 : SchedWriteRes<[ADLPPort02_03_11]> {
+def ADLPWriteResGroup197 : SchedWriteRes<[ADLPPort02_03_11]> {
let Latency = 0;
}
-def : InstRW<[ADLPWriteResGroup183], (instregex "^PREFETCHT(0|1|2)$")>;
-def : InstRW<[ADLPWriteResGroup183], (instrs PREFETCHNTA)>;
+def : InstRW<[ADLPWriteResGroup197], (instregex "^PREFETCHT(0|1|2)$")>;
+def : InstRW<[ADLPWriteResGroup197], (instrs PREFETCHNTA)>;
-def ADLPWriteResGroup184 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort06]> {
+def ADLPWriteResGroup198 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
+ let Latency = 8;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup198, ReadAfterVecXLd], (instrs PSUBQrm)>;
+def : InstRW<[ADLPWriteResGroup198, ReadAfterVecYLd], (instregex "^VP(ADD|SUB)(B|D|Q|W)Yrm$")>;
+
+def ADLPWriteResGroup199 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort06]> {
let ResourceCycles = [1, 1, 2];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup184], (instregex "^PTWRITE((64)?)m$")>;
+def : InstRW<[ADLPWriteResGroup199], (instregex "^PTWRITE((64)?)m$")>;
-def ADLPWriteResGroup185 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort06]> {
+def ADLPWriteResGroup200 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort06]> {
let ResourceCycles = [1, 2];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup185], (instrs PTWRITE64r)>;
+def : InstRW<[ADLPWriteResGroup200], (instrs PTWRITE64r)>;
-def ADLPWriteResGroup186 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort06]> {
+def ADLPWriteResGroup201 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort06]> {
let ResourceCycles = [2, 2];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup186], (instrs PTWRITEr)>;
+def : InstRW<[ADLPWriteResGroup201], (instrs PTWRITEr)>;
-def ADLPWriteResGroup187 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
- let NumMicroOps = 2;
+def ADLPWriteResGroup202 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 12;
+ let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup187], (instregex "^PUSH64r((mr)?)$")>;
+def : InstRW<[ADLPWriteResGroup202], (instregex "^PUSH16r((mr)?)$",
+ "^PUSH64i(8|32)$")>;
+def : InstRW<[ADLPWriteResGroup202], (instrs PUSHi16)>;
-def ADLPWriteResGroup188 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
- let NumMicroOps = 3;
+def ADLPWriteResGroup203 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+ let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup188], (instrs PUSH64rmm)>;
+def : InstRW<[ADLPWriteResGroup203], (instrs PUSH64rmm)>;
-def ADLPWriteResGroup189 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04]>;
-def : InstRW<[ADLPWriteResGroup189], (instregex "^PUSHA(16|32)$",
+def ADLPWriteResGroup204 : SchedWriteRes<[ADLPPort02_03_07, ADLPPort04]>;
+def : InstRW<[ADLPWriteResGroup204], (instregex "^PUSHA(16|32)$",
"^ST_F(32|64)m$")>;
-def : InstRW<[ADLPWriteResGroup189], (instrs PUSHF32)>;
+def : InstRW<[ADLPWriteResGroup204], (instrs PUSHF32)>;
-def ADLPWriteResGroup190 : SchedWriteRes<[ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup205 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+ let Latency = 12;
+ let NumMicroOps = 5;
+}
+def : InstRW<[ADLPWriteResGroup205], (instrs PUSHF16)>;
+
+def ADLPWriteResGroup206 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 4;
+ let NumMicroOps = 5;
+}
+def : InstRW<[ADLPWriteResGroup206], (instrs PUSHF64)>;
+
+def ADLPWriteResGroup207 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup190], (instrs PUSHF64)>;
+def : InstRW<[ADLPWriteResGroup207], (instregex "^PUSH(F|G)S64$")>;
-def ADLPWriteResGroup191 : SchedWriteRes<[ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
- let NumMicroOps = 3;
+def ADLPWriteResGroup208 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+ let ResourceCycles = [2, 3, 2];
+ let Latency = 19;
+ let NumMicroOps = 7;
}
-def : InstRW<[ADLPWriteResGroup191], (instregex "^PUSH(F|G)S64$")>;
+def : InstRW<[ADLPWriteResGroup208, WriteRMW], (instregex "^RC(L|R)(16|32|64)mCL$")>;
-def ADLPWriteResGroup192 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup209 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
let ResourceCycles = [2, 3, 2];
let Latency = 8;
let NumMicroOps = 7;
}
-def : InstRW<[ADLPWriteResGroup192], (instregex "^RC(L|R)(16|32|64)rCL$")>;
+def : InstRW<[ADLPWriteResGroup209], (instregex "^RC(L|R)(16|32|64)rCL$")>;
-def ADLPWriteResGroup193 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+def ADLPWriteResGroup210 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
let ResourceCycles = [1, 2];
let Latency = 13;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup193, WriteRMW], (instregex "^RC(L|R)8m(1|i)$")>;
+def : InstRW<[ADLPWriteResGroup210, WriteRMW], (instregex "^RC(L|R)8m(1|i)$")>;
-def ADLPWriteResGroup194 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup211 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
let ResourceCycles = [1, 5, 2];
let Latency = 20;
let NumMicroOps = 8;
}
-def : InstRW<[ADLPWriteResGroup194, WriteRMW], (instrs RCL8mCL)>;
+def : InstRW<[ADLPWriteResGroup211, WriteRMW], (instrs RCL8mCL)>;
-def ADLPWriteResGroup195 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup212 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
let ResourceCycles = [2, 5, 2];
let Latency = 7;
let NumMicroOps = 9;
}
-def : InstRW<[ADLPWriteResGroup195], (instrs RCL8rCL)>;
+def : InstRW<[ADLPWriteResGroup212], (instrs RCL8rCL)>;
-def ADLPWriteResGroup196 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup213 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
+ let Latency = 10;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup213, ReadAfterVecLd], (instregex "^(V?)R(CP|SQRT)SSm_Int$")>;
+
+def ADLPWriteResGroup214 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
let ResourceCycles = [2, 4, 3];
let Latency = 20;
let NumMicroOps = 9;
}
-def : InstRW<[ADLPWriteResGroup196, WriteRMW], (instrs RCR8mCL)>;
+def : InstRW<[ADLPWriteResGroup214, WriteRMW], (instrs RCR8mCL)>;
-def ADLPWriteResGroup197 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup215 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
let ResourceCycles = [3, 4, 3];
let Latency = 9;
let NumMicroOps = 10;
}
-def : InstRW<[ADLPWriteResGroup197], (instrs RCR8rCL)>;
+def : InstRW<[ADLPWriteResGroup215], (instrs RCR8rCL)>;
-def ADLPWriteResGroup198 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort01_05_10, ADLPPort05]> {
+def ADLPWriteResGroup216 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort01_05_10, ADLPPort05]> {
let ResourceCycles = [1, 6, 1, 10, 20, 8, 5, 1, 2];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 54;
}
-def : InstRW<[ADLPWriteResGroup198], (instrs RDMSR)>;
+def : InstRW<[ADLPWriteResGroup216], (instrs RDMSR)>;
-def ADLPWriteResGroup199 : SchedWriteRes<[ADLPPort01]> {
+def ADLPWriteResGroup217 : SchedWriteRes<[ADLPPort01]> {
let Latency = AlderlakePModel.MaxLatency;
}
-def : InstRW<[ADLPWriteResGroup199], (instrs RDPID64)>;
+def : InstRW<[ADLPWriteResGroup217], (instrs RDPID64)>;
-def ADLPWriteResGroup200 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup218 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup200], (instrs RDPKRUr)>;
+def : InstRW<[ADLPWriteResGroup218], (instrs RDPKRUr)>;
-def ADLPWriteResGroup201 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
+def ADLPWriteResGroup219 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
let ResourceCycles = [9, 6, 2, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 18;
}
-def : InstRW<[ADLPWriteResGroup201], (instrs RDPMC)>;
+def : InstRW<[ADLPWriteResGroup219], (instrs RDPMC)>;
-def ADLPWriteResGroup202 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup220 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [2, 3, 2, 5, 7, 3, 1, 2];
let Latency = 1386;
let NumMicroOps = 25;
}
-def : InstRW<[ADLPWriteResGroup202], (instrs RDRAND16r)>;
+def : InstRW<[ADLPWriteResGroup220], (instrs RDRAND16r)>;
-def ADLPWriteResGroup203 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup221 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [2, 3, 2, 5, 7, 3, 1, 2];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 25;
}
-def : InstRW<[ADLPWriteResGroup203], (instregex "^RDRAND(32|64)r$")>;
+def : InstRW<[ADLPWriteResGroup221], (instregex "^RDRAND(32|64)r$")>;
-def ADLPWriteResGroup204 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup222 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [2, 3, 3, 5, 7, 1, 4];
let Latency = 1381;
let NumMicroOps = 25;
}
-def : InstRW<[ADLPWriteResGroup204], (instrs RDSEED16r)>;
+def : InstRW<[ADLPWriteResGroup222], (instrs RDSEED16r)>;
-def ADLPWriteResGroup205 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup223 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [2, 3, 3, 5, 7, 1, 4];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 25;
}
-def : InstRW<[ADLPWriteResGroup205], (instregex "^RDSEED(32|64)r$")>;
+def : InstRW<[ADLPWriteResGroup223], (instregex "^RDSEED(32|64)r$")>;
-def ADLPWriteResGroup206 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
+def ADLPWriteResGroup224 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
let ResourceCycles = [5, 6, 3, 1];
let Latency = 18;
let NumMicroOps = 15;
}
-def : InstRW<[ADLPWriteResGroup206], (instrs RDTSC)>;
+def : InstRW<[ADLPWriteResGroup224], (instrs RDTSC)>;
-def ADLPWriteResGroup207 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
+def ADLPWriteResGroup225 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
let ResourceCycles = [2, 2, 1, 2, 7, 4, 3];
let Latency = 42;
let NumMicroOps = 21;
}
-def : InstRW<[ADLPWriteResGroup207], (instrs RDTSCP)>;
+def : InstRW<[ADLPWriteResGroup225], (instrs RDTSCP)>;
-def ADLPWriteResGroup208 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
+def ADLPWriteResGroup226 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort06]> {
let Latency = 7;
- let NumMicroOps = 2;
+ let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup208], (instrs RET64)>;
+def : InstRW<[ADLPWriteResGroup226], (instrs RET64)>;
-def ADLPWriteResGroup209 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
+def ADLPWriteResGroup227 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
let ResourceCycles = [2, 1];
let Latency = 6;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup209], (instregex "^RETI(16|32|64)$")>;
+def : InstRW<[ADLPWriteResGroup227], (instregex "^RETI(16|32)$")>;
-def ADLPWriteResGroup210 : SchedWriteRes<[]>;
-def : InstRW<[ADLPWriteResGroup210], (instrs REX64_PREFIX)>;
+def ADLPWriteResGroup228 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11, ADLPPort06]> {
+ let ResourceCycles = [2, 1, 2];
+ let Latency = 6;
+ let NumMicroOps = 5;
+}
+def : InstRW<[ADLPWriteResGroup228], (instrs RETI64)>;
+
+def ADLPWriteResGroup229 : SchedWriteRes<[]>;
+def : InstRW<[ADLPWriteResGroup229], (instrs REX64_PREFIX)>;
-def ADLPWriteResGroup211 : SchedWriteRes<[ADLPPort00_06]> {
+def ADLPWriteResGroup230 : SchedWriteRes<[ADLPPort00_06]> {
let ResourceCycles = [2];
let Latency = 12;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup211, WriteRMW], (instregex "^RO(L|R)(16|32|64)m(1|i|CL)$")>;
+def : InstRW<[ADLPWriteResGroup230, WriteRMW], (instregex "^RO(L|R)(16|32|64)m1$")>;
-def ADLPWriteResGroup212 : SchedWriteRes<[ADLPPort00_06]> {
+def ADLPWriteResGroup231 : SchedWriteRes<[ADLPPort00_06]> {
let ResourceCycles = [2];
+ let Latency = 7;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup212], (instregex "^RO(L|R)(8|16|32|64)r(1|i)$")>;
+def : InstRW<[ADLPWriteResGroup231, WriteRMW], (instregex "^RO(L|R)(8|16|32|64)mi$")>;
-def ADLPWriteResGroup213 : SchedWriteRes<[ADLPPort00_06]> {
+def ADLPWriteResGroup232 : SchedWriteRes<[ADLPPort00_06]> {
let ResourceCycles = [2];
- let Latency = 13;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup213, WriteRMW], (instregex "^RO(L|R)8m(1|i)$",
- "^(RO|SH)L8mCL$",
- "^(RO|SA|SH)R8mCL$")>;
+def : InstRW<[ADLPWriteResGroup232], (instregex "^RO(L|R)(8|16|32|64)r1$")>;
-def ADLPWriteResGroup214 : SchedWriteRes<[ADLPPort00_06]> {
+def ADLPWriteResGroup233 : SchedWriteRes<[ADLPPort00_06]> {
let ResourceCycles = [2];
- let Latency = 4;
+ let Latency = 13;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup214], (instrs SAHF)>;
+def : InstRW<[ADLPWriteResGroup233, WriteRMW], (instregex "^RO(L|R)8m1$")>;
-def ADLPWriteResGroup215 : SchedWriteRes<[ADLPPort00_06]> {
- let Latency = 13;
+def ADLPWriteResGroup234 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+ let ResourceCycles = [2, 1];
+ let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup215, WriteRMW], (instregex "^S(A|H)R8m(1|i)$",
- "^SHL8m(1|i)$")>;
+def : InstRW<[ADLPWriteResGroup234], (instrs ROR8ri)>;
-def ADLPWriteResGroup216 : SchedWriteRes<[ADLPPort00_06, ADLPPort02_03_11]> {
- let Latency = 8;
+def ADLPWriteResGroup235 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11]> {
+ let ResourceCycles = [2, 1];
+ let Latency = 15;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup235, ReadAfterVecXLd], (instregex "^(V?)ROUNDS(D|S)m$")>;
+
+def ADLPWriteResGroup236 : SchedWriteRes<[ADLPPort00_06]> {
+ let ResourceCycles = [2];
+ let Latency = 4;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup216, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^S(A|H)RX(32|64)rm$",
- "^SHLX(32|64)rm$")>;
+def : InstRW<[ADLPWriteResGroup236], (instrs SAHF)>;
-def ADLPWriteResGroup217 : SchedWriteRes<[ADLPPort00_06]> {
- let Latency = 3;
+def ADLPWriteResGroup237 : SchedWriteRes<[ADLPPort00_06]> {
+ let Latency = 12;
}
-def : InstRW<[ADLPWriteResGroup217], (instregex "^S(A|H)RX(32|64)rr$",
- "^SHLX(32|64)rr$")>;
+def : InstRW<[ADLPWriteResGroup237, WriteRMW], (instregex "^S(A|H)R(16|32|64)m1$",
+ "^SHL(16|32|64)m1$")>;
-def ADLPWriteResGroup218 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup238 : SchedWriteRes<[ADLPPort00_06]> {
+ let Latency = 13;
+}
+def : InstRW<[ADLPWriteResGroup238, WriteRMW], (instregex "^S(A|H)R8m1$")>;
+def : InstRW<[ADLPWriteResGroup238, WriteRMW], (instrs SHL8m1)>;
+
+def ADLPWriteResGroup239 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [2, 2, 1, 1, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 7;
}
-def : InstRW<[ADLPWriteResGroup218], (instrs SERIALIZE)>;
+def : InstRW<[ADLPWriteResGroup239], (instrs SERIALIZE)>;
-def ADLPWriteResGroup219 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup240 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 2;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup219], (instrs SFENCE)>;
+def : InstRW<[ADLPWriteResGroup240], (instrs SFENCE)>;
-def ADLPWriteResGroup220 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup241 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [1, 2, 2, 2];
let Latency = 21;
let NumMicroOps = 7;
}
-def : InstRW<[ADLPWriteResGroup220], (instregex "^S(G|I)DT64m$")>;
+def : InstRW<[ADLPWriteResGroup241], (instregex "^S(G|I)DT64m$")>;
-def ADLPWriteResGroup221 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11, ADLPPort05]> {
- let Latency = 9;
+def ADLPWriteResGroup242 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11, ADLPPort05]> {
+ let Latency = 8;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup221, ReadAfterVecXLd], (instrs SHA1MSG1rm)>;
+def : InstRW<[ADLPWriteResGroup242, ReadAfterVecXLd], (instrs SHA1MSG1rm)>;
-def ADLPWriteResGroup222 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort05]> {
+def ADLPWriteResGroup243 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort05]> {
let Latency = 2;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup222], (instrs SHA1MSG1rr)>;
+def : InstRW<[ADLPWriteResGroup243], (instrs SHA1MSG1rr)>;
-def ADLPWriteResGroup223 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup244 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05, ADLPPort02_03_11]> {
let ResourceCycles = [2, 2, 1, 2, 1];
let Latency = 13;
let NumMicroOps = 8;
}
-def : InstRW<[ADLPWriteResGroup223, ReadAfterVecXLd], (instrs SHA1MSG2rm)>;
+def : InstRW<[ADLPWriteResGroup244, ReadAfterVecXLd], (instrs SHA1MSG2rm)>;
-def ADLPWriteResGroup224 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05]> {
+def ADLPWriteResGroup245 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05]> {
let ResourceCycles = [2, 2, 1, 2];
let Latency = 6;
let NumMicroOps = 7;
}
-def : InstRW<[ADLPWriteResGroup224], (instrs SHA1MSG2rr)>;
+def : InstRW<[ADLPWriteResGroup245], (instrs SHA1MSG2rr)>;
-def ADLPWriteResGroup225 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup246 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
let Latency = 8;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup225, ReadAfterVecXLd], (instrs SHA1NEXTErm)>;
+def : InstRW<[ADLPWriteResGroup246, ReadAfterVecXLd], (instrs SHA1NEXTErm)>;
-def ADLPWriteResGroup226 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort01_05]> {
+def ADLPWriteResGroup247 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort01_05]> {
let Latency = 3;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup226], (instrs SHA1NEXTErr)>;
+def : InstRW<[ADLPWriteResGroup247], (instrs SHA1NEXTErr)>;
-def ADLPWriteResGroup227 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
- let Latency = 13;
+def ADLPWriteResGroup248 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+ let Latency = 12;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup227, ReadAfterVecXLd], (instrs SHA1RNDS4rmi,
+def : InstRW<[ADLPWriteResGroup248, ReadAfterVecXLd], (instrs SHA1RNDS4rmi,
SHA256RNDS2rm)>;
-def ADLPWriteResGroup228 : SchedWriteRes<[ADLPPort05]> {
- let Latency = 6;
+def ADLPWriteResGroup249 : SchedWriteRes<[ADLPPort05]> {
+ let Latency = 4;
}
-def : InstRW<[ADLPWriteResGroup228], (instrs SHA1RNDS4rri,
+def : InstRW<[ADLPWriteResGroup249], (instrs SHA1RNDS4rri,
SHA256RNDS2rr)>;
-def ADLPWriteResGroup229 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup250 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [3, 2, 1, 1, 1];
let Latency = 12;
let NumMicroOps = 8;
}
-def : InstRW<[ADLPWriteResGroup229, ReadAfterVecXLd], (instrs SHA256MSG1rm)>;
+def : InstRW<[ADLPWriteResGroup250, ReadAfterVecXLd], (instrs SHA256MSG1rm)>;
-def ADLPWriteResGroup230 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort05]> {
+def ADLPWriteResGroup251 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort05]> {
let ResourceCycles = [3, 2, 1, 1];
let Latency = 5;
let NumMicroOps = 7;
}
-def : InstRW<[ADLPWriteResGroup230], (instrs SHA256MSG1rr)>;
+def : InstRW<[ADLPWriteResGroup251], (instrs SHA256MSG1rr)>;
-def ADLPWriteResGroup231 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+def ADLPWriteResGroup252 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
let ResourceCycles = [1, 2];
- let Latency = 13;
+ let Latency = 12;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup231, ReadAfterVecXLd], (instrs SHA256MSG2rm)>;
+def : InstRW<[ADLPWriteResGroup252, ReadAfterVecXLd], (instrs SHA256MSG2rm)>;
-def ADLPWriteResGroup232 : SchedWriteRes<[ADLPPort05]> {
+def ADLPWriteResGroup253 : SchedWriteRes<[ADLPPort05]> {
let ResourceCycles = [2];
let Latency = 6;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup232], (instrs SHA256MSG2rr)>;
+def : InstRW<[ADLPWriteResGroup253], (instrs SHA256MSG2rr)>;
-def ADLPWriteResGroup233 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup254 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort07_08]> {
let Latency = 13;
let NumMicroOps = 5;
}
-def : InstRW<[ADLPWriteResGroup233], (instrs SHRD16mri8)>;
+def : InstRW<[ADLPWriteResGroup254], (instrs SHRD16mri8)>;
+
+def ADLPWriteResGroup255 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+ let Latency = 5;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup255], (instrs SHRD16rrCL)>;
-def ADLPWriteResGroup234 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
+def ADLPWriteResGroup256 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup234], (instregex "^SLDT(32|64)r$")>;
+def : InstRW<[ADLPWriteResGroup256], (instregex "^SLDT(32|64)r$")>;
-def ADLPWriteResGroup235 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort05]> {
+def ADLPWriteResGroup257 : SchedWriteRes<[ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+ let Latency = 12;
+ let NumMicroOps = 3;
+}
+def : InstRW<[ADLPWriteResGroup257], (instrs SMSW16m)>;
+
+def ADLPWriteResGroup258 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort05]> {
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup235], (instrs SMSW16r)>;
+def : InstRW<[ADLPWriteResGroup258], (instrs SMSW16r)>;
-def ADLPWriteResGroup236 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort05]> {
+def ADLPWriteResGroup259 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort05]> {
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup236], (instregex "^SMSW(32|64)r$")>;
+def : InstRW<[ADLPWriteResGroup259], (instregex "^SMSW(32|64)r$")>;
-def ADLPWriteResGroup237 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
+def ADLPWriteResGroup260 : SchedWriteRes<[ADLPPort00, ADLPPort02_03_11]> {
let Latency = 24;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup237, ReadAfterVecLd], (instregex "^(V?)SQRTSDm_Int$")>;
+def : InstRW<[ADLPWriteResGroup260, ReadAfterVecLd], (instregex "^(V?)SQRTSDm_Int$")>;
-def ADLPWriteResGroup238 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+def ADLPWriteResGroup261 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
let Latency = 6;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup238], (instrs STD)>;
+def : InstRW<[ADLPWriteResGroup261], (instrs STD)>;
-def ADLPWriteResGroup239 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup262 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01]> {
let ResourceCycles = [1, 4, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 6;
}
-def : InstRW<[ADLPWriteResGroup239], (instrs STI)>;
+def : InstRW<[ADLPWriteResGroup262], (instrs STI)>;
-def ADLPWriteResGroup240 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
- let ResourceCycles = [2, 1, 1];
- let Latency = 8;
- let NumMicroOps = 4;
+def ADLPWriteResGroup263 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+ let Latency = 6;
}
-def : InstRW<[ADLPWriteResGroup240], (instrs STOSB)>;
+def : InstRW<[ADLPWriteResGroup263], (instrs STOSB)>;
-def ADLPWriteResGroup241 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup264 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort04_09, ADLPPort07_08]> {
let ResourceCycles = [2, 1, 1];
let Latency = 7;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup241], (instregex "^STOS(L|Q|W)$")>;
+def : InstRW<[ADLPWriteResGroup264], (instregex "^STOS(L|Q|W)$")>;
-def ADLPWriteResGroup242 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
+def ADLPWriteResGroup265 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort01]> {
let Latency = 5;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup242], (instregex "^STR(32|64)r$")>;
+def : InstRW<[ADLPWriteResGroup265], (instregex "^STR(32|64)r$")>;
-def ADLPWriteResGroup243 : SchedWriteRes<[ADLPPort00]> {
+def ADLPWriteResGroup266 : SchedWriteRes<[ADLPPort00]> {
let Latency = 2;
}
-def : InstRW<[ADLPWriteResGroup243], (instregex "^(TST|XAM)_F$")>;
-def : InstRW<[ADLPWriteResGroup243], (instrs UCOM_FPPr)>;
+def : InstRW<[ADLPWriteResGroup266], (instregex "^(TST|XAM)_F$")>;
+def : InstRW<[ADLPWriteResGroup266], (instrs UCOM_FPPr)>;
-def ADLPWriteResGroup244 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup267 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
let ResourceCycles = [3, 1];
- let Latency = 9;
+ let Latency = 8;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup244, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)rm$")>;
-def : InstRW<[ADLPWriteResGroup244, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBrm)>;
+def : InstRW<[ADLPWriteResGroup267, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)rm$")>;
+def : InstRW<[ADLPWriteResGroup267, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBrm)>;
-def ADLPWriteResGroup245 : SchedWriteRes<[ADLPPort00_01_05]> {
+def ADLPWriteResGroup268 : SchedWriteRes<[ADLPPort00_01_05]> {
let ResourceCycles = [3];
let Latency = 3;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup245], (instregex "^VBLENDVP(D|S)rr$")>;
-def : InstRW<[ADLPWriteResGroup245], (instrs VPBLENDVBrr)>;
+def : InstRW<[ADLPWriteResGroup268], (instregex "^VBLENDVP(D|S)rr$")>;
+def : InstRW<[ADLPWriteResGroup268], (instrs VPBLENDVBrr)>;
-def ADLPWriteResGroup246 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup269 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
let ResourceCycles = [6, 7, 18];
let Latency = 81;
let NumMicroOps = 31;
}
-def : InstRW<[ADLPWriteResGroup246], (instrs VERRm)>;
+def : InstRW<[ADLPWriteResGroup269], (instrs VERRm)>;
-def ADLPWriteResGroup247 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup270 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
let ResourceCycles = [6, 7, 17];
let Latency = 74;
let NumMicroOps = 30;
}
-def : InstRW<[ADLPWriteResGroup247], (instrs VERRr)>;
+def : InstRW<[ADLPWriteResGroup270], (instrs VERRr)>;
-def ADLPWriteResGroup248 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup271 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
let ResourceCycles = [5, 8, 21];
let Latency = 81;
let NumMicroOps = 34;
}
-def : InstRW<[ADLPWriteResGroup248], (instrs VERWm)>;
+def : InstRW<[ADLPWriteResGroup271], (instrs VERWm)>;
-def ADLPWriteResGroup249 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
+def ADLPWriteResGroup272 : SchedWriteRes<[ADLPPort00, ADLPPort01, ADLPPort02_03_11]> {
let ResourceCycles = [5, 8, 20];
let Latency = 74;
let NumMicroOps = 33;
}
-def : InstRW<[ADLPWriteResGroup249], (instrs VERWr)>;
+def : InstRW<[ADLPWriteResGroup272], (instrs VERWr)>;
-def ADLPWriteResGroup250 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup273 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
let ResourceCycles = [1, 1, 2, 4];
let Latency = 29;
let NumMicroOps = 8;
}
-def : InstRW<[ADLPWriteResGroup250, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDYrm$",
+def : InstRW<[ADLPWriteResGroup273, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDYrm$",
"^VPGATHER(D|Q)QYrm$")>;
-def : InstRW<[ADLPWriteResGroup250, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSYrm,
+def : InstRW<[ADLPWriteResGroup273, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSYrm,
VPGATHERQDYrm)>;
-def ADLPWriteResGroup251 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup274 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
let ResourceCycles = [1, 1, 1, 2];
let Latency = 20;
let NumMicroOps = 5;
}
-def : InstRW<[ADLPWriteResGroup251, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDrm$",
+def : InstRW<[ADLPWriteResGroup274, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDrm$",
"^VPGATHER(D|Q)Qrm$")>;
-def : InstRW<[ADLPWriteResGroup251, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSrm,
+def : InstRW<[ADLPWriteResGroup274, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSrm,
VPGATHERQDrm)>;
-def ADLPWriteResGroup252 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup275 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
let ResourceCycles = [1, 1, 2, 8];
let Latency = 30;
let NumMicroOps = 12;
}
-def : InstRW<[ADLPWriteResGroup252, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSYrm,
+def : InstRW<[ADLPWriteResGroup275, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSYrm,
VPGATHERDDYrm)>;
-def ADLPWriteResGroup253 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup276 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05, ADLPPort01_05, ADLPPort02_03_11]> {
let ResourceCycles = [1, 1, 2, 4];
let Latency = 28;
let NumMicroOps = 8;
}
-def : InstRW<[ADLPWriteResGroup253, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSrm,
+def : InstRW<[ADLPWriteResGroup276, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSrm,
VPGATHERDDrm)>;
-def ADLPWriteResGroup254 : SchedWriteRes<[ADLPPort01_05, ADLPPort05]> {
- let ResourceCycles = [1, 2];
- let Latency = 5;
- let NumMicroOps = 3;
+def ADLPWriteResGroup277 : SchedWriteRes<[ADLPPort00_01]> {
+ let Latency = 3;
+}
+def : InstRW<[ADLPWriteResGroup277], (instregex "^VGF2P8AFFINE((INV)?)QB(Y?)rri$",
+ "^VGF2P8MULB(Y?)rr$")>;
+
+def ADLPWriteResGroup278 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11, ADLPPort05]> {
+ let ResourceCycles = [1, 1, 2];
+ let Latency = 13;
+ let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup254], (instregex "^VH(ADD|SUB)P(D|S)rr$")>;
+def : InstRW<[ADLPWriteResGroup278, ReadAfterVecYLd], (instregex "^VH(ADD|SUB)PSYrm$")>;
-def ADLPWriteResGroup255 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup279 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort02_03_11]> {
let Latency = 9;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup255, ReadAfterVecYLd], (instregex "^VINSERT(F|I)128rm$",
- "^VP(ADD|SUB)(B|D|Q|W)Yrm$")>;
+def : InstRW<[ADLPWriteResGroup279, ReadAfterVecYLd], (instregex "^VINSERT(F|I)128rm$")>;
-def ADLPWriteResGroup256 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort02_03_11]> {
+def ADLPWriteResGroup280 : SchedWriteRes<[ADLPPort00, ADLPPort00_06, ADLPPort02_03_11]> {
let Latency = 7;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup256], (instrs VLDMXCSR)>;
+def : InstRW<[ADLPWriteResGroup280], (instrs VLDMXCSR)>;
-def ADLPWriteResGroup257 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03, ADLPPort02_03_07, ADLPPort04, ADLPPort05, ADLPPort06]> {
+def ADLPWriteResGroup281 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03, ADLPPort02_03_07, ADLPPort04, ADLPPort05, ADLPPort06]> {
let ResourceCycles = [8, 1, 1, 1, 1, 1, 2, 3];
let Latency = 40;
let NumMicroOps = 18;
}
-def : InstRW<[ADLPWriteResGroup257], (instrs VMCLEARm)>;
+def : InstRW<[ADLPWriteResGroup281], (instrs VMCLEARm)>;
-def ADLPWriteResGroup258 : SchedWriteRes<[ADLPPort00]> {
+def ADLPWriteResGroup282 : SchedWriteRes<[ADLPPort00]> {
let Latency = 5;
}
-def : InstRW<[ADLPWriteResGroup258], (instregex "^VMOVMSKP(D|S)Yrr$")>;
+def : InstRW<[ADLPWriteResGroup282], (instregex "^VMOVMSKP(D|S)Yrr$")>;
-def ADLPWriteResGroup259 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup283 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 521;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup259], (instrs VMOVNTDQmr)>;
+def : InstRW<[ADLPWriteResGroup283], (instrs VMOVNTDQmr)>;
-def ADLPWriteResGroup260 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup284 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 473;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup260], (instrs VMOVNTPDmr)>;
+def : InstRW<[ADLPWriteResGroup284], (instrs VMOVNTPDmr)>;
-def ADLPWriteResGroup261 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup285 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 494;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup261], (instrs VMOVNTPSYmr)>;
+def : InstRW<[ADLPWriteResGroup285], (instrs VMOVNTPSYmr)>;
-def ADLPWriteResGroup262 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
+def ADLPWriteResGroup286 : SchedWriteRes<[ADLPPort04_09, ADLPPort07_08]> {
let Latency = 470;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup262], (instrs VMOVNTPSmr)>;
+def : InstRW<[ADLPWriteResGroup286], (instrs VMOVNTPSmr)>;
-def ADLPWriteResGroup263 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
- let Latency = 11;
+def ADLPWriteResGroup287 : SchedWriteRes<[ADLPPort02_03_11, ADLPPort05]> {
+ let Latency = 10;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup263, ReadAfterVecYLd], (instregex "^VPACK(S|U)S(DW|WB)Yrm$")>;
-def : InstRW<[ADLPWriteResGroup263, ReadAfterVecYLd], (instrs VPCMPGTQYrm)>;
-def : InstRW<[ADLPWriteResGroup263, ReadAfterVecXLd], (instrs VPCLMULQDQYrm)>;
+def : InstRW<[ADLPWriteResGroup287, ReadAfterVecYLd], (instregex "^VPACK(S|U)S(DW|WB)Yrm$")>;
+def : InstRW<[ADLPWriteResGroup287, ReadAfterVecYLd], (instrs VPCMPGTQYrm)>;
+def : InstRW<[ADLPWriteResGroup287, ReadAfterVecXLd], (instrs VPCLMULQDQYrm)>;
-def ADLPWriteResGroup264 : SchedWriteRes<[ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup288 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_11]> {
+ let ResourceCycles = [1, 2, 1];
let Latency = 9;
- let NumMicroOps = 2;
-}
-def : InstRW<[ADLPWriteResGroup264, ReadAfterVecYLd], (instregex "^VSHUFP(D|S)Yrmi$")>;
-def : InstRW<[ADLPWriteResGroup264, ReadAfterVecYLd], (instrs VPBLENDWYrmi)>;
-
-def ADLPWriteResGroup265 : SchedWriteRes<[ADLPPort00_01, ADLPPort02_03_11]> {
- let Latency = 13;
- let NumMicroOps = 2;
+ let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup265], (instregex "^VPDP(BU|WS)SD((SY)?)rm$",
- "^VPDP(BU|WS)SD(S|Y)rm$")>;
+def : InstRW<[ADLPWriteResGroup288, ReadAfterVecYLd], (instrs VPHADDSWYrm)>;
-def ADLPWriteResGroup266 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_11]> {
+def ADLPWriteResGroup289 : SchedWriteRes<[ADLPPort00_01, ADLPPort01_05, ADLPPort02_03_11]> {
let ResourceCycles = [1, 2, 1];
let Latency = 10;
let NumMicroOps = 4;
}
-def : InstRW<[ADLPWriteResGroup266, ReadAfterVecYLd], (instregex "^VPH(ADD|SUB)SWYrm$")>;
+def : InstRW<[ADLPWriteResGroup289, ReadAfterVecYLd], (instrs VPHSUBSWYrm)>;
-def ADLPWriteResGroup267 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10]> {
+def ADLPWriteResGroup290 : SchedWriteRes<[ADLPPort01_05, ADLPPort05]> {
+ let Latency = 4;
+ let NumMicroOps = 2;
+}
+def : InstRW<[ADLPWriteResGroup290, ReadDefault, ReadInt2Fpu], (instregex "^VPINSR(B|D|Q|W)rr$")>;
+
+def ADLPWriteResGroup291 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10]> {
let ResourceCycles = [1, 2, 3, 3, 1];
let Latency = 16;
let NumMicroOps = 10;
}
-def : InstRW<[ADLPWriteResGroup267], (instrs VZEROALL)>;
+def : InstRW<[ADLPWriteResGroup291], (instrs VZEROALL)>;
+
+def ADLPWriteResGroup292 : SchedWriteRes<[]> {
+ let Latency = 0;
+ let NumMicroOps = 0;
+}
+def : InstRW<[ADLPWriteResGroup292], (instrs VZEROUPPER)>;
-def ADLPWriteResGroup268 : SchedWriteRes<[ADLPPort00_01_05_06]> {
+def ADLPWriteResGroup293 : SchedWriteRes<[ADLPPort00_01_05_06]> {
let ResourceCycles = [2];
let Latency = 2;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup268], (instrs WAIT)>;
+def : InstRW<[ADLPWriteResGroup293], (instrs WAIT)>;
-def ADLPWriteResGroup269 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup294 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [8, 6, 19, 63, 21, 15, 1, 10, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 144;
}
-def : InstRW<[ADLPWriteResGroup269], (instrs WRMSR)>;
+def : InstRW<[ADLPWriteResGroup294], (instrs WRMSR)>;
-def ADLPWriteResGroup270 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
+def ADLPWriteResGroup295 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06, ADLPPort01, ADLPPort05]> {
let ResourceCycles = [2, 1, 4, 1];
let Latency = AlderlakePModel.MaxLatency;
let NumMicroOps = 8;
}
-def : InstRW<[ADLPWriteResGroup270], (instrs WRPKRUr)>;
-
-def ADLPWriteResGroup271 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
- let ResourceCycles = [2];
- let Latency = 12;
- let NumMicroOps = 2;
-}
-def : InstRW<[ADLPWriteResGroup271, WriteRMW], (instregex "^XADD(16|32|64)rm$")>;
+def : InstRW<[ADLPWriteResGroup295], (instrs WRPKRUr)>;
-def ADLPWriteResGroup272 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
+def ADLPWriteResGroup296 : SchedWriteRes<[ADLPPort00_01_05_06_10]> {
let ResourceCycles = [2];
- let Latency = 13;
+ let Latency = 7;
let NumMicroOps = 2;
}
-def : InstRW<[ADLPWriteResGroup272, WriteRMW], (instrs XADD8rm)>;
+def : InstRW<[ADLPWriteResGroup296, WriteRMW], (instregex "^XADD(8|16|32|64)rm$")>;
-def ADLPWriteResGroup273 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+def ADLPWriteResGroup297 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
let ResourceCycles = [4, 1];
let Latency = 39;
let NumMicroOps = 5;
}
-def : InstRW<[ADLPWriteResGroup273, WriteRMW], (instregex "^XCHG(16|32)rm$")>;
+def : InstRW<[ADLPWriteResGroup297, WriteRMW], (instregex "^XCHG(16|32)rm$")>;
-def ADLPWriteResGroup274 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+def ADLPWriteResGroup298 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
let ResourceCycles = [5, 1];
let Latency = 39;
let NumMicroOps = 6;
}
-def : InstRW<[ADLPWriteResGroup274, WriteRMW], (instrs XCHG64rm)>;
+def : InstRW<[ADLPWriteResGroup298, WriteRMW], (instrs XCHG64rm)>;
-def ADLPWriteResGroup275 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
+def ADLPWriteResGroup299 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_06]> {
let ResourceCycles = [4, 1];
let Latency = 40;
let NumMicroOps = 5;
}
-def : InstRW<[ADLPWriteResGroup275, WriteRMW], (instrs XCHG8rm)>;
+def : InstRW<[ADLPWriteResGroup299, WriteRMW], (instrs XCHG8rm)>;
-def ADLPWriteResGroup276 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort01, ADLPPort05, ADLPPort06]> {
+def ADLPWriteResGroup300 : SchedWriteRes<[ADLPPort00, ADLPPort00_01_05_06, ADLPPort00_05, ADLPPort01, ADLPPort05, ADLPPort06]> {
let ResourceCycles = [2, 4, 2, 1, 2, 4];
let Latency = 17;
let NumMicroOps = 15;
}
-def : InstRW<[ADLPWriteResGroup276], (instrs XCH_F)>;
+def : InstRW<[ADLPWriteResGroup300], (instrs XCH_F)>;
-def ADLPWriteResGroup277 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01]> {
+def ADLPWriteResGroup301 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01]> {
let ResourceCycles = [7, 3, 8, 5];
let Latency = 4;
let NumMicroOps = 23;
}
-def : InstRW<[ADLPWriteResGroup277], (instrs XGETBV)>;
+def : InstRW<[ADLPWriteResGroup301], (instrs XGETBV)>;
-def ADLPWriteResGroup278 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
+def ADLPWriteResGroup302 : SchedWriteRes<[ADLPPort00_01_05_06_10, ADLPPort02_03_11]> {
let ResourceCycles = [2, 1];
let Latency = 7;
let NumMicroOps = 3;
}
-def : InstRW<[ADLPWriteResGroup278], (instrs XLAT)>;
+def : InstRW<[ADLPWriteResGroup302], (instrs XLAT)>;
-def ADLPWriteResGroup279 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort01, ADLPPort02_03, ADLPPort06]> {
+def ADLPWriteResGroup303 : SchedWriteRes<[ADLPPort00_01_05_06, ADLPPort01, ADLPPort02_03, ADLPPort06]> {
let ResourceCycles = [21, 1, 1, 8];
let Latency = 37;
let NumMicroOps = 31;
}
-def : InstRW<[ADLPWriteResGroup279], (instregex "^XRSTOR((S|64)?)$")>;
-def : InstRW<[ADLPWriteResGroup279], (instrs XRSTORS64)>;
+def : InstRW<[ADLPWriteResGroup303], (instregex "^XRSTOR((S|64)?)$")>;
+def : InstRW<[ADLPWriteResGroup303], (instrs XRSTORS64)>;
-def ADLPWriteResGroup280 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup304 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
let Latency = 42;
let NumMicroOps = 140;
}
-def : InstRW<[ADLPWriteResGroup280], (instrs XSAVE)>;
+def : InstRW<[ADLPWriteResGroup304], (instrs XSAVE)>;
-def ADLPWriteResGroup281 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup305 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
let Latency = 41;
let NumMicroOps = 140;
}
-def : InstRW<[ADLPWriteResGroup281], (instrs XSAVE64)>;
+def : InstRW<[ADLPWriteResGroup305], (instrs XSAVE64)>;
-def ADLPWriteResGroup282 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup306 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [1, 19, 36, 52, 23, 4, 2, 12, 2];
let Latency = 42;
let NumMicroOps = 151;
}
-def : InstRW<[ADLPWriteResGroup282], (instrs XSAVEC)>;
+def : InstRW<[ADLPWriteResGroup306], (instrs XSAVEC)>;
-def ADLPWriteResGroup283 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup307 : SchedWriteRes<[ADLPPort00, ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [1, 19, 36, 53, 23, 4, 2, 12, 2];
let Latency = 42;
let NumMicroOps = 152;
}
-def : InstRW<[ADLPWriteResGroup283], (instrs XSAVEC64)>;
+def : InstRW<[ADLPWriteResGroup307], (instrs XSAVEC64)>;
-def ADLPWriteResGroup284 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup308 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [25, 35, 52, 27, 4, 1, 10, 1];
let Latency = 46;
let NumMicroOps = 155;
}
-def : InstRW<[ADLPWriteResGroup284], (instrs XSAVEOPT)>;
+def : InstRW<[ADLPWriteResGroup308], (instrs XSAVEOPT)>;
-def ADLPWriteResGroup285 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup309 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [25, 35, 53, 27, 4, 1, 10, 1];
let Latency = 46;
let NumMicroOps = 156;
}
-def : InstRW<[ADLPWriteResGroup285], (instrs XSAVEOPT64)>;
+def : InstRW<[ADLPWriteResGroup309], (instrs XSAVEOPT64)>;
-def ADLPWriteResGroup286 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup310 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [23, 32, 53, 29, 30, 4, 2, 9, 2];
let Latency = 42;
let NumMicroOps = 184;
}
-def : InstRW<[ADLPWriteResGroup286], (instrs XSAVES)>;
+def : InstRW<[ADLPWriteResGroup310], (instrs XSAVES)>;
-def ADLPWriteResGroup287 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
+def ADLPWriteResGroup311 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_05, ADLPPort00_06, ADLPPort01, ADLPPort01_05, ADLPPort02_03_11, ADLPPort04_09, ADLPPort05, ADLPPort07_08]> {
let ResourceCycles = [23, 33, 53, 29, 32, 4, 2, 8, 2];
let Latency = 42;
let NumMicroOps = 186;
}
-def : InstRW<[ADLPWriteResGroup287], (instrs XSAVES64)>;
+def : InstRW<[ADLPWriteResGroup311], (instrs XSAVES64)>;
-def ADLPWriteResGroup288 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort05]> {
+def ADLPWriteResGroup312 : SchedWriteRes<[ADLPPort00_01_05, ADLPPort00_01_05_06_10, ADLPPort00_05_06, ADLPPort00_06, ADLPPort01, ADLPPort01_05_10, ADLPPort05]> {
let ResourceCycles = [4, 23, 2, 14, 8, 1, 2];
let Latency = 5;
let NumMicroOps = 54;
}
-def : InstRW<[ADLPWriteResGroup288], (instrs XSETBV)>;
+def : InstRW<[ADLPWriteResGroup312], (instrs XSETBV)>;
}
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/independent-load-stores.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/independent-load-stores.s
index dd7ac2734318..abe470551f41 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/independent-load-stores.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/independent-load-stores.s
@@ -16,18 +16,18 @@
# ALL: Iterations: 100
# ALL-NEXT: Instructions: 1000
-# NOALIAS-NEXT: Total Cycles: 1014
-# YESALIAS-NEXT: Total Cycles: 12003
+# NOALIAS-NEXT: Total Cycles: 1009
+# YESALIAS-NEXT: Total Cycles: 7003
# ALL-NEXT: Total uOps: 4000
# ALL: Dispatch Width: 6
-# NOALIAS-NEXT: uOps Per Cycle: 3.94
+# NOALIAS-NEXT: uOps Per Cycle: 3.96
# NOALIAS-NEXT: IPC: 0.99
-# YESALIAS-NEXT: uOps Per Cycle: 0.33
-# YESALIAS-NEXT: IPC: 0.08
+# YESALIAS-NEXT: uOps Per Cycle: 0.57
+# YESALIAS-NEXT: IPC: 0.14
# ALL-NEXT: Block RThroughput: 6.7
@@ -40,16 +40,16 @@
# ALL-NEXT: [6]: HasSideEffects (U)
# ALL: [1] [2] [3] [4] [5] [6] Instructions:
-# ALL-NEXT: 4 12 0.50 * * addq $44, 64(%r14)
-# ALL-NEXT: 4 12 0.50 * * addq $44, 128(%r14)
-# ALL-NEXT: 4 12 0.50 * * addq $44, 192(%r14)
-# ALL-NEXT: 4 12 0.50 * * addq $44, 256(%r14)
-# ALL-NEXT: 4 12 0.50 * * addq $44, 320(%r14)
-# ALL-NEXT: 4 12 0.50 * * addq $44, 384(%r14)
-# ALL-NEXT: 4 12 0.50 * * addq $44, 448(%r14)
-# ALL-NEXT: 4 12 0.50 * * addq $44, 512(%r14)
-# ALL-NEXT: 4 12 0.50 * * addq $44, 576(%r14)
-# ALL-NEXT: 4 12 0.50 * * addq $44, 640(%r14)
+# ALL-NEXT: 4 7 0.50 * * addq $44, 64(%r14)
+# ALL-NEXT: 4 7 0.50 * * addq $44, 128(%r14)
+# ALL-NEXT: 4 7 0.50 * * addq $44, 192(%r14)
+# ALL-NEXT: 4 7 0.50 * * addq $44, 256(%r14)
+# ALL-NEXT: 4 7 0.50 * * addq $44, 320(%r14)
+# ALL-NEXT: 4 7 0.50 * * addq $44, 384(%r14)
+# ALL-NEXT: 4 7 0.50 * * addq $44, 448(%r14)
+# ALL-NEXT: 4 7 0.50 * * addq $44, 512(%r14)
+# ALL-NEXT: 4 7 0.50 * * addq $44, 576(%r14)
+# ALL-NEXT: 4 7 0.50 * * addq $44, 640(%r14)
# ALL: Resources:
# ALL-NEXT: [0] - ADLPPort00
@@ -85,30 +85,33 @@
# ALL: Timeline view:
-# NOALIAS-NEXT: 0123456789
-# NOALIAS-NEXT: Index 0123456789 0123
+# NOALIAS-NEXT: 012345678
+# NOALIAS-NEXT: Index 0123456789
-# YESALIAS-NEXT: 0123456789 0123456789 0123456789 01234
+# YESALIAS-NEXT: 0123456789 0123456789 0123456789 012
# YESALIAS-NEXT: Index 0123456789 0123456789 0123456789 0123456789
-# NOALIAS: [0,0] DeeeeeeeeeeeeER. . . addq $44, 64(%r14)
-# NOALIAS-NEXT: [0,1] .DeeeeeeeeeeeeER . . addq $44, 128(%r14)
-# NOALIAS-NEXT: [0,2] . DeeeeeeeeeeeeER . . addq $44, 192(%r14)
-# NOALIAS-NEXT: [0,3] . DeeeeeeeeeeeeER . . addq $44, 256(%r14)
-# NOALIAS-NEXT: [0,4] . DeeeeeeeeeeeeER . . addq $44, 320(%r14)
-# NOALIAS-NEXT: [0,5] . DeeeeeeeeeeeeER. . addq $44, 384(%r14)
-# NOALIAS-NEXT: [0,6] . .DeeeeeeeeeeeeER . addq $44, 448(%r14)
-# NOALIAS-NEXT: [0,7] . . DeeeeeeeeeeeeER . addq $44, 512(%r14)
-# NOALIAS-NEXT: [0,8] . . DeeeeeeeeeeeeER. addq $44, 576(%r14)
-# NOALIAS-NEXT: [0,9] . . DeeeeeeeeeeeeER addq $44, 640(%r14)
-
-# YESALIAS: [0,0] DeeeeeeeeeeeeER. . . . . . . . . . . . . addq $44, 64(%r14)
-# YESALIAS-NEXT: [0,1] .D===========eeeeeeeeeeeeER . . . . . . . . . . addq $44, 128(%r14)
-# YESALIAS-NEXT: [0,2] . D======================eeeeeeeeeeeeER . . . . . . . . addq $44, 192(%r14)
-# YESALIAS-NEXT: [0,3] . D=================================eeeeeeeeeeeeER . . . . . addq $44, 256(%r14)
-# YESALIAS-NEXT: [0,4] . D============================================eeeeeeeeeeeeER . . . addq $44, 320(%r14)
-# YESALIAS-NEXT: [0,5] . D=======================================================eeeeeeeeeeeeER addq $44, 384(%r14)
-# YESALIAS-NEXT: Truncated display due to cycle limit
+# NOALIAS: [0,0] DeeeeeeeER. . . addq $44, 64(%r14)
+# NOALIAS-NEXT: [0,1] .DeeeeeeeER . . addq $44, 128(%r14)
+# NOALIAS-NEXT: [0,2] . DeeeeeeeER . . addq $44, 192(%r14)
+# NOALIAS-NEXT: [0,3] . DeeeeeeeER . . addq $44, 256(%r14)
+# NOALIAS-NEXT: [0,4] . DeeeeeeeER . . addq $44, 320(%r14)
+# NOALIAS-NEXT: [0,5] . DeeeeeeeER. . addq $44, 384(%r14)
+# NOALIAS-NEXT: [0,6] . .DeeeeeeeER . addq $44, 448(%r14)
+# NOALIAS-NEXT: [0,7] . . DeeeeeeeER . addq $44, 512(%r14)
+# NOALIAS-NEXT: [0,8] . . DeeeeeeeER. addq $44, 576(%r14)
+# NOALIAS-NEXT: [0,9] . . DeeeeeeeER addq $44, 640(%r14)
+
+# YESALIAS: [0,0] DeeeeeeeER. . . . . . . . . . . . . . addq $44, 64(%r14)
+# YESALIAS-NEXT: [0,1] .D======eeeeeeeER . . . . . . . . . . . . addq $44, 128(%r14)
+# YESALIAS-NEXT: [0,2] . D============eeeeeeeER . . . . . . . . . . . addq $44, 192(%r14)
+# YESALIAS-NEXT: [0,3] . D==================eeeeeeeER . . . . . . . . . addq $44, 256(%r14)
+# YESALIAS-NEXT: [0,4] . D========================eeeeeeeER . . . . . . . . addq $44, 320(%r14)
+# YESALIAS-NEXT: [0,5] . D==============================eeeeeeeER. . . . . . . addq $44, 384(%r14)
+# YESALIAS-NEXT: [0,6] . .D====================================eeeeeeeER . . . . . addq $44, 448(%r14)
+# YESALIAS-NEXT: [0,7] . . D==========================================eeeeeeeER . . . . addq $44, 512(%r14)
+# YESALIAS-NEXT: [0,8] . . D================================================eeeeeeeER . . addq $44, 576(%r14)
+# YESALIAS-NEXT: [0,9] . . D======================================================eeeeeeeER addq $44, 640(%r14)
# ALL: Average Wait times (based on the timeline view):
# ALL-NEXT: [0]: Executions
@@ -130,13 +133,13 @@
# NOALIAS-NEXT: 9. 1 1.0 1.0 0.0 addq $44, 640(%r14)
# NOALIAS-NEXT: 1 1.0 1.0 0.0 <total>
-# YESALIAS-NEXT: 1. 1 12.0 0.0 0.0 addq $44, 128(%r14)
-# YESALIAS-NEXT: 2. 1 23.0 0.0 0.0 addq $44, 192(%r14)
-# YESALIAS-NEXT: 3. 1 34.0 0.0 0.0 addq $44, 256(%r14)
-# YESALIAS-NEXT: 4. 1 45.0 0.0 0.0 addq $44, 320(%r14)
-# YESALIAS-NEXT: 5. 1 56.0 0.0 0.0 addq $44, 384(%r14)
-# YESALIAS-NEXT: 6. 1 67.0 0.0 0.0 addq $44, 448(%r14)
-# YESALIAS-NEXT: 7. 1 78.0 0.0 0.0 addq $44, 512(%r14)
-# YESALIAS-NEXT: 8. 1 89.0 0.0 0.0 addq $44, 576(%r14)
-# YESALIAS-NEXT: 9. 1 100.0 0.0 0.0 addq $44, 640(%r14)
-# YESALIAS-NEXT: 1 50.5 0.1 0.0 <total>
+# YESALIAS-NEXT: 1. 1 7.0 0.0 0.0 addq $44, 128(%r14)
+# YESALIAS-NEXT: 2. 1 13.0 0.0 0.0 addq $44, 192(%r14)
+# YESALIAS-NEXT: 3. 1 19.0 0.0 0.0 addq $44, 256(%r14)
+# YESALIAS-NEXT: 4. 1 25.0 0.0 0.0 addq $44, 320(%r14)
+# YESALIAS-NEXT: 5. 1 31.0 0.0 0.0 addq $44, 384(%r14)
+# YESALIAS-NEXT: 6. 1 37.0 0.0 0.0 addq $44, 448(%r14)
+# YESALIAS-NEXT: 7. 1 43.0 0.0 0.0 addq $44, 512(%r14)
+# YESALIAS-NEXT: 8. 1 49.0 0.0 0.0 addq $44, 576(%r14)
+# YESALIAS-NEXT: 9. 1 55.0 0.0 0.0 addq $44, 640(%r14)
+# YESALIAS-NEXT: 1 28.0 0.1 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-aes.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-aes.s
index 9384488f0678..670c802c8e93 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-aes.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-aes.s
@@ -28,16 +28,16 @@ aeskeygenassist $22, (%rax), %xmm2
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 5 0.50 aesdec %xmm0, %xmm2
-# CHECK-NEXT: 2 12 0.50 * aesdec (%rax), %xmm2
-# CHECK-NEXT: 1 5 0.50 aesdeclast %xmm0, %xmm2
-# CHECK-NEXT: 2 12 0.50 * aesdeclast (%rax), %xmm2
-# CHECK-NEXT: 1 5 0.50 aesenc %xmm0, %xmm2
-# CHECK-NEXT: 2 12 0.50 * aesenc (%rax), %xmm2
-# CHECK-NEXT: 1 5 0.50 aesenclast %xmm0, %xmm2
-# CHECK-NEXT: 2 12 0.50 * aesenclast (%rax), %xmm2
-# CHECK-NEXT: 2 8 1.00 aesimc %xmm0, %xmm2
-# CHECK-NEXT: 3 15 1.00 * aesimc (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 aesdec %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * aesdec (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 aesdeclast %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * aesdeclast (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 aesenc %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * aesenc (%rax), %xmm2
+# CHECK-NEXT: 1 3 0.50 aesenclast %xmm0, %xmm2
+# CHECK-NEXT: 2 11 0.50 * aesenclast (%rax), %xmm2
+# CHECK-NEXT: 2 6 1.00 aesimc %xmm0, %xmm2
+# CHECK-NEXT: 3 14 1.00 * aesimc (%rax), %xmm2
# CHECK-NEXT: 14 7 4.00 aeskeygenassist $22, %xmm0, %xmm2
# CHECK-NEXT: 14 12 4.00 * aeskeygenassist $22, (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx1.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx1.s
index dc8ad8e46a77..fb4e19494adf 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx1.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx1.s
@@ -1030,145 +1030,145 @@ vzeroupper
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 3 0.50 vaddpd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 10 0.50 * vaddpd (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 3 0.50 vaddpd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 11 0.50 * vaddpd (%rax), %ymm1, %ymm2
-# CHECK-NEXT: 1 3 0.50 vaddps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 10 0.50 * vaddps (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 3 0.50 vaddps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 11 0.50 * vaddps (%rax), %ymm1, %ymm2
-# CHECK-NEXT: 1 3 0.50 vaddsd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 10 0.50 * vaddsd (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 3 0.50 vaddss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 10 0.50 * vaddss (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 3 0.50 vaddsubpd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 10 0.50 * vaddsubpd (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 3 0.50 vaddsubpd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 11 0.50 * vaddsubpd (%rax), %ymm1, %ymm2
-# CHECK-NEXT: 1 3 0.50 vaddsubps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 10 0.50 * vaddsubps (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 3 0.50 vaddsubps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 11 0.50 * vaddsubps (%rax), %ymm1, %ymm2
-# CHECK-NEXT: 1 5 0.50 vaesdec %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 12 0.50 * vaesdec (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 5 0.50 vaesdeclast %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 12 0.50 * vaesdeclast (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 5 0.50 vaesenc %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 12 0.50 * vaesenc (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 5 0.50 vaesenclast %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 12 0.50 * vaesenclast (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 2 8 1.00 vaesimc %xmm0, %xmm2
-# CHECK-NEXT: 3 15 1.00 * vaesimc (%rax), %xmm2
+# CHECK-NEXT: 1 2 0.50 vaddpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 9 0.50 * vaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vaddpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 10 0.50 * vaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 2 0.50 vaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 9 0.50 * vaddps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 10 0.50 * vaddps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 2 0.50 vaddsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 9 0.50 * vaddsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vaddss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 9 0.50 * vaddss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vaddsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 9 0.50 * vaddsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vaddsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 10 0.50 * vaddsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 2 0.50 vaddsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 9 0.50 * vaddsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vaddsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 10 0.50 * vaddsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vaesdec %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vaesdec (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaesdeclast %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vaesdeclast (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaesenc %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vaesenc (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vaesenclast %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vaesenclast (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 6 1.00 vaesimc %xmm0, %xmm2
+# CHECK-NEXT: 3 14 1.00 * vaesimc (%rax), %xmm2
# CHECK-NEXT: 14 7 4.00 vaeskeygenassist $22, %xmm0, %xmm2
# CHECK-NEXT: 14 12 4.00 * vaeskeygenassist $22, (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 vandnpd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vandnpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vandnpd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vandnpd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vandnpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vandnpd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.33 vandnps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vandnps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vandnps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vandnps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vandnps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vandnps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.33 vandpd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vandpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vandpd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vandpd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vandpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vandpd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.33 vandps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vandps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vandps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vandps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vandps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vandps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.33 vblendpd $11, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vblendpd $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vblendpd $11, (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vblendpd $11, %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vblendpd $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vblendpd $11, (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.33 vblendps $11, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vblendps $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vblendps $11, (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vblendps $11, %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vblendps $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vblendps $11, (%rax), %ymm1, %ymm2
# CHECK-NEXT: 3 3 1.00 vblendvpd %xmm3, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 4 9 1.00 * vblendvpd %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 8 1.00 * vblendvpd %xmm3, (%rax), %xmm1, %xmm2
# CHECK-NEXT: 3 3 1.00 vblendvpd %ymm3, %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 4 10 1.00 * vblendvpd %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 9 1.00 * vblendvpd %ymm3, (%rax), %ymm1, %ymm2
# CHECK-NEXT: 3 3 1.00 vblendvps %xmm3, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 4 9 1.00 * vblendvps %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 8 1.00 * vblendvps %xmm3, (%rax), %xmm1, %xmm2
# CHECK-NEXT: 3 3 1.00 vblendvps %ymm3, %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 4 10 1.00 * vblendvps %ymm3, (%rax), %ymm1, %ymm2
-# CHECK-NEXT: 1 8 0.33 * vbroadcastf128 (%rax), %ymm2
-# CHECK-NEXT: 1 8 0.33 * vbroadcastsd (%rax), %ymm2
-# CHECK-NEXT: 1 7 0.33 * vbroadcastss (%rax), %xmm2
-# CHECK-NEXT: 1 8 0.33 * vbroadcastss (%rax), %ymm2
+# CHECK-NEXT: 4 9 1.00 * vblendvps %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 7 0.33 * vbroadcastf128 (%rax), %ymm2
+# CHECK-NEXT: 1 7 0.33 * vbroadcastsd (%rax), %ymm2
+# CHECK-NEXT: 1 6 0.33 * vbroadcastss (%rax), %xmm2
+# CHECK-NEXT: 1 7 0.33 * vbroadcastss (%rax), %ymm2
# CHECK-NEXT: 1 4 0.50 vcmpeqpd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vcmpeqpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vcmpeqpd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vcmpeqpd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vcmpeqpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vcmpeqpd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vcmpeqps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vcmpeqps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vcmpeqps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vcmpeqps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vcmpeqps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vcmpeqps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vcmpeqsd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vcmpeqsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vcmpeqsd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vcmpeqss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vcmpeqss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vcmpeqss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 3 1.00 vcomisd %xmm0, %xmm1
-# CHECK-NEXT: 2 8 1.00 * vcomisd (%rax), %xmm1
+# CHECK-NEXT: 2 9 1.00 * vcomisd (%rax), %xmm1
# CHECK-NEXT: 1 3 1.00 vcomiss %xmm0, %xmm1
-# CHECK-NEXT: 2 8 1.00 * vcomiss (%rax), %xmm1
+# CHECK-NEXT: 2 9 1.00 * vcomiss (%rax), %xmm1
# CHECK-NEXT: 2 5 1.00 vcvtdq2pd %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vcvtdq2pd (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * vcvtdq2pd (%rax), %xmm2
# CHECK-NEXT: 2 7 1.00 vcvtdq2pd %xmm0, %ymm2
# CHECK-NEXT: 2 12 0.50 * vcvtdq2pd (%rax), %ymm2
# CHECK-NEXT: 1 4 0.50 vcvtdq2ps %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vcvtdq2ps (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * vcvtdq2ps (%rax), %xmm2
# CHECK-NEXT: 1 4 0.50 vcvtdq2ps %ymm0, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vcvtdq2ps (%rax), %ymm2
+# CHECK-NEXT: 2 11 0.50 * vcvtdq2ps (%rax), %ymm2
# CHECK-NEXT: 2 5 1.00 vcvtpd2dq %xmm0, %xmm2
-# CHECK-NEXT: 3 12 1.00 * vcvtpd2dqx (%rax), %xmm2
+# CHECK-NEXT: 3 11 1.00 * vcvtpd2dqx (%rax), %xmm2
# CHECK-NEXT: 2 7 1.00 vcvtpd2dq %ymm0, %xmm2
-# CHECK-NEXT: 3 15 1.00 * vcvtpd2dqy (%rax), %xmm2
+# CHECK-NEXT: 3 14 1.00 * vcvtpd2dqy (%rax), %xmm2
# CHECK-NEXT: 2 5 1.00 vcvtpd2ps %xmm0, %xmm2
-# CHECK-NEXT: 3 12 1.00 * vcvtpd2psx (%rax), %xmm2
+# CHECK-NEXT: 3 11 1.00 * vcvtpd2psx (%rax), %xmm2
# CHECK-NEXT: 2 7 1.00 vcvtpd2ps %ymm0, %xmm2
-# CHECK-NEXT: 3 15 1.00 * vcvtpd2psy (%rax), %xmm2
+# CHECK-NEXT: 3 14 1.00 * vcvtpd2psy (%rax), %xmm2
# CHECK-NEXT: 1 4 0.50 vcvtps2dq %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vcvtps2dq (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * vcvtps2dq (%rax), %xmm2
# CHECK-NEXT: 1 4 0.50 vcvtps2dq %ymm0, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vcvtps2dq (%rax), %ymm2
+# CHECK-NEXT: 2 11 0.50 * vcvtps2dq (%rax), %ymm2
# CHECK-NEXT: 2 5 1.00 vcvtps2pd %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vcvtps2pd (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * vcvtps2pd (%rax), %xmm2
# CHECK-NEXT: 2 7 1.00 vcvtps2pd %xmm0, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vcvtps2pd (%rax), %ymm2
+# CHECK-NEXT: 2 11 0.50 * vcvtps2pd (%rax), %ymm2
# CHECK-NEXT: 2 7 1.00 vcvtsd2si %xmm0, %ecx
# CHECK-NEXT: 2 7 1.00 vcvtsd2si %xmm0, %rcx
-# CHECK-NEXT: 3 26 1.00 * vcvtsd2si (%rax), %ecx
+# CHECK-NEXT: 3 12 1.00 * vcvtsd2si (%rax), %ecx
# CHECK-NEXT: 3 12 1.00 * vcvtsd2si (%rax), %rcx
# CHECK-NEXT: 2 5 1.00 vcvtsd2ss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 3 12 1.00 * vcvtsd2ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 11 1.00 * vcvtsd2ss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 2 7 1.00 vcvtsi2sd %ecx, %xmm0, %xmm2
# CHECK-NEXT: 2 7 1.00 vcvtsi2sd %rcx, %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vcvtsi2sdl (%rax), %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vcvtsi2sdq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vcvtsi2sdl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vcvtsi2sdq (%rax), %xmm0, %xmm2
# CHECK-NEXT: 2 7 1.00 vcvtsi2ss %ecx, %xmm0, %xmm2
# CHECK-NEXT: 3 8 2.00 vcvtsi2ss %rcx, %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vcvtsi2ssl (%rax), %xmm0, %xmm2
-# CHECK-NEXT: 3 12 1.00 * vcvtsi2ssq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vcvtsi2ssl (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 3 11 1.00 * vcvtsi2ssq (%rax), %xmm0, %xmm2
# CHECK-NEXT: 2 5 1.00 vcvtss2sd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vcvtss2sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vcvtss2sd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 2 7 1.00 vcvtss2si %xmm0, %ecx
# CHECK-NEXT: 3 8 1.00 vcvtss2si %xmm0, %rcx
# CHECK-NEXT: 3 12 1.00 * vcvtss2si (%rax), %ecx
# CHECK-NEXT: 3 12 1.00 * vcvtss2si (%rax), %rcx
# CHECK-NEXT: 2 5 1.00 vcvttpd2dq %xmm0, %xmm2
-# CHECK-NEXT: 3 12 1.00 * vcvttpd2dqx (%rax), %xmm2
+# CHECK-NEXT: 3 11 1.00 * vcvttpd2dqx (%rax), %xmm2
# CHECK-NEXT: 2 7 1.00 vcvttpd2dq %ymm0, %xmm2
-# CHECK-NEXT: 3 15 1.00 * vcvttpd2dqy (%rax), %xmm2
+# CHECK-NEXT: 3 14 1.00 * vcvttpd2dqy (%rax), %xmm2
# CHECK-NEXT: 1 4 0.50 vcvttps2dq %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vcvttps2dq (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * vcvttps2dq (%rax), %xmm2
# CHECK-NEXT: 1 4 0.50 vcvttps2dq %ymm0, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vcvttps2dq (%rax), %ymm2
+# CHECK-NEXT: 2 11 0.50 * vcvttps2dq (%rax), %ymm2
# CHECK-NEXT: 2 7 1.00 vcvttsd2si %xmm0, %ecx
# CHECK-NEXT: 2 7 1.00 vcvttsd2si %xmm0, %rcx
-# CHECK-NEXT: 3 26 1.00 * vcvttsd2si (%rax), %ecx
+# CHECK-NEXT: 3 12 1.00 * vcvttsd2si (%rax), %ecx
# CHECK-NEXT: 3 12 1.00 * vcvttsd2si (%rax), %rcx
# CHECK-NEXT: 2 7 1.00 vcvttss2si %xmm0, %ecx
# CHECK-NEXT: 3 8 1.00 vcvttss2si %xmm0, %rcx
@@ -1179,35 +1179,35 @@ vzeroupper
# CHECK-NEXT: 1 14 1.00 vdivpd %ymm0, %ymm1, %ymm2
# CHECK-NEXT: 2 21 1.00 * vdivpd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 11 1.00 vdivps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 18 1.00 * vdivps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 17 1.00 * vdivps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 11 1.00 vdivps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 19 1.00 * vdivps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 18 1.00 * vdivps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 14 1.00 vdivsd %xmm0, %xmm1, %xmm2
# CHECK-NEXT: 2 20 1.00 * vdivsd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 11 1.00 vdivss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 18 1.00 * vdivss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 17 1.00 * vdivss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 3 9 1.00 vdppd $22, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 4 16 1.00 * vdppd $22, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 15 1.00 * vdppd $22, (%rax), %xmm1, %xmm2
# CHECK-NEXT: 6 14 1.67 vdpps $22, %xmm0, %xmm1, %xmm2
# CHECK-NEXT: 7 21 1.67 * vdpps $22, (%rax), %xmm1, %xmm2
# CHECK-NEXT: 6 14 1.67 vdpps $22, %ymm0, %ymm1, %ymm2
# CHECK-NEXT: 7 22 1.67 * vdpps $22, (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 3 1.00 vextractf128 $1, %ymm0, %xmm2
-# CHECK-NEXT: 2 12 0.50 * vextractf128 $1, %ymm0, (%rax)
+# CHECK-NEXT: 2 1 0.50 * vextractf128 $1, %ymm0, (%rax)
# CHECK-NEXT: 2 4 1.00 vextractps $1, %xmm0, %ecx
-# CHECK-NEXT: 3 12 1.00 * vextractps $1, %xmm0, (%rax)
+# CHECK-NEXT: 3 2 1.00 * vextractps $1, %xmm0, (%rax)
# CHECK-NEXT: 3 5 2.00 vhaddpd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 4 12 2.00 * vhaddpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 11 2.00 * vhaddpd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 3 5 2.00 vhaddpd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 4 13 2.00 * vhaddpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 12 2.00 * vhaddpd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 3 5 2.00 vhaddps %xmm0, %xmm1, %xmm2
# CHECK-NEXT: 4 12 2.00 * vhaddps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 3 5 2.00 vhaddps %ymm0, %ymm1, %ymm2
# CHECK-NEXT: 4 13 2.00 * vhaddps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 3 5 2.00 vhsubpd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 4 12 2.00 * vhsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 11 2.00 * vhsubpd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 3 5 2.00 vhsubpd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 4 13 2.00 * vhsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 12 2.00 * vhsubpd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 3 5 2.00 vhsubps %xmm0, %xmm1, %xmm2
# CHECK-NEXT: 4 12 2.00 * vhsubps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 3 5 2.00 vhsubps %ymm0, %ymm1, %ymm2
@@ -1215,85 +1215,85 @@ vzeroupper
# CHECK-NEXT: 1 3 1.00 vinsertf128 $1, %xmm0, %ymm1, %ymm2
# CHECK-NEXT: 2 9 0.33 * vinsertf128 $1, (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 1.00 vinsertps $1, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 1.00 * vinsertps $1, (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 7 0.33 * vlddqu (%rax), %xmm2
-# CHECK-NEXT: 1 8 0.33 * vlddqu (%rax), %ymm2
+# CHECK-NEXT: 2 7 1.00 * vinsertps $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 6 0.33 * vlddqu (%rax), %xmm2
+# CHECK-NEXT: 1 7 0.33 * vlddqu (%rax), %ymm2
# CHECK-NEXT: 3 7 1.00 * * U vldmxcsr (%rax)
# CHECK-NEXT: 2 1 1.00 * * U vmaskmovdqu %xmm0, %xmm1
-# CHECK-NEXT: 2 8 0.33 * vmaskmovpd (%rax), %xmm0, %xmm2
-# CHECK-NEXT: 2 9 0.33 * vmaskmovpd (%rax), %ymm0, %ymm2
-# CHECK-NEXT: 3 14 1.00 * * vmaskmovpd %xmm0, %xmm1, (%rax)
-# CHECK-NEXT: 3 14 1.00 * * vmaskmovpd %ymm0, %ymm1, (%rax)
-# CHECK-NEXT: 2 8 0.33 * vmaskmovps (%rax), %xmm0, %xmm2
-# CHECK-NEXT: 2 9 0.33 * vmaskmovps (%rax), %ymm0, %ymm2
-# CHECK-NEXT: 3 14 1.00 * * vmaskmovps %xmm0, %xmm1, (%rax)
-# CHECK-NEXT: 3 14 1.00 * * vmaskmovps %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 2 7 0.33 * vmaskmovpd (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vmaskmovpd (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 3 3 1.00 * * vmaskmovpd %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 3 3 1.00 * * vmaskmovpd %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 2 7 0.33 * vmaskmovps (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vmaskmovps (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 3 3 1.00 * * vmaskmovps %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 3 3 1.00 * * vmaskmovps %ymm0, %ymm1, (%rax)
# CHECK-NEXT: 1 4 0.50 vmaxpd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vmaxpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vmaxpd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vmaxpd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vmaxpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vmaxpd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vmaxps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vmaxps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vmaxps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vmaxps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vmaxps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vmaxps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vmaxsd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vmaxsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vmaxsd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vmaxss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vmaxss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vmaxss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vminpd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vminpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vminpd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vminpd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vminpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vminpd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vminps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vminps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vminps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vminps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vminps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vminps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vminsd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vminsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vminsd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vminss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vminss (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 0 1 0.00 vmovapd %xmm0, %xmm2
-# CHECK-NEXT: 2 12 0.50 * vmovapd %xmm0, (%rax)
-# CHECK-NEXT: 1 7 0.33 * vmovapd (%rax), %xmm2
-# CHECK-NEXT: 0 1 0.00 vmovapd %ymm0, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vmovapd %ymm0, (%rax)
-# CHECK-NEXT: 1 8 0.33 * vmovapd (%rax), %ymm2
-# CHECK-NEXT: 0 1 0.00 vmovaps %xmm0, %xmm2
-# CHECK-NEXT: 2 12 0.50 * vmovaps %xmm0, (%rax)
-# CHECK-NEXT: 1 7 0.33 * vmovaps (%rax), %xmm2
-# CHECK-NEXT: 0 1 0.00 vmovaps %ymm0, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vmovaps %ymm0, (%rax)
-# CHECK-NEXT: 1 8 0.33 * vmovaps (%rax), %ymm2
-# CHECK-NEXT: 1 3 1.00 vmovd %eax, %xmm2
-# CHECK-NEXT: 1 7 0.33 * vmovd (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * vminss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 0 0.33 vmovapd %xmm0, %xmm2
+# CHECK-NEXT: 2 1 0.50 * vmovapd %xmm0, (%rax)
+# CHECK-NEXT: 1 6 0.33 * vmovapd (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.33 vmovapd %ymm0, %ymm2
+# CHECK-NEXT: 2 1 0.50 * vmovapd %ymm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * vmovapd (%rax), %ymm2
+# CHECK-NEXT: 1 0 0.33 vmovaps %xmm0, %xmm2
+# CHECK-NEXT: 2 1 0.50 * vmovaps %xmm0, (%rax)
+# CHECK-NEXT: 1 6 0.33 * vmovaps (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.33 vmovaps %ymm0, %ymm2
+# CHECK-NEXT: 2 1 0.50 * vmovaps %ymm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * vmovaps (%rax), %ymm2
+# CHECK-NEXT: 1 1 1.00 vmovd %eax, %xmm2
+# CHECK-NEXT: 1 6 0.33 * vmovd (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 vmovd %xmm0, %ecx
-# CHECK-NEXT: 2 12 0.50 * vmovd %xmm0, (%rax)
+# CHECK-NEXT: 2 1 0.50 * vmovd %xmm0, (%rax)
# CHECK-NEXT: 1 1 1.00 vmovddup %xmm0, %xmm2
# CHECK-NEXT: 1 7 0.33 * vmovddup (%rax), %xmm2
# CHECK-NEXT: 1 1 1.00 vmovddup %ymm0, %ymm2
-# CHECK-NEXT: 1 8 0.33 * vmovddup (%rax), %ymm2
-# CHECK-NEXT: 0 1 0.00 vmovdqa %xmm0, %xmm2
-# CHECK-NEXT: 2 12 0.50 * vmovdqa %xmm0, (%rax)
-# CHECK-NEXT: 1 7 0.33 * vmovdqa (%rax), %xmm2
-# CHECK-NEXT: 0 1 0.00 vmovdqa %ymm0, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vmovdqa %ymm0, (%rax)
-# CHECK-NEXT: 1 8 0.33 * vmovdqa (%rax), %ymm2
-# CHECK-NEXT: 0 1 0.00 vmovdqu %xmm0, %xmm2
-# CHECK-NEXT: 2 12 0.50 * vmovdqu %xmm0, (%rax)
-# CHECK-NEXT: 1 7 0.33 * vmovdqu (%rax), %xmm2
-# CHECK-NEXT: 0 1 0.00 vmovdqu %ymm0, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vmovdqu %ymm0, (%rax)
-# CHECK-NEXT: 1 8 0.33 * vmovdqu (%rax), %ymm2
+# CHECK-NEXT: 1 7 0.33 * vmovddup (%rax), %ymm2
+# CHECK-NEXT: 1 0 0.33 vmovdqa %xmm0, %xmm2
+# CHECK-NEXT: 2 1 0.50 * vmovdqa %xmm0, (%rax)
+# CHECK-NEXT: 1 6 0.33 * vmovdqa (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.33 vmovdqa %ymm0, %ymm2
+# CHECK-NEXT: 2 1 0.50 * vmovdqa %ymm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * vmovdqa (%rax), %ymm2
+# CHECK-NEXT: 1 0 0.33 vmovdqu %xmm0, %xmm2
+# CHECK-NEXT: 2 1 0.50 * vmovdqu %xmm0, (%rax)
+# CHECK-NEXT: 1 6 0.33 * vmovdqu (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.33 vmovdqu %ymm0, %ymm2
+# CHECK-NEXT: 2 1 0.50 * vmovdqu %ymm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * vmovdqu (%rax), %ymm2
# CHECK-NEXT: 1 1 1.00 vmovhlps %xmm0, %xmm1, %xmm2
# CHECK-NEXT: 1 1 1.00 vmovlhps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 12 0.50 * vmovhpd %xmm0, (%rax)
-# CHECK-NEXT: 2 8 1.00 * vmovhpd (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 2 12 0.50 * vmovhps %xmm0, (%rax)
-# CHECK-NEXT: 2 8 1.00 * vmovhps (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 2 12 0.50 * vmovlpd %xmm0, (%rax)
-# CHECK-NEXT: 2 8 0.50 * vmovlpd (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 2 12 0.50 * vmovlps %xmm0, (%rax)
-# CHECK-NEXT: 2 8 0.50 * vmovlps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 1 0.50 * vmovhpd %xmm0, (%rax)
+# CHECK-NEXT: 2 7 1.00 * vmovhpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 1 0.50 * vmovhps %xmm0, (%rax)
+# CHECK-NEXT: 2 7 1.00 * vmovhps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 1 0.50 * vmovlpd %xmm0, (%rax)
+# CHECK-NEXT: 2 7 0.50 * vmovlpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 1 0.50 * vmovlps %xmm0, (%rax)
+# CHECK-NEXT: 2 7 0.50 * vmovlps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 3 1.00 vmovmskpd %xmm0, %ecx
# CHECK-NEXT: 1 5 1.00 vmovmskpd %ymm0, %ecx
# CHECK-NEXT: 1 3 1.00 vmovmskps %xmm0, %ecx
@@ -1307,382 +1307,382 @@ vzeroupper
# CHECK-NEXT: 2 470 0.50 * vmovntps %xmm0, (%rax)
# CHECK-NEXT: 2 494 0.50 * vmovntps %ymm0, (%rax)
# CHECK-NEXT: 1 1 0.33 vmovq %xmm0, %xmm2
-# CHECK-NEXT: 1 3 1.00 vmovq %rax, %xmm2
-# CHECK-NEXT: 1 7 0.33 * vmovq (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 vmovq %rax, %xmm2
+# CHECK-NEXT: 1 6 0.33 * vmovq (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 vmovq %xmm0, %rcx
-# CHECK-NEXT: 2 12 0.50 * vmovq %xmm0, (%rax)
+# CHECK-NEXT: 2 1 0.50 * vmovq %xmm0, (%rax)
# CHECK-NEXT: 1 1 0.33 vmovsd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 12 0.50 * vmovsd %xmm0, (%rax)
-# CHECK-NEXT: 1 7 0.33 * vmovsd (%rax), %xmm2
+# CHECK-NEXT: 2 1 0.50 * vmovsd %xmm0, (%rax)
+# CHECK-NEXT: 1 6 0.33 * vmovsd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 vmovshdup %xmm0, %xmm2
# CHECK-NEXT: 1 7 0.33 * vmovshdup (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 vmovshdup %ymm0, %ymm2
-# CHECK-NEXT: 1 8 0.33 * vmovshdup (%rax), %ymm2
+# CHECK-NEXT: 1 7 0.33 * vmovshdup (%rax), %ymm2
# CHECK-NEXT: 1 1 0.50 vmovsldup %xmm0, %xmm2
# CHECK-NEXT: 1 7 0.33 * vmovsldup (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 vmovsldup %ymm0, %ymm2
-# CHECK-NEXT: 1 8 0.33 * vmovsldup (%rax), %ymm2
+# CHECK-NEXT: 1 7 0.33 * vmovsldup (%rax), %ymm2
# CHECK-NEXT: 1 1 0.33 vmovss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 12 0.50 * vmovss %xmm0, (%rax)
-# CHECK-NEXT: 1 7 0.33 * vmovss (%rax), %xmm2
-# CHECK-NEXT: 0 1 0.00 vmovupd %xmm0, %xmm2
-# CHECK-NEXT: 2 12 0.50 * vmovupd %xmm0, (%rax)
-# CHECK-NEXT: 1 7 0.33 * vmovupd (%rax), %xmm2
-# CHECK-NEXT: 0 1 0.00 vmovupd %ymm0, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vmovupd %ymm0, (%rax)
-# CHECK-NEXT: 1 8 0.33 * vmovupd (%rax), %ymm2
-# CHECK-NEXT: 0 1 0.00 vmovups %xmm0, %xmm2
-# CHECK-NEXT: 2 12 0.50 * vmovups %xmm0, (%rax)
-# CHECK-NEXT: 1 7 0.33 * vmovups (%rax), %xmm2
-# CHECK-NEXT: 0 1 0.00 vmovups %ymm0, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vmovups %ymm0, (%rax)
-# CHECK-NEXT: 1 8 0.33 * vmovups (%rax), %ymm2
+# CHECK-NEXT: 2 1 0.50 * vmovss %xmm0, (%rax)
+# CHECK-NEXT: 1 6 0.33 * vmovss (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.33 vmovupd %xmm0, %xmm2
+# CHECK-NEXT: 2 1 0.50 * vmovupd %xmm0, (%rax)
+# CHECK-NEXT: 1 6 0.33 * vmovupd (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.33 vmovupd %ymm0, %ymm2
+# CHECK-NEXT: 2 1 0.50 * vmovupd %ymm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * vmovupd (%rax), %ymm2
+# CHECK-NEXT: 1 0 0.33 vmovups %xmm0, %xmm2
+# CHECK-NEXT: 2 1 0.50 * vmovups %xmm0, (%rax)
+# CHECK-NEXT: 1 6 0.33 * vmovups (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.33 vmovups %ymm0, %ymm2
+# CHECK-NEXT: 2 1 0.50 * vmovups %ymm0, (%rax)
+# CHECK-NEXT: 1 7 0.33 * vmovups (%rax), %ymm2
# CHECK-NEXT: 2 4 1.00 vmpsadbw $1, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 3 11 1.00 * vmpsadbw $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 10 1.00 * vmpsadbw $1, (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vmulpd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vmulpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vmulpd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vmulpd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vmulpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vmulpd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vmulps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vmulps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vmulps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vmulps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vmulps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vmulps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vmulsd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vmulsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vmulsd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vmulss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vmulss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vmulss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vorpd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vorpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vorpd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vorpd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vorpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vorpd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.33 vorps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vorps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vorps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vorps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vorps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vorps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpabsb %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpabsb (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpabsb (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 vpabsd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpabsd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpabsd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 vpabsw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpabsw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpabsw (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 vpackssdw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 10 1.00 * vpackssdw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 9 1.00 * vpackssdw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 3 1.00 vpacksswb %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 10 1.00 * vpacksswb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 9 1.00 * vpacksswb (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 3 1.00 vpackusdw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 10 1.00 * vpackusdw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 9 1.00 * vpackusdw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 3 1.00 vpackuswb %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 10 1.00 * vpackuswb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 9 1.00 * vpackuswb (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vpaddb %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vpaddb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vpaddb (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vpaddd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vpaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vpaddd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vpaddq %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vpaddq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vpaddq (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpaddsb %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpaddsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpaddsb (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpaddsw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpaddsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpaddsw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpaddusb %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpaddusb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpaddusb (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpaddusw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpaddusw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpaddusw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vpaddw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vpaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vpaddw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 1.00 vpalignr $1, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 1.00 * vpalignr $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 1.00 * vpalignr $1, (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vpand %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vpand (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vpand (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vpandn %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vpandn (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vpandn (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpavgb %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpavgb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpavgb (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpavgw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpavgw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpavgw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 3 3 1.00 vpblendvb %xmm3, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 4 9 1.00 * vpblendvb %xmm3, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 8 1.00 * vpblendvb %xmm3, (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpblendw $11, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpblendw $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpblendw $11, (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 3 1.00 vpclmulqdq $11, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 10 1.00 * vpclmulqdq $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 9 1.00 * vpclmulqdq $11, (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpcmpeqb %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpcmpeqb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpcmpeqb (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpcmpeqd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpcmpeqd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpcmpeqd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpcmpeqq %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpcmpeqq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpcmpeqq (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpcmpeqw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpcmpeqw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpcmpeqw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 8 16 3.00 vpcmpestri $1, %xmm0, %xmm2
# CHECK-NEXT: 8 31 3.00 * vpcmpestri $1, (%rax), %xmm2
# CHECK-NEXT: 9 16 3.00 vpcmpestrm $1, %xmm0, %xmm2
# CHECK-NEXT: 9 17 3.00 * vpcmpestrm $1, (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 vpcmpgtb %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpcmpgtb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpcmpgtb (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpcmpgtd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpcmpgtd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpcmpgtd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 3 1.00 vpcmpgtq %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 10 1.00 * vpcmpgtq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 9 1.00 * vpcmpgtq (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpcmpgtw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpcmpgtw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpcmpgtw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 3 11 3.00 vpcmpistri $1, %xmm0, %xmm2
# CHECK-NEXT: 4 31 3.00 * vpcmpistri $1, (%rax), %xmm2
# CHECK-NEXT: 3 11 3.00 vpcmpistrm $1, %xmm0, %xmm2
# CHECK-NEXT: 4 16 3.00 * vpcmpistrm $1, (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 vperm2f128 $1, %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vperm2f128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 10 1.00 * vperm2f128 $1, (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 1.00 vpermilpd $1, %xmm0, %xmm2
-# CHECK-NEXT: 2 8 1.00 * vpermilpd $1, (%rax), %xmm2
+# CHECK-NEXT: 2 7 1.00 * vpermilpd $1, (%rax), %xmm2
# CHECK-NEXT: 1 1 1.00 vpermilpd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 1.00 * vpermilpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 1.00 * vpermilpd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 1.00 vpermilpd $1, %ymm0, %ymm2
-# CHECK-NEXT: 2 9 1.00 * vpermilpd $1, (%rax), %ymm2
+# CHECK-NEXT: 2 8 1.00 * vpermilpd $1, (%rax), %ymm2
# CHECK-NEXT: 1 1 1.00 vpermilpd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 1.00 * vpermilpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 1.00 * vpermilpd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 1.00 vpermilps $1, %xmm0, %xmm2
-# CHECK-NEXT: 2 8 1.00 * vpermilps $1, (%rax), %xmm2
+# CHECK-NEXT: 2 7 1.00 * vpermilps $1, (%rax), %xmm2
# CHECK-NEXT: 1 1 1.00 vpermilps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 1.00 * vpermilps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 1.00 * vpermilps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 1.00 vpermilps $1, %ymm0, %ymm2
-# CHECK-NEXT: 2 9 1.00 * vpermilps $1, (%rax), %ymm2
+# CHECK-NEXT: 2 8 1.00 * vpermilps $1, (%rax), %ymm2
# CHECK-NEXT: 1 1 1.00 vpermilps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 1.00 * vpermilps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 1.00 * vpermilps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 2 4 1.00 vpextrb $1, %xmm0, %ecx
-# CHECK-NEXT: 3 19 0.50 * vpextrb $1, %xmm0, (%rax)
+# CHECK-NEXT: 3 2 0.50 * vpextrb $1, %xmm0, (%rax)
# CHECK-NEXT: 2 4 1.00 vpextrd $1, %xmm0, %ecx
-# CHECK-NEXT: 3 12 0.50 * vpextrd $1, %xmm0, (%rax)
+# CHECK-NEXT: 3 2 0.50 * vpextrd $1, %xmm0, (%rax)
# CHECK-NEXT: 2 4 1.00 vpextrq $1, %xmm0, %rcx
-# CHECK-NEXT: 3 12 0.50 * vpextrq $1, %xmm0, (%rax)
+# CHECK-NEXT: 3 2 0.50 * vpextrq $1, %xmm0, (%rax)
# CHECK-NEXT: 2 4 1.00 vpextrw $1, %xmm0, %ecx
-# CHECK-NEXT: 3 19 0.50 * vpextrw $1, %xmm0, (%rax)
+# CHECK-NEXT: 3 2 0.50 * vpextrw $1, %xmm0, (%rax)
# CHECK-NEXT: 3 2 1.00 vphaddd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 4 9 1.00 * vphaddd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 8 1.00 * vphaddd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 3 2 1.00 vphaddsw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 4 9 1.00 * vphaddsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 8 1.00 * vphaddsw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 3 2 1.00 vphaddw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 4 9 1.00 * vphaddw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 8 1.00 * vphaddw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 1.00 vphminposuw %xmm0, %xmm2
# CHECK-NEXT: 2 11 1.00 * vphminposuw (%rax), %xmm2
# CHECK-NEXT: 3 2 1.00 vphsubd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 4 9 1.00 * vphsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 8 1.00 * vphsubd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 3 2 1.00 vphsubsw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 4 9 1.00 * vphsubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 8 1.00 * vphsubsw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 3 2 1.00 vphsubw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 4 9 1.00 * vphsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 4 8 1.00 * vphsubw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 2 4 1.00 vpinsrb $1, %eax, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpinsrb $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpinsrb $1, (%rax), %xmm1, %xmm2
# CHECK-NEXT: 2 4 1.00 vpinsrd $1, %eax, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpinsrd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpinsrd $1, (%rax), %xmm1, %xmm2
# CHECK-NEXT: 2 4 1.00 vpinsrq $1, %rax, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpinsrq $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpinsrq $1, (%rax), %xmm1, %xmm2
# CHECK-NEXT: 2 4 1.00 vpinsrw $1, %eax, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpinsrw $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpinsrw $1, (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 5 0.50 vpmaddubsw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 13 0.50 * vpmaddubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vpmaddubsw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 5 0.50 vpmaddwd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 13 0.50 * vpmaddwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vpmaddwd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpmaxsb %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpmaxsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpmaxsb (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpmaxsd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpmaxsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpmaxsd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpmaxsw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpmaxsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpmaxsw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpmaxub %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpmaxub (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpmaxub (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpmaxud %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpmaxud (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpmaxud (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpmaxuw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpmaxuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpmaxuw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpminsb %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpminsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpminsb (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpminsd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpminsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpminsd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpminsw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpminsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpminsw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpminub %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpminub (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpminub (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpminud %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpminud (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpminud (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpminuw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpminuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpminuw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 3 1.00 vpmovmskb %xmm0, %ecx
# CHECK-NEXT: 1 1 0.50 vpmovsxbd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpmovsxbd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpmovsxbd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 vpmovsxbq %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpmovsxbq (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpmovsxbq (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 vpmovsxbw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpmovsxbw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpmovsxbw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 vpmovsxdq %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpmovsxdq (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpmovsxdq (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 vpmovsxwd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpmovsxwd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpmovsxwd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 vpmovsxwq %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpmovsxwq (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpmovsxwq (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 vpmovzxbd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpmovzxbd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpmovzxbd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 vpmovzxbq %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpmovzxbq (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpmovzxbq (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 vpmovzxbw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpmovzxbw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpmovzxbw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 vpmovzxdq %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpmovzxdq (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpmovzxdq (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 vpmovzxwd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpmovzxwd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpmovzxwd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 vpmovzxwq %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpmovzxwq (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpmovzxwq (%rax), %xmm2
# CHECK-NEXT: 1 5 0.50 vpmuldq %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 13 0.50 * vpmuldq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vpmuldq (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 5 0.50 vpmulhrsw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 13 0.50 * vpmulhrsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vpmulhrsw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 5 0.50 vpmulhuw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 13 0.50 * vpmulhuw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vpmulhuw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 5 0.50 vpmulhw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 13 0.50 * vpmulhw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vpmulhw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 2 10 1.00 vpmulld %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 3 18 1.00 * vpmulld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 16 1.00 * vpmulld (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 5 0.50 vpmullw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 13 0.50 * vpmullw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vpmullw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 5 0.50 vpmuludq %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 13 0.50 * vpmuludq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vpmuludq (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vpor %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vpor (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vpor (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 3 1.00 vpsadbw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 10 1.00 * vpsadbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 9 1.00 * vpsadbw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpshufb %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpshufb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpshufb (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpshufd $1, %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpshufd $1, (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpshufd $1, (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 vpshufhw $1, %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpshufhw $1, (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpshufhw $1, (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 vpshuflw $1, %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpshuflw $1, (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpshuflw $1, (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 vpsignb %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpsignb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpsignb (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsignd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpsignd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpsignd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsignw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpsignw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpsignw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpslld $1, %xmm0, %xmm2
# CHECK-NEXT: 2 2 0.67 vpslld %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpslld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpslld (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpslldq $1, %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsllq $1, %xmm0, %xmm2
# CHECK-NEXT: 2 2 0.67 vpsllq %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpsllq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpsllq (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsllw $1, %xmm0, %xmm2
# CHECK-NEXT: 2 2 0.67 vpsllw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpsllw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpsllw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsrad $1, %xmm0, %xmm2
# CHECK-NEXT: 2 2 0.67 vpsrad %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpsrad (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpsrad (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsraw $1, %xmm0, %xmm2
# CHECK-NEXT: 2 2 0.67 vpsraw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpsraw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpsraw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsrld $1, %xmm0, %xmm2
# CHECK-NEXT: 2 2 0.67 vpsrld %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpsrld (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpsrld (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsrldq $1, %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsrlq $1, %xmm0, %xmm2
# CHECK-NEXT: 2 2 0.67 vpsrlq %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpsrlq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpsrlq (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsrlw $1, %xmm0, %xmm2
# CHECK-NEXT: 2 2 0.67 vpsrlw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpsrlw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpsrlw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vpsubb %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vpsubb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vpsubb (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vpsubd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vpsubd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vpsubd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vpsubq %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vpsubq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vpsubq (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsubsb %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpsubsb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpsubsb (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsubsw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpsubsw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpsubsw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsubusb %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpsubusb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpsubusb (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsubusw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpsubusw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpsubusw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vpsubw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vpsubw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vpsubw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 2 4 1.00 vptest %xmm0, %xmm1
# CHECK-NEXT: 3 9 1.00 * vptest (%rax), %xmm1
# CHECK-NEXT: 2 6 1.00 vptest %ymm0, %ymm1
# CHECK-NEXT: 3 12 1.00 * vptest (%rax), %ymm1
# CHECK-NEXT: 1 1 0.50 vpunpckhbw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpunpckhbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpunpckhbw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpunpckhdq %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpunpckhdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpunpckhdq (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpunpckhqdq %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpunpckhqdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpunpckhqdq (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpunpckhwd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpunpckhwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpunpckhwd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpunpcklbw %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpunpcklbw (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpunpcklbw (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpunpckldq %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpunpckldq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpunpckldq (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpunpcklqdq %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpunpcklqdq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpunpcklqdq (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpunpcklwd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpunpcklwd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpunpcklwd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vpxor %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vpxor (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vpxor (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 1.00 vrcpps %xmm0, %xmm2
-# CHECK-NEXT: 2 11 1.00 * vrcpps (%rax), %xmm2
+# CHECK-NEXT: 2 10 1.00 * vrcpps (%rax), %xmm2
# CHECK-NEXT: 1 4 1.00 vrcpps %ymm0, %ymm2
-# CHECK-NEXT: 2 12 1.00 * vrcpps (%rax), %ymm2
+# CHECK-NEXT: 2 11 1.00 * vrcpps (%rax), %ymm2
# CHECK-NEXT: 1 4 1.00 vrcpss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 1.00 * vrcpss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 1.00 * vrcpss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 2 8 1.00 vroundpd $1, %xmm0, %xmm2
-# CHECK-NEXT: 3 15 1.00 * vroundpd $1, (%rax), %xmm2
+# CHECK-NEXT: 3 14 1.00 * vroundpd $1, (%rax), %xmm2
# CHECK-NEXT: 2 8 1.00 vroundpd $1, %ymm0, %ymm2
-# CHECK-NEXT: 3 16 1.00 * vroundpd $1, (%rax), %ymm2
+# CHECK-NEXT: 3 15 1.00 * vroundpd $1, (%rax), %ymm2
# CHECK-NEXT: 2 8 1.00 vroundps $1, %xmm0, %xmm2
-# CHECK-NEXT: 3 15 1.00 * vroundps $1, (%rax), %xmm2
+# CHECK-NEXT: 3 14 1.00 * vroundps $1, (%rax), %xmm2
# CHECK-NEXT: 2 8 1.00 vroundps $1, %ymm0, %ymm2
-# CHECK-NEXT: 3 16 1.00 * vroundps $1, (%rax), %ymm2
+# CHECK-NEXT: 3 15 1.00 * vroundps $1, (%rax), %ymm2
# CHECK-NEXT: 2 8 1.00 vroundsd $1, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 3 15 1.00 * vroundsd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 14 1.00 * vroundsd $1, (%rax), %xmm1, %xmm2
# CHECK-NEXT: 2 8 1.00 vroundss $1, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 3 15 1.00 * vroundss $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 3 14 1.00 * vroundss $1, (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 1.00 vrsqrtps %xmm0, %xmm2
-# CHECK-NEXT: 2 11 1.00 * vrsqrtps (%rax), %xmm2
+# CHECK-NEXT: 2 10 1.00 * vrsqrtps (%rax), %xmm2
# CHECK-NEXT: 1 4 1.00 vrsqrtps %ymm0, %ymm2
-# CHECK-NEXT: 2 12 1.00 * vrsqrtps (%rax), %ymm2
+# CHECK-NEXT: 2 11 1.00 * vrsqrtps (%rax), %ymm2
# CHECK-NEXT: 1 4 1.00 vrsqrtss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 1.00 * vrsqrtss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 1.00 * vrsqrtss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vshufpd $1, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vshufpd $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vshufpd $1, (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vshufpd $1, %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vshufpd $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vshufpd $1, (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vshufps $1, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vshufps $1, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vshufps $1, (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vshufps $1, %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vshufps $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vshufps $1, (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 18 1.00 vsqrtpd %xmm0, %xmm2
# CHECK-NEXT: 2 24 1.00 * vsqrtpd (%rax), %xmm2
# CHECK-NEXT: 1 18 1.00 vsqrtpd %ymm0, %ymm2
# CHECK-NEXT: 2 25 1.00 * vsqrtpd (%rax), %ymm2
# CHECK-NEXT: 1 12 1.00 vsqrtps %xmm0, %xmm2
-# CHECK-NEXT: 2 19 1.00 * vsqrtps (%rax), %xmm2
+# CHECK-NEXT: 2 18 1.00 * vsqrtps (%rax), %xmm2
# CHECK-NEXT: 1 12 1.00 vsqrtps %ymm0, %ymm2
-# CHECK-NEXT: 2 20 1.00 * vsqrtps (%rax), %ymm2
+# CHECK-NEXT: 2 19 1.00 * vsqrtps (%rax), %ymm2
# CHECK-NEXT: 1 18 1.00 vsqrtsd %xmm0, %xmm1, %xmm2
# CHECK-NEXT: 2 24 1.00 * vsqrtsd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 12 1.00 vsqrtss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 19 1.00 * vsqrtss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 18 1.00 * vsqrtss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 4 12 1.00 * U vstmxcsr (%rax)
-# CHECK-NEXT: 1 3 0.50 vsubpd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 10 0.50 * vsubpd (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 3 0.50 vsubpd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 11 0.50 * vsubpd (%rax), %ymm1, %ymm2
-# CHECK-NEXT: 1 3 0.50 vsubps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 10 0.50 * vsubps (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 3 0.50 vsubps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 11 0.50 * vsubps (%rax), %ymm1, %ymm2
-# CHECK-NEXT: 1 3 0.50 vsubsd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 10 0.50 * vsubsd (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 3 0.50 vsubss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 10 0.50 * vsubss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vsubpd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 9 0.50 * vsubpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vsubpd %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 10 0.50 * vsubpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 2 0.50 vsubps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 9 0.50 * vsubps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vsubps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 10 0.50 * vsubps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 2 0.50 vsubsd %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 9 0.50 * vsubsd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 2 0.50 vsubss %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 9 0.50 * vsubss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 3 1.00 vtestpd %xmm0, %xmm1
# CHECK-NEXT: 2 8 1.00 * vtestpd (%rax), %xmm1
# CHECK-NEXT: 1 5 1.00 vtestpd %ymm0, %ymm1
@@ -1692,33 +1692,33 @@ vzeroupper
# CHECK-NEXT: 1 5 1.00 vtestps %ymm0, %ymm1
# CHECK-NEXT: 2 11 1.00 * vtestps (%rax), %ymm1
# CHECK-NEXT: 1 3 1.00 vucomisd %xmm0, %xmm1
-# CHECK-NEXT: 2 8 1.00 * vucomisd (%rax), %xmm1
+# CHECK-NEXT: 2 9 1.00 * vucomisd (%rax), %xmm1
# CHECK-NEXT: 1 3 1.00 vucomiss %xmm0, %xmm1
-# CHECK-NEXT: 2 8 1.00 * vucomiss (%rax), %xmm1
+# CHECK-NEXT: 2 9 1.00 * vucomiss (%rax), %xmm1
# CHECK-NEXT: 1 1 1.00 vunpckhpd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 1.00 * vunpckhpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 1.00 * vunpckhpd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 1.00 vunpckhpd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 1.00 * vunpckhpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 1.00 * vunpckhpd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 1.00 vunpckhps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 1.00 * vunpckhps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 1.00 * vunpckhps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 1.00 vunpckhps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 1.00 * vunpckhps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 1.00 * vunpckhps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 1.00 vunpcklpd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 1.00 * vunpcklpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 1.00 * vunpcklpd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 1.00 vunpcklpd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 1.00 * vunpcklpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 1.00 * vunpcklpd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 1.00 vunpcklps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 1.00 * vunpcklps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 1.00 * vunpcklps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 1.00 vunpcklps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 1.00 * vunpcklps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 1.00 * vunpcklps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.33 vxorpd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vxorpd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vxorpd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vxorpd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vxorpd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vxorpd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.33 vxorps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vxorps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vxorps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vxorps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vxorps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vxorps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 10 16 3.00 U vzeroall
# CHECK-NEXT: 0 0 0.00 U vzeroupper
@@ -1739,7 +1739,7 @@ vzeroupper
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
-# CHECK-NEXT: 310.90 275.73 107.33 107.33 19.50 277.73 8.90 18.83 18.50 18.50 0.73 107.00 -
+# CHECK-NEXT: 314.40 279.73 107.33 107.33 19.50 281.73 9.40 18.83 18.50 18.50 0.73 107.00 -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
@@ -1965,16 +1965,16 @@ vzeroupper
# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vminsd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vminss %xmm0, %xmm1, %xmm2
# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - vminss (%rax), %xmm1, %xmm2
-# CHECK-NEXT: - - - - - - - - - - - - - vmovapd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vmovapd %xmm0, %xmm2
# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovapd %xmm0, (%rax)
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovapd (%rax), %xmm2
-# CHECK-NEXT: - - - - - - - - - - - - - vmovapd %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vmovapd %ymm0, %ymm2
# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovapd %ymm0, (%rax)
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovapd (%rax), %ymm2
-# CHECK-NEXT: - - - - - - - - - - - - - vmovaps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vmovaps %xmm0, %xmm2
# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovaps %xmm0, (%rax)
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovaps (%rax), %xmm2
-# CHECK-NEXT: - - - - - - - - - - - - - vmovaps %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vmovaps %ymm0, %ymm2
# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovaps %ymm0, (%rax)
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovaps (%rax), %ymm2
# CHECK-NEXT: - - - - - 1.00 - - - - - - - vmovd %eax, %xmm2
@@ -1985,16 +1985,16 @@ vzeroupper
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovddup (%rax), %xmm2
# CHECK-NEXT: - - - - - 1.00 - - - - - - - vmovddup %ymm0, %ymm2
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovddup (%rax), %ymm2
-# CHECK-NEXT: - - - - - - - - - - - - - vmovdqa %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vmovdqa %xmm0, %xmm2
# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovdqa %xmm0, (%rax)
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovdqa (%rax), %xmm2
-# CHECK-NEXT: - - - - - - - - - - - - - vmovdqa %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vmovdqa %ymm0, %ymm2
# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovdqa %ymm0, (%rax)
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovdqa (%rax), %ymm2
-# CHECK-NEXT: - - - - - - - - - - - - - vmovdqu %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vmovdqu %xmm0, %xmm2
# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovdqu %xmm0, (%rax)
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovdqu (%rax), %xmm2
-# CHECK-NEXT: - - - - - - - - - - - - - vmovdqu %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vmovdqu %ymm0, %ymm2
# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovdqu %ymm0, (%rax)
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovdqu (%rax), %ymm2
# CHECK-NEXT: - - - - - 1.00 - - - - - - - vmovhlps %xmm0, %xmm1, %xmm2
@@ -2038,16 +2038,16 @@ vzeroupper
# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vmovss %xmm0, %xmm1, %xmm2
# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovss %xmm0, (%rax)
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovss (%rax), %xmm2
-# CHECK-NEXT: - - - - - - - - - - - - - vmovupd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vmovupd %xmm0, %xmm2
# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovupd %xmm0, (%rax)
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovupd (%rax), %xmm2
-# CHECK-NEXT: - - - - - - - - - - - - - vmovupd %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vmovupd %ymm0, %ymm2
# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovupd %ymm0, (%rax)
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovupd (%rax), %ymm2
-# CHECK-NEXT: - - - - - - - - - - - - - vmovups %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vmovups %xmm0, %xmm2
# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovups %xmm0, (%rax)
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovups (%rax), %xmm2
-# CHECK-NEXT: - - - - - - - - - - - - - vmovups %ymm0, %ymm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - vmovups %ymm0, %ymm2
# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - vmovups %ymm0, (%rax)
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - vmovups (%rax), %ymm2
# CHECK-NEXT: - 0.50 - - - 1.50 - - - - - - - vmpsadbw $1, %xmm0, %xmm1, %xmm2
@@ -2383,7 +2383,7 @@ vzeroupper
# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vsqrtsd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1.00 - - - - - - - - - - - - vsqrtss %xmm0, %xmm1, %xmm2
# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - vsqrtss (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1.50 - - - 0.50 - 0.50 0.50 0.50 0.50 - - - vstmxcsr (%rax)
+# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - vstmxcsr (%rax)
# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vsubpd %xmm0, %xmm1, %xmm2
# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - vsubpd (%rax), %xmm1, %xmm2
# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - vsubpd %ymm0, %ymm1, %ymm2
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx2.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx2.s
index 96f66d1aad6c..eada999e002e 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx2.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avx2.s
@@ -460,11 +460,11 @@ vpxor (%rax), %ymm1, %ymm2
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 8 0.33 * vbroadcasti128 (%rax), %ymm0
+# CHECK-NEXT: 1 7 0.33 * vbroadcasti128 (%rax), %ymm0
# CHECK-NEXT: 1 3 1.00 vbroadcastsd %xmm0, %ymm0
# CHECK-NEXT: 1 3 1.00 vbroadcastss %xmm0, %ymm0
# CHECK-NEXT: 1 3 1.00 vextracti128 $1, %ymm0, %xmm2
-# CHECK-NEXT: 2 12 0.50 * vextracti128 $1, %ymm0, (%rax)
+# CHECK-NEXT: 2 1 0.50 * vextracti128 $1, %ymm0, (%rax)
# CHECK-NEXT: 5 20 1.00 * vgatherdpd %xmm0, (%rax,%xmm1,2), %xmm2
# CHECK-NEXT: 8 29 1.33 * vgatherdpd %ymm0, (%rax,%xmm1,2), %ymm2
# CHECK-NEXT: 8 28 1.33 * vgatherdps %xmm0, (%rax,%xmm1,2), %xmm2
@@ -477,97 +477,97 @@ vpxor (%rax), %ymm1, %ymm2
# CHECK-NEXT: 2 9 0.33 * vinserti128 $1, (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 8 0.33 * vmovntdqa (%rax), %ymm0
# CHECK-NEXT: 2 4 1.00 vmpsadbw $1, %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 3 12 1.00 * vmpsadbw $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 11 1.00 * vmpsadbw $1, (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpabsb %ymm0, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpabsb (%rax), %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpabsb (%rax), %ymm2
# CHECK-NEXT: 1 1 0.50 vpabsd %ymm0, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpabsd (%rax), %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpabsd (%rax), %ymm2
# CHECK-NEXT: 1 1 0.50 vpabsw %ymm0, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpabsw (%rax), %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpabsw (%rax), %ymm2
# CHECK-NEXT: 1 3 1.00 vpackssdw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vpackssdw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 10 1.00 * vpackssdw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 3 1.00 vpacksswb %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vpacksswb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 10 1.00 * vpacksswb (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 3 1.00 vpackusdw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vpackusdw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 10 1.00 * vpackusdw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 3 1.00 vpackuswb %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vpackuswb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 10 1.00 * vpackuswb (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.33 vpaddb %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vpaddb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vpaddb (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.33 vpaddd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vpaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vpaddd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.33 vpaddq %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vpaddq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vpaddq (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpaddsb %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpaddsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpaddsb (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpaddsw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpaddsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpaddsw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpaddusb %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpaddusb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpaddusb (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpaddusw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpaddusw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpaddusw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.33 vpaddw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vpaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vpaddw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 1.00 vpalignr $1, %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 1.00 * vpalignr $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 1.00 * vpalignr $1, (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.33 vpand %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vpand (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vpand (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.33 vpandn %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vpandn (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vpandn (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpavgb %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpavgb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpavgb (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpavgw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpavgw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpavgw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.33 vpblendd $11, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.33 * vpblendd $11, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.33 * vpblendd $11, (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.33 vpblendd $11, %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vpblendd $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vpblendd $11, (%rax), %ymm1, %ymm2
# CHECK-NEXT: 3 3 1.00 vpblendvb %ymm3, %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 4 10 1.00 * vpblendvb %ymm3, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 9 1.00 * vpblendvb %ymm3, (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpblendw $11, %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpblendw $11, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpblendw $11, (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 1.00 vpbroadcastb %xmm0, %xmm0
-# CHECK-NEXT: 2 8 1.00 * vpbroadcastb (%rax), %xmm0
+# CHECK-NEXT: 2 7 1.00 * vpbroadcastb (%rax), %xmm0
# CHECK-NEXT: 1 3 1.00 vpbroadcastb %xmm0, %ymm0
-# CHECK-NEXT: 2 9 1.00 * vpbroadcastb (%rax), %ymm0
+# CHECK-NEXT: 2 8 1.00 * vpbroadcastb (%rax), %ymm0
# CHECK-NEXT: 1 1 1.00 vpbroadcastd %xmm0, %xmm0
-# CHECK-NEXT: 1 7 0.33 * vpbroadcastd (%rax), %xmm0
+# CHECK-NEXT: 1 6 0.33 * vpbroadcastd (%rax), %xmm0
# CHECK-NEXT: 1 3 1.00 vpbroadcastd %xmm0, %ymm0
-# CHECK-NEXT: 1 8 0.33 * vpbroadcastd (%rax), %ymm0
+# CHECK-NEXT: 1 7 0.33 * vpbroadcastd (%rax), %ymm0
# CHECK-NEXT: 1 1 1.00 vpbroadcastq %xmm0, %xmm0
-# CHECK-NEXT: 1 7 0.33 * vpbroadcastq (%rax), %xmm0
+# CHECK-NEXT: 1 6 0.33 * vpbroadcastq (%rax), %xmm0
# CHECK-NEXT: 1 3 1.00 vpbroadcastq %xmm0, %ymm0
-# CHECK-NEXT: 1 8 0.33 * vpbroadcastq (%rax), %ymm0
+# CHECK-NEXT: 1 7 0.33 * vpbroadcastq (%rax), %ymm0
# CHECK-NEXT: 1 1 1.00 vpbroadcastw %xmm0, %xmm0
-# CHECK-NEXT: 2 8 1.00 * vpbroadcastw (%rax), %xmm0
+# CHECK-NEXT: 2 7 1.00 * vpbroadcastw (%rax), %xmm0
# CHECK-NEXT: 1 3 1.00 vpbroadcastw %xmm0, %ymm0
-# CHECK-NEXT: 2 9 1.00 * vpbroadcastw (%rax), %ymm0
+# CHECK-NEXT: 2 8 1.00 * vpbroadcastw (%rax), %ymm0
# CHECK-NEXT: 1 1 0.50 vpcmpeqb %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpcmpeqb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpcmpeqb (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpcmpeqd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpcmpeqd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpcmpeqd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpcmpeqq %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpcmpeqq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpcmpeqq (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpcmpeqw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpcmpeqw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpcmpeqw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpcmpgtb %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpcmpgtb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpcmpgtb (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpcmpgtd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpcmpgtd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpcmpgtd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 3 1.00 vpcmpgtq %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vpcmpgtq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 10 1.00 * vpcmpgtq (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpcmpgtw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpcmpgtw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpcmpgtw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 3 1.00 vperm2i128 $1, %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vperm2i128 $1, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 10 1.00 * vperm2i128 $1, (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 3 1.00 vpermd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vpermd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 10 1.00 * vpermd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 3 1.00 vpermpd $1, %ymm0, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vpermpd $1, (%rax), %ymm2
+# CHECK-NEXT: 2 10 1.00 * vpermpd $1, (%rax), %ymm2
# CHECK-NEXT: 1 3 1.00 vpermps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vpermps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 10 1.00 * vpermps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 3 1.00 vpermq $1, %ymm0, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vpermq $1, (%rax), %ymm2
+# CHECK-NEXT: 2 10 1.00 * vpermq $1, (%rax), %ymm2
# CHECK-NEXT: 8 28 1.33 * vpgatherdd %xmm0, (%rax,%xmm1,2), %xmm2
# CHECK-NEXT: 12 30 2.67 * vpgatherdd %ymm0, (%rax,%ymm1,2), %ymm2
# CHECK-NEXT: 5 20 1.00 * vpgatherdq %xmm0, (%rax,%xmm1,2), %xmm2
@@ -577,190 +577,190 @@ vpxor (%rax), %ymm1, %ymm2
# CHECK-NEXT: 5 20 1.00 * vpgatherqq %xmm0, (%rax,%xmm1,2), %xmm2
# CHECK-NEXT: 8 29 1.33 * vpgatherqq %ymm0, (%rax,%ymm1,2), %ymm2
# CHECK-NEXT: 3 2 1.00 vphaddd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 4 10 1.00 * vphaddd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 9 1.00 * vphaddd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 3 2 1.00 vphaddsw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 4 10 1.00 * vphaddsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 9 1.00 * vphaddsw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 3 2 1.00 vphaddw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 4 10 1.00 * vphaddw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 9 1.00 * vphaddw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 3 2 1.00 vphsubd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 4 10 1.00 * vphsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 9 1.00 * vphsubd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 3 2 1.00 vphsubsw %ymm0, %ymm1, %ymm2
# CHECK-NEXT: 4 10 1.00 * vphsubsw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 3 2 1.00 vphsubw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 4 10 1.00 * vphsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 4 9 1.00 * vphsubw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 5 0.50 vpmaddubsw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 13 0.50 * vpmaddubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vpmaddubsw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 5 0.50 vpmaddwd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 13 0.50 * vpmaddwd (%rax), %ymm1, %ymm2
-# CHECK-NEXT: 2 8 0.33 * vpmaskmovd (%rax), %xmm0, %xmm2
-# CHECK-NEXT: 2 9 0.33 * vpmaskmovd (%rax), %ymm0, %ymm2
-# CHECK-NEXT: 3 14 1.00 * * vpmaskmovd %xmm0, %xmm1, (%rax)
-# CHECK-NEXT: 3 14 1.00 * * vpmaskmovd %ymm0, %ymm1, (%rax)
-# CHECK-NEXT: 2 8 0.33 * vpmaskmovq (%rax), %xmm0, %xmm2
-# CHECK-NEXT: 2 9 0.33 * vpmaskmovq (%rax), %ymm0, %ymm2
-# CHECK-NEXT: 3 14 1.00 * * vpmaskmovq %xmm0, %xmm1, (%rax)
-# CHECK-NEXT: 3 14 1.00 * * vpmaskmovq %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 2 12 0.50 * vpmaddwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 7 0.33 * vpmaskmovd (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vpmaskmovd (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 3 3 1.00 * * vpmaskmovd %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 3 3 1.00 * * vpmaskmovd %ymm0, %ymm1, (%rax)
+# CHECK-NEXT: 2 7 0.33 * vpmaskmovq (%rax), %xmm0, %xmm2
+# CHECK-NEXT: 2 8 0.33 * vpmaskmovq (%rax), %ymm0, %ymm2
+# CHECK-NEXT: 3 3 1.00 * * vpmaskmovq %xmm0, %xmm1, (%rax)
+# CHECK-NEXT: 3 3 1.00 * * vpmaskmovq %ymm0, %ymm1, (%rax)
# CHECK-NEXT: 1 1 0.50 vpmaxsb %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpmaxsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpmaxsb (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpmaxsd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpmaxsd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpmaxsd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpmaxsw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpmaxsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpmaxsw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpmaxub %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpmaxub (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpmaxub (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpmaxud %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpmaxud (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpmaxud (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpmaxuw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpmaxuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpmaxuw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpminsb %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpminsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpminsb (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpminsd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpminsd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpminsd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpminsw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpminsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpminsw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpminub %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpminub (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpminub (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpminud %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpminud (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpminud (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpminuw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpminuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpminuw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 1.00 vpmovmskb %ymm0, %ecx
# CHECK-NEXT: 1 3 1.00 vpmovsxbd %xmm0, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vpmovsxbd (%rax), %ymm2
+# CHECK-NEXT: 2 10 1.00 * vpmovsxbd (%rax), %ymm2
# CHECK-NEXT: 1 3 1.00 vpmovsxbq %xmm0, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vpmovsxbq (%rax), %ymm2
+# CHECK-NEXT: 2 10 1.00 * vpmovsxbq (%rax), %ymm2
# CHECK-NEXT: 1 3 1.00 vpmovsxbw %xmm0, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vpmovsxbw (%rax), %ymm2
+# CHECK-NEXT: 2 10 1.00 * vpmovsxbw (%rax), %ymm2
# CHECK-NEXT: 1 3 1.00 vpmovsxdq %xmm0, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vpmovsxdq (%rax), %ymm2
+# CHECK-NEXT: 2 10 1.00 * vpmovsxdq (%rax), %ymm2
# CHECK-NEXT: 1 3 1.00 vpmovsxwd %xmm0, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vpmovsxwd (%rax), %ymm2
+# CHECK-NEXT: 2 10 1.00 * vpmovsxwd (%rax), %ymm2
# CHECK-NEXT: 1 3 1.00 vpmovsxwq %xmm0, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vpmovsxwq (%rax), %ymm2
+# CHECK-NEXT: 2 10 1.00 * vpmovsxwq (%rax), %ymm2
# CHECK-NEXT: 1 3 1.00 vpmovzxbd %xmm0, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vpmovzxbd (%rax), %ymm2
+# CHECK-NEXT: 2 10 1.00 * vpmovzxbd (%rax), %ymm2
# CHECK-NEXT: 1 3 1.00 vpmovzxbq %xmm0, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vpmovzxbq (%rax), %ymm2
+# CHECK-NEXT: 2 10 1.00 * vpmovzxbq (%rax), %ymm2
# CHECK-NEXT: 1 3 1.00 vpmovzxbw %xmm0, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vpmovzxbw (%rax), %ymm2
+# CHECK-NEXT: 2 10 1.00 * vpmovzxbw (%rax), %ymm2
# CHECK-NEXT: 1 3 1.00 vpmovzxdq %xmm0, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vpmovzxdq (%rax), %ymm2
+# CHECK-NEXT: 2 10 1.00 * vpmovzxdq (%rax), %ymm2
# CHECK-NEXT: 1 3 1.00 vpmovzxwd %xmm0, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vpmovzxwd (%rax), %ymm2
+# CHECK-NEXT: 2 10 1.00 * vpmovzxwd (%rax), %ymm2
# CHECK-NEXT: 1 3 1.00 vpmovzxwq %xmm0, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vpmovzxwq (%rax), %ymm2
+# CHECK-NEXT: 2 10 1.00 * vpmovzxwq (%rax), %ymm2
# CHECK-NEXT: 1 5 0.50 vpmuldq %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 13 0.50 * vpmuldq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vpmuldq (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 5 0.50 vpmulhrsw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 13 0.50 * vpmulhrsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vpmulhrsw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 5 0.50 vpmulhuw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 13 0.50 * vpmulhuw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vpmulhuw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 5 0.50 vpmulhw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 13 0.50 * vpmulhw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vpmulhw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 2 10 1.00 vpmulld %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 3 18 1.00 * vpmulld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 3 17 1.00 * vpmulld (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 5 0.50 vpmullw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 13 0.50 * vpmullw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vpmullw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 5 0.50 vpmuludq %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 13 0.50 * vpmuludq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vpmuludq (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.33 vpor %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vpor (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vpor (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 3 1.00 vpsadbw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 11 1.00 * vpsadbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 10 1.00 * vpsadbw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpshufb %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpshufb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpshufb (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpshufd $1, %ymm0, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpshufd $1, (%rax), %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpshufd $1, (%rax), %ymm2
# CHECK-NEXT: 1 1 0.50 vpshufhw $1, %ymm0, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpshufhw $1, (%rax), %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpshufhw $1, (%rax), %ymm2
# CHECK-NEXT: 1 1 0.50 vpshuflw $1, %ymm0, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpshuflw $1, (%rax), %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpshuflw $1, (%rax), %ymm2
# CHECK-NEXT: 1 1 0.50 vpsignb %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpsignb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpsignb (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpsignd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpsignd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpsignd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpsignw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpsignw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpsignw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpslld $1, %ymm0, %ymm2
# CHECK-NEXT: 2 4 1.00 vpslld %xmm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpslld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpslld (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpslldq $1, %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpsllq $1, %ymm0, %ymm2
# CHECK-NEXT: 2 4 1.00 vpsllq %xmm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpsllq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpsllq (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpsllvd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpsllvd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpsllvd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsllvd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpsllvd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpsllvd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpsllvq %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpsllvq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpsllvq (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsllvq %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpsllvq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpsllvq (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpsllw $1, %ymm0, %ymm2
# CHECK-NEXT: 2 4 1.00 vpsllw %xmm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpsllw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpsllw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpsrad $1, %ymm0, %ymm2
# CHECK-NEXT: 2 4 1.00 vpsrad %xmm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpsrad (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpsrad (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpsravd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpsravd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpsravd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsravd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpsravd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpsravd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpsraw $1, %ymm0, %ymm2
# CHECK-NEXT: 2 4 1.00 vpsraw %xmm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpsraw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpsraw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpsrld $1, %ymm0, %ymm2
# CHECK-NEXT: 2 4 1.00 vpsrld %xmm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpsrld (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpsrld (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpsrldq $1, %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpsrlq $1, %ymm0, %ymm2
# CHECK-NEXT: 2 4 1.00 vpsrlq %xmm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpsrlq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpsrlq (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpsrlvd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpsrlvd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpsrlvd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsrlvd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpsrlvd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpsrlvd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpsrlvq %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 8 0.50 * vpsrlvq (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 7 0.50 * vpsrlvq (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 1 0.50 vpsrlvq %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpsrlvq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpsrlvq (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpsrlw $1, %ymm0, %ymm2
# CHECK-NEXT: 2 4 1.00 vpsrlw %xmm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpsrlw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpsrlw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.33 vpsubb %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vpsubb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vpsubb (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.33 vpsubd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vpsubd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vpsubd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.33 vpsubq %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vpsubq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vpsubq (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpsubsb %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpsubsb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpsubsb (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpsubsw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpsubsw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpsubsw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpsubusb %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpsubusb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpsubusb (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpsubusw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpsubusw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpsubusw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.33 vpsubw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vpsubw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vpsubw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpunpckhbw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpunpckhbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpunpckhbw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpunpckhdq %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpunpckhdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpunpckhdq (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpunpckhqdq %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpunpckhqdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpunpckhqdq (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpunpckhwd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpunpckhwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpunpckhwd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpunpcklbw %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpunpcklbw (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpunpcklbw (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpunpckldq %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpunpckldq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpunpckldq (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpunpcklqdq %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpunpcklqdq (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpunpcklqdq (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.50 vpunpcklwd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.50 * vpunpcklwd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.50 * vpunpcklwd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 1 0.33 vpxor %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 9 0.33 * vpxor (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 8 0.33 * vpxor (%rax), %ymm1, %ymm2
# CHECK: Resources:
# CHECK-NEXT: [0] - ADLPPort00
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avxgfni.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avxgfni.s
index 2f9fe5dd23a1..540c82e87b0c 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avxgfni.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avxgfni.s
@@ -28,18 +28,18 @@ vgf2p8mulb (%rax), %ymm1, %ymm2
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 5 0.50 vgf2p8affineinvqb $0, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 12 0.50 * vgf2p8affineinvqb $0, (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 5 0.50 vgf2p8affineinvqb $0, %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vgf2p8affineinvqb $0, (%rax), %ymm1, %ymm2
-# CHECK-NEXT: 1 5 0.50 vgf2p8affineqb $0, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 12 0.50 * vgf2p8affineqb $0, (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 5 0.50 vgf2p8affineqb $0, %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vgf2p8affineqb $0, (%rax), %ymm1, %ymm2
-# CHECK-NEXT: 1 5 0.50 vgf2p8mulb %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 12 0.50 * vgf2p8mulb (%rax), %xmm1, %xmm2
-# CHECK-NEXT: 1 5 0.50 vgf2p8mulb %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vgf2p8mulb (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vgf2p8affineinvqb $0, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vgf2p8affineinvqb $0, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vgf2p8affineinvqb $0, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vgf2p8affineinvqb $0, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vgf2p8affineqb $0, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vgf2p8affineqb $0, (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vgf2p8affineqb $0, %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vgf2p8affineqb $0, (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 1 3 0.50 vgf2p8mulb %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vgf2p8mulb (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 1 3 0.50 vgf2p8mulb %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vgf2p8mulb (%rax), %ymm1, %ymm2
# CHECK: Resources:
# CHECK-NEXT: [0] - ADLPPort00
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avxvnni.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avxvnni.s
index 5c8d5e74e7ed..e586662d71aa 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avxvnni.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avxvnni.s
@@ -35,21 +35,21 @@ vpdpwssds (%rax), %ymm1, %ymm2
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 5 0.50 vpdpbusd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 13 0.50 * vpdpbusd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vpdpbusd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 5 0.50 vpdpbusd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 13 0.50 * vpdpbusd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vpdpbusd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 5 0.50 vpdpbusds %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 13 0.50 * vpdpbusds (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vpdpbusds (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 5 0.50 vpdpbusds %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 13 0.50 * vpdpbusds (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vpdpbusds (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 5 0.50 vpdpwssd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 13 0.50 * vpdpwssd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vpdpwssd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 5 0.50 vpdpwssd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 13 0.50 * vpdpwssd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vpdpwssd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 5 0.50 vpdpwssds %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 13 0.50 * vpdpwssds (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 11 0.50 * vpdpwssds (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 5 0.50 vpdpwssds %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 13 0.50 * vpdpwssds (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 12 0.50 * vpdpwssds (%rax), %ymm1, %ymm2
# CHECK: Resources:
# CHECK-NEXT: [0] - ADLPPort00
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi1.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi1.s
index 4ed882a37a68..652c9e3aad45 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi1.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi1.s
@@ -49,26 +49,26 @@ tzcnt (%rax), %rcx
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 2 0.33 andnl %eax, %ebx, %ecx
-# CHECK-NEXT: 2 7 0.33 * andnl (%rax), %ebx, %ecx
-# CHECK-NEXT: 1 2 0.33 andnq %rax, %rbx, %rcx
-# CHECK-NEXT: 2 7 0.33 * andnq (%rax), %rbx, %rcx
-# CHECK-NEXT: 2 6 1.00 bextrl %eax, %ebx, %ecx
-# CHECK-NEXT: 3 11 1.00 * bextrl %eax, (%rbx), %ecx
-# CHECK-NEXT: 2 6 1.00 bextrq %rax, %rbx, %rcx
-# CHECK-NEXT: 3 11 1.00 * bextrq %rax, (%rbx), %rcx
-# CHECK-NEXT: 1 2 0.33 blsil %eax, %ecx
-# CHECK-NEXT: 2 7 0.33 * blsil (%rax), %ecx
-# CHECK-NEXT: 1 2 0.33 blsiq %rax, %rcx
-# CHECK-NEXT: 2 7 0.33 * blsiq (%rax), %rcx
-# CHECK-NEXT: 1 2 0.33 blsmskl %eax, %ecx
-# CHECK-NEXT: 2 7 0.33 * blsmskl (%rax), %ecx
-# CHECK-NEXT: 1 2 0.33 blsmskq %rax, %rcx
-# CHECK-NEXT: 2 7 0.33 * blsmskq (%rax), %rcx
-# CHECK-NEXT: 1 2 0.33 blsrl %eax, %ecx
-# CHECK-NEXT: 2 7 0.33 * blsrl (%rax), %ecx
-# CHECK-NEXT: 1 2 0.33 blsrq %rax, %rcx
-# CHECK-NEXT: 2 7 0.33 * blsrq (%rax), %rcx
+# CHECK-NEXT: 1 1 0.33 andnl %eax, %ebx, %ecx
+# CHECK-NEXT: 2 6 0.33 * andnl (%rax), %ebx, %ecx
+# CHECK-NEXT: 1 1 0.33 andnq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 6 0.33 * andnq (%rax), %rbx, %rcx
+# CHECK-NEXT: 2 2 1.00 bextrl %eax, %ebx, %ecx
+# CHECK-NEXT: 3 7 1.00 * bextrl %eax, (%rbx), %ecx
+# CHECK-NEXT: 2 2 1.00 bextrq %rax, %rbx, %rcx
+# CHECK-NEXT: 3 7 1.00 * bextrq %rax, (%rbx), %rcx
+# CHECK-NEXT: 1 1 0.33 blsil %eax, %ecx
+# CHECK-NEXT: 2 6 0.33 * blsil (%rax), %ecx
+# CHECK-NEXT: 1 1 0.33 blsiq %rax, %rcx
+# CHECK-NEXT: 2 6 0.33 * blsiq (%rax), %rcx
+# CHECK-NEXT: 1 1 0.33 blsmskl %eax, %ecx
+# CHECK-NEXT: 2 6 0.33 * blsmskl (%rax), %ecx
+# CHECK-NEXT: 1 1 0.33 blsmskq %rax, %rcx
+# CHECK-NEXT: 2 6 0.33 * blsmskq (%rax), %rcx
+# CHECK-NEXT: 1 1 0.33 blsrl %eax, %ecx
+# CHECK-NEXT: 2 6 0.33 * blsrl (%rax), %ecx
+# CHECK-NEXT: 1 1 0.33 blsrq %rax, %rcx
+# CHECK-NEXT: 2 6 0.33 * blsrq (%rax), %rcx
# CHECK-NEXT: 1 3 1.00 tzcntw %ax, %cx
# CHECK-NEXT: 2 8 1.00 * tzcntw (%rax), %cx
# CHECK-NEXT: 1 3 1.00 tzcntl %eax, %ecx
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi2.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi2.s
index 559ca83906cb..8f955ff6c2d9 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi2.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-bmi2.s
@@ -58,10 +58,10 @@ shrx %rax, (%rbx), %rcx
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 3 1.00 bzhil %eax, %ebx, %ecx
-# CHECK-NEXT: 2 8 1.00 * bzhil %eax, (%rbx), %ecx
-# CHECK-NEXT: 1 3 1.00 bzhiq %rax, %rbx, %rcx
-# CHECK-NEXT: 2 8 1.00 * bzhiq %rax, (%rbx), %rcx
+# CHECK-NEXT: 1 1 1.00 bzhil %eax, %ebx, %ecx
+# CHECK-NEXT: 2 6 1.00 * bzhil %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 1 1.00 bzhiq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 6 1.00 * bzhiq %rax, (%rbx), %rcx
# CHECK-NEXT: 3 4 1.00 mulxl %eax, %ebx, %ecx
# CHECK-NEXT: 4 9 1.00 * mulxl (%rax), %ebx, %ecx
# CHECK-NEXT: 2 4 1.00 mulxq %rax, %rbx, %rcx
@@ -78,18 +78,18 @@ shrx %rax, (%rbx), %rcx
# CHECK-NEXT: 2 6 0.50 * rorxl $1, (%rax), %ecx
# CHECK-NEXT: 1 1 0.50 rorxq $1, %rax, %rcx
# CHECK-NEXT: 2 6 0.50 * rorxq $1, (%rax), %rcx
-# CHECK-NEXT: 1 3 0.50 sarxl %eax, %ebx, %ecx
-# CHECK-NEXT: 2 8 0.50 * sarxl %eax, (%rbx), %ecx
-# CHECK-NEXT: 1 3 0.50 sarxq %rax, %rbx, %rcx
-# CHECK-NEXT: 2 8 0.50 * sarxq %rax, (%rbx), %rcx
-# CHECK-NEXT: 1 3 0.50 shlxl %eax, %ebx, %ecx
-# CHECK-NEXT: 2 8 0.50 * shlxl %eax, (%rbx), %ecx
-# CHECK-NEXT: 1 3 0.50 shlxq %rax, %rbx, %rcx
-# CHECK-NEXT: 2 8 0.50 * shlxq %rax, (%rbx), %rcx
-# CHECK-NEXT: 1 3 0.50 shrxl %eax, %ebx, %ecx
-# CHECK-NEXT: 2 8 0.50 * shrxl %eax, (%rbx), %ecx
-# CHECK-NEXT: 1 3 0.50 shrxq %rax, %rbx, %rcx
-# CHECK-NEXT: 2 8 0.50 * shrxq %rax, (%rbx), %rcx
+# CHECK-NEXT: 1 1 0.50 sarxl %eax, %ebx, %ecx
+# CHECK-NEXT: 2 6 0.50 * sarxl %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.50 sarxq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 6 0.50 * sarxq %rax, (%rbx), %rcx
+# CHECK-NEXT: 1 1 0.50 shlxl %eax, %ebx, %ecx
+# CHECK-NEXT: 2 6 0.50 * shlxl %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.50 shlxq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 6 0.50 * shlxq %rax, (%rbx), %rcx
+# CHECK-NEXT: 1 1 0.50 shrxl %eax, %ebx, %ecx
+# CHECK-NEXT: 2 6 0.50 * shrxl %eax, (%rbx), %ecx
+# CHECK-NEXT: 1 1 0.50 shrxq %rax, %rbx, %rcx
+# CHECK-NEXT: 2 6 0.50 * shrxq %rax, (%rbx), %rcx
# CHECK: Resources:
# CHECK-NEXT: [0] - ADLPPort00
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clflushopt.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clflushopt.s
index e61cc06951ae..bd51197554e5 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clflushopt.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clflushopt.s
@@ -31,8 +31,8 @@ clflushopt (%rax)
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
-# CHECK-NEXT: 0.20 0.20 - - 0.50 0.20 0.20 0.50 0.50 0.50 0.20 - -
+# CHECK-NEXT: 0.25 - - - 0.50 0.25 0.25 0.50 0.50 0.50 0.25 - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
-# CHECK-NEXT: 0.20 0.20 - - 0.50 0.20 0.20 0.50 0.50 0.50 0.20 - - clflushopt (%rax)
+# CHECK-NEXT: 0.25 - - - 0.50 0.25 0.25 0.50 0.50 0.50 0.25 - - clflushopt (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clwb.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clwb.s
index d35eadcc3f9d..4d547f247d5d 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clwb.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-clwb.s
@@ -31,8 +31,8 @@ clwb (%rax)
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
-# CHECK-NEXT: 0.20 0.20 - - 0.50 0.20 0.20 0.50 0.50 0.50 0.20 - -
+# CHECK-NEXT: 0.25 - - - 0.50 0.25 0.25 0.50 0.50 0.50 0.25 - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
-# CHECK-NEXT: 0.20 0.20 - - 0.50 0.20 0.20 0.50 0.50 0.50 0.20 - - clwb (%rax)
+# CHECK-NEXT: 0.25 - - - 0.50 0.25 0.25 0.50 0.50 0.50 0.25 - - clwb (%rax)
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-cmov.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-cmov.s
index 87a0e070096c..12d157aca298 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-cmov.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-cmov.s
@@ -112,102 +112,102 @@ cmovgq (%rax), %rdi
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 0.50 cmovow %si, %di
-# CHECK-NEXT: 1 1 0.50 cmovnow %si, %di
-# CHECK-NEXT: 1 1 0.50 cmovbw %si, %di
-# CHECK-NEXT: 1 1 0.50 cmovaew %si, %di
-# CHECK-NEXT: 1 1 0.50 cmovew %si, %di
-# CHECK-NEXT: 1 1 0.50 cmovnew %si, %di
-# CHECK-NEXT: 1 1 0.50 cmovbew %si, %di
-# CHECK-NEXT: 1 1 0.50 cmovaw %si, %di
-# CHECK-NEXT: 1 1 0.50 cmovsw %si, %di
-# CHECK-NEXT: 1 1 0.50 cmovnsw %si, %di
-# CHECK-NEXT: 1 1 0.50 cmovpw %si, %di
-# CHECK-NEXT: 1 1 0.50 cmovnpw %si, %di
-# CHECK-NEXT: 1 1 0.50 cmovlw %si, %di
-# CHECK-NEXT: 1 1 0.50 cmovgew %si, %di
-# CHECK-NEXT: 1 1 0.50 cmovlew %si, %di
-# CHECK-NEXT: 1 1 0.50 cmovgw %si, %di
-# CHECK-NEXT: 2 7 0.50 * cmovow (%rax), %di
-# CHECK-NEXT: 2 7 0.50 * cmovnow (%rax), %di
-# CHECK-NEXT: 2 7 0.50 * cmovbw (%rax), %di
-# CHECK-NEXT: 2 7 0.50 * cmovaew (%rax), %di
-# CHECK-NEXT: 2 7 0.50 * cmovew (%rax), %di
-# CHECK-NEXT: 2 7 0.50 * cmovnew (%rax), %di
-# CHECK-NEXT: 2 7 0.50 * cmovbew (%rax), %di
-# CHECK-NEXT: 2 7 0.50 * cmovaw (%rax), %di
-# CHECK-NEXT: 2 7 0.50 * cmovsw (%rax), %di
-# CHECK-NEXT: 2 7 0.50 * cmovnsw (%rax), %di
-# CHECK-NEXT: 2 7 0.50 * cmovpw (%rax), %di
-# CHECK-NEXT: 2 7 0.50 * cmovnpw (%rax), %di
-# CHECK-NEXT: 2 7 0.50 * cmovlw (%rax), %di
-# CHECK-NEXT: 2 7 0.50 * cmovgew (%rax), %di
-# CHECK-NEXT: 2 7 0.50 * cmovlew (%rax), %di
-# CHECK-NEXT: 2 7 0.50 * cmovgw (%rax), %di
-# CHECK-NEXT: 1 1 0.50 cmovol %esi, %edi
-# CHECK-NEXT: 1 1 0.50 cmovnol %esi, %edi
-# CHECK-NEXT: 1 1 0.50 cmovbl %esi, %edi
-# CHECK-NEXT: 1 1 0.50 cmovael %esi, %edi
-# CHECK-NEXT: 1 1 0.50 cmovel %esi, %edi
-# CHECK-NEXT: 1 1 0.50 cmovnel %esi, %edi
-# CHECK-NEXT: 1 1 0.50 cmovbel %esi, %edi
-# CHECK-NEXT: 1 1 0.50 cmoval %esi, %edi
-# CHECK-NEXT: 1 1 0.50 cmovsl %esi, %edi
-# CHECK-NEXT: 1 1 0.50 cmovnsl %esi, %edi
-# CHECK-NEXT: 1 1 0.50 cmovpl %esi, %edi
-# CHECK-NEXT: 1 1 0.50 cmovnpl %esi, %edi
-# CHECK-NEXT: 1 1 0.50 cmovll %esi, %edi
-# CHECK-NEXT: 1 1 0.50 cmovgel %esi, %edi
-# CHECK-NEXT: 1 1 0.50 cmovlel %esi, %edi
-# CHECK-NEXT: 1 1 0.50 cmovgl %esi, %edi
-# CHECK-NEXT: 2 7 0.50 * cmovol (%rax), %edi
-# CHECK-NEXT: 2 7 0.50 * cmovnol (%rax), %edi
-# CHECK-NEXT: 2 7 0.50 * cmovbl (%rax), %edi
-# CHECK-NEXT: 2 7 0.50 * cmovael (%rax), %edi
-# CHECK-NEXT: 2 7 0.50 * cmovel (%rax), %edi
-# CHECK-NEXT: 2 7 0.50 * cmovnel (%rax), %edi
-# CHECK-NEXT: 2 7 0.50 * cmovbel (%rax), %edi
-# CHECK-NEXT: 2 7 0.50 * cmoval (%rax), %edi
-# CHECK-NEXT: 2 7 0.50 * cmovsl (%rax), %edi
-# CHECK-NEXT: 2 7 0.50 * cmovnsl (%rax), %edi
-# CHECK-NEXT: 2 7 0.50 * cmovpl (%rax), %edi
-# CHECK-NEXT: 2 7 0.50 * cmovnpl (%rax), %edi
-# CHECK-NEXT: 2 7 0.50 * cmovll (%rax), %edi
-# CHECK-NEXT: 2 7 0.50 * cmovgel (%rax), %edi
-# CHECK-NEXT: 2 7 0.50 * cmovlel (%rax), %edi
-# CHECK-NEXT: 2 7 0.50 * cmovgl (%rax), %edi
-# CHECK-NEXT: 1 1 0.50 cmovoq %rsi, %rdi
-# CHECK-NEXT: 1 1 0.50 cmovnoq %rsi, %rdi
-# CHECK-NEXT: 1 1 0.50 cmovbq %rsi, %rdi
-# CHECK-NEXT: 1 1 0.50 cmovaeq %rsi, %rdi
-# CHECK-NEXT: 1 1 0.50 cmoveq %rsi, %rdi
-# CHECK-NEXT: 1 1 0.50 cmovneq %rsi, %rdi
-# CHECK-NEXT: 1 1 0.50 cmovbeq %rsi, %rdi
-# CHECK-NEXT: 1 1 0.50 cmovaq %rsi, %rdi
-# CHECK-NEXT: 1 1 0.50 cmovsq %rsi, %rdi
-# CHECK-NEXT: 1 1 0.50 cmovnsq %rsi, %rdi
-# CHECK-NEXT: 1 1 0.50 cmovpq %rsi, %rdi
-# CHECK-NEXT: 1 1 0.50 cmovnpq %rsi, %rdi
-# CHECK-NEXT: 1 1 0.50 cmovlq %rsi, %rdi
-# CHECK-NEXT: 1 1 0.50 cmovgeq %rsi, %rdi
-# CHECK-NEXT: 1 1 0.50 cmovleq %rsi, %rdi
-# CHECK-NEXT: 1 1 0.50 cmovgq %rsi, %rdi
-# CHECK-NEXT: 2 7 0.50 * cmovoq (%rax), %rdi
-# CHECK-NEXT: 2 7 0.50 * cmovnoq (%rax), %rdi
-# CHECK-NEXT: 2 7 0.50 * cmovbq (%rax), %rdi
-# CHECK-NEXT: 2 7 0.50 * cmovaeq (%rax), %rdi
-# CHECK-NEXT: 2 7 0.50 * cmoveq (%rax), %rdi
-# CHECK-NEXT: 2 7 0.50 * cmovneq (%rax), %rdi
-# CHECK-NEXT: 2 7 0.50 * cmovbeq (%rax), %rdi
-# CHECK-NEXT: 2 7 0.50 * cmovaq (%rax), %rdi
-# CHECK-NEXT: 2 7 0.50 * cmovsq (%rax), %rdi
-# CHECK-NEXT: 2 7 0.50 * cmovnsq (%rax), %rdi
-# CHECK-NEXT: 2 7 0.50 * cmovpq (%rax), %rdi
-# CHECK-NEXT: 2 7 0.50 * cmovnpq (%rax), %rdi
-# CHECK-NEXT: 2 7 0.50 * cmovlq (%rax), %rdi
-# CHECK-NEXT: 2 7 0.50 * cmovgeq (%rax), %rdi
-# CHECK-NEXT: 2 7 0.50 * cmovleq (%rax), %rdi
-# CHECK-NEXT: 2 7 0.50 * cmovgq (%rax), %rdi
+# CHECK-NEXT: 1 2 1.00 cmovow %si, %di
+# CHECK-NEXT: 1 2 1.00 cmovnow %si, %di
+# CHECK-NEXT: 1 2 1.00 cmovbw %si, %di
+# CHECK-NEXT: 1 2 1.00 cmovaew %si, %di
+# CHECK-NEXT: 1 2 1.00 cmovew %si, %di
+# CHECK-NEXT: 1 2 1.00 cmovnew %si, %di
+# CHECK-NEXT: 1 2 1.00 cmovbew %si, %di
+# CHECK-NEXT: 1 2 1.00 cmovaw %si, %di
+# CHECK-NEXT: 1 2 1.00 cmovsw %si, %di
+# CHECK-NEXT: 1 2 1.00 cmovnsw %si, %di
+# CHECK-NEXT: 1 2 1.00 cmovpw %si, %di
+# CHECK-NEXT: 1 2 1.00 cmovnpw %si, %di
+# CHECK-NEXT: 1 2 1.00 cmovlw %si, %di
+# CHECK-NEXT: 1 2 1.00 cmovgew %si, %di
+# CHECK-NEXT: 1 2 1.00 cmovlew %si, %di
+# CHECK-NEXT: 1 2 1.00 cmovgw %si, %di
+# CHECK-NEXT: 2 6 1.00 * cmovow (%rax), %di
+# CHECK-NEXT: 2 6 1.00 * cmovnow (%rax), %di
+# CHECK-NEXT: 2 6 1.00 * cmovbw (%rax), %di
+# CHECK-NEXT: 2 6 1.00 * cmovaew (%rax), %di
+# CHECK-NEXT: 2 6 1.00 * cmovew (%rax), %di
+# CHECK-NEXT: 2 6 1.00 * cmovnew (%rax), %di
+# CHECK-NEXT: 2 6 1.00 * cmovbew (%rax), %di
+# CHECK-NEXT: 2 6 1.00 * cmovaw (%rax), %di
+# CHECK-NEXT: 2 6 1.00 * cmovsw (%rax), %di
+# CHECK-NEXT: 2 6 1.00 * cmovnsw (%rax), %di
+# CHECK-NEXT: 2 6 1.00 * cmovpw (%rax), %di
+# CHECK-NEXT: 2 6 1.00 * cmovnpw (%rax), %di
+# CHECK-NEXT: 2 6 1.00 * cmovlw (%rax), %di
+# CHECK-NEXT: 2 6 1.00 * cmovgew (%rax), %di
+# CHECK-NEXT: 2 6 1.00 * cmovlew (%rax), %di
+# CHECK-NEXT: 2 6 1.00 * cmovgw (%rax), %di
+# CHECK-NEXT: 1 2 1.00 cmovol %esi, %edi
+# CHECK-NEXT: 1 2 1.00 cmovnol %esi, %edi
+# CHECK-NEXT: 1 2 1.00 cmovbl %esi, %edi
+# CHECK-NEXT: 1 2 1.00 cmovael %esi, %edi
+# CHECK-NEXT: 1 2 1.00 cmovel %esi, %edi
+# CHECK-NEXT: 1 2 1.00 cmovnel %esi, %edi
+# CHECK-NEXT: 1 2 1.00 cmovbel %esi, %edi
+# CHECK-NEXT: 1 2 1.00 cmoval %esi, %edi
+# CHECK-NEXT: 1 2 1.00 cmovsl %esi, %edi
+# CHECK-NEXT: 1 2 1.00 cmovnsl %esi, %edi
+# CHECK-NEXT: 1 2 1.00 cmovpl %esi, %edi
+# CHECK-NEXT: 1 2 1.00 cmovnpl %esi, %edi
+# CHECK-NEXT: 1 2 1.00 cmovll %esi, %edi
+# CHECK-NEXT: 1 2 1.00 cmovgel %esi, %edi
+# CHECK-NEXT: 1 2 1.00 cmovlel %esi, %edi
+# CHECK-NEXT: 1 2 1.00 cmovgl %esi, %edi
+# CHECK-NEXT: 2 6 1.00 * cmovol (%rax), %edi
+# CHECK-NEXT: 2 6 1.00 * cmovnol (%rax), %edi
+# CHECK-NEXT: 2 6 1.00 * cmovbl (%rax), %edi
+# CHECK-NEXT: 2 6 1.00 * cmovael (%rax), %edi
+# CHECK-NEXT: 2 6 1.00 * cmovel (%rax), %edi
+# CHECK-NEXT: 2 6 1.00 * cmovnel (%rax), %edi
+# CHECK-NEXT: 2 6 1.00 * cmovbel (%rax), %edi
+# CHECK-NEXT: 2 6 1.00 * cmoval (%rax), %edi
+# CHECK-NEXT: 2 6 1.00 * cmovsl (%rax), %edi
+# CHECK-NEXT: 2 6 1.00 * cmovnsl (%rax), %edi
+# CHECK-NEXT: 2 6 1.00 * cmovpl (%rax), %edi
+# CHECK-NEXT: 2 6 1.00 * cmovnpl (%rax), %edi
+# CHECK-NEXT: 2 6 1.00 * cmovll (%rax), %edi
+# CHECK-NEXT: 2 6 1.00 * cmovgel (%rax), %edi
+# CHECK-NEXT: 2 6 1.00 * cmovlel (%rax), %edi
+# CHECK-NEXT: 2 6 1.00 * cmovgl (%rax), %edi
+# CHECK-NEXT: 1 2 1.00 cmovoq %rsi, %rdi
+# CHECK-NEXT: 1 2 1.00 cmovnoq %rsi, %rdi
+# CHECK-NEXT: 1 2 1.00 cmovbq %rsi, %rdi
+# CHECK-NEXT: 1 2 1.00 cmovaeq %rsi, %rdi
+# CHECK-NEXT: 1 2 1.00 cmoveq %rsi, %rdi
+# CHECK-NEXT: 1 2 1.00 cmovneq %rsi, %rdi
+# CHECK-NEXT: 1 2 1.00 cmovbeq %rsi, %rdi
+# CHECK-NEXT: 1 2 1.00 cmovaq %rsi, %rdi
+# CHECK-NEXT: 1 2 1.00 cmovsq %rsi, %rdi
+# CHECK-NEXT: 1 2 1.00 cmovnsq %rsi, %rdi
+# CHECK-NEXT: 1 2 1.00 cmovpq %rsi, %rdi
+# CHECK-NEXT: 1 2 1.00 cmovnpq %rsi, %rdi
+# CHECK-NEXT: 1 2 1.00 cmovlq %rsi, %rdi
+# CHECK-NEXT: 1 2 1.00 cmovgeq %rsi, %rdi
+# CHECK-NEXT: 1 2 1.00 cmovleq %rsi, %rdi
+# CHECK-NEXT: 1 2 1.00 cmovgq %rsi, %rdi
+# CHECK-NEXT: 2 6 1.00 * cmovoq (%rax), %rdi
+# CHECK-NEXT: 2 6 1.00 * cmovnoq (%rax), %rdi
+# CHECK-NEXT: 2 6 1.00 * cmovbq (%rax), %rdi
+# CHECK-NEXT: 2 6 1.00 * cmovaeq (%rax), %rdi
+# CHECK-NEXT: 2 6 1.00 * cmoveq (%rax), %rdi
+# CHECK-NEXT: 2 6 1.00 * cmovneq (%rax), %rdi
+# CHECK-NEXT: 2 6 1.00 * cmovbeq (%rax), %rdi
+# CHECK-NEXT: 2 6 1.00 * cmovaq (%rax), %rdi
+# CHECK-NEXT: 2 6 1.00 * cmovsq (%rax), %rdi
+# CHECK-NEXT: 2 6 1.00 * cmovnsq (%rax), %rdi
+# CHECK-NEXT: 2 6 1.00 * cmovpq (%rax), %rdi
+# CHECK-NEXT: 2 6 1.00 * cmovnpq (%rax), %rdi
+# CHECK-NEXT: 2 6 1.00 * cmovlq (%rax), %rdi
+# CHECK-NEXT: 2 6 1.00 * cmovgeq (%rax), %rdi
+# CHECK-NEXT: 2 6 1.00 * cmovleq (%rax), %rdi
+# CHECK-NEXT: 2 6 1.00 * cmovgq (%rax), %rdi
# CHECK: Resources:
# CHECK-NEXT: [0] - ADLPPort00
@@ -226,103 +226,103 @@ cmovgq (%rax), %rdi
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
-# CHECK-NEXT: 48.00 - 16.00 16.00 - - 48.00 - - - - 16.00 -
+# CHECK-NEXT: 96.00 - 16.00 16.00 - - 96.00 - - - - 16.00 -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovow %si, %di
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovnow %si, %di
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovbw %si, %di
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovaew %si, %di
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovew %si, %di
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovnew %si, %di
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovbew %si, %di
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovaw %si, %di
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovsw %si, %di
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovnsw %si, %di
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovpw %si, %di
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovnpw %si, %di
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovlw %si, %di
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovgew %si, %di
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovlew %si, %di
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovgw %si, %di
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovow (%rax), %di
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovnow (%rax), %di
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovbw (%rax), %di
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovaew (%rax), %di
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovew (%rax), %di
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovnew (%rax), %di
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovbew (%rax), %di
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovaw (%rax), %di
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovsw (%rax), %di
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovnsw (%rax), %di
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovpw (%rax), %di
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovnpw (%rax), %di
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovlw (%rax), %di
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovgew (%rax), %di
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovlew (%rax), %di
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovgw (%rax), %di
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovol %esi, %edi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovnol %esi, %edi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovbl %esi, %edi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovael %esi, %edi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovel %esi, %edi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovnel %esi, %edi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovbel %esi, %edi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmoval %esi, %edi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovsl %esi, %edi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovnsl %esi, %edi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovpl %esi, %edi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovnpl %esi, %edi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovll %esi, %edi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovgel %esi, %edi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovlel %esi, %edi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovgl %esi, %edi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovol (%rax), %edi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovnol (%rax), %edi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovbl (%rax), %edi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovael (%rax), %edi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovel (%rax), %edi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovnel (%rax), %edi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovbel (%rax), %edi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmoval (%rax), %edi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovsl (%rax), %edi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovnsl (%rax), %edi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovpl (%rax), %edi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovnpl (%rax), %edi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovll (%rax), %edi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovgel (%rax), %edi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovlel (%rax), %edi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovgl (%rax), %edi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovoq %rsi, %rdi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovnoq %rsi, %rdi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovbq %rsi, %rdi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovaeq %rsi, %rdi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmoveq %rsi, %rdi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovneq %rsi, %rdi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovbeq %rsi, %rdi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovaq %rsi, %rdi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovsq %rsi, %rdi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovnsq %rsi, %rdi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovpq %rsi, %rdi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovnpq %rsi, %rdi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovlq %rsi, %rdi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovgeq %rsi, %rdi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovleq %rsi, %rdi
-# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cmovgq %rsi, %rdi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovoq (%rax), %rdi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovnoq (%rax), %rdi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovbq (%rax), %rdi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovaeq (%rax), %rdi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmoveq (%rax), %rdi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovneq (%rax), %rdi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovbeq (%rax), %rdi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovaq (%rax), %rdi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovsq (%rax), %rdi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovnsq (%rax), %rdi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovpq (%rax), %rdi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovnpq (%rax), %rdi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovlq (%rax), %rdi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovgeq (%rax), %rdi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovleq (%rax), %rdi
-# CHECK-NEXT: 0.50 - 0.33 0.33 - - 0.50 - - - - 0.33 - cmovgq (%rax), %rdi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovow %si, %di
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovnow %si, %di
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovbw %si, %di
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovaew %si, %di
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovew %si, %di
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovnew %si, %di
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovbew %si, %di
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovaw %si, %di
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovsw %si, %di
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovnsw %si, %di
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovpw %si, %di
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovnpw %si, %di
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovlw %si, %di
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovgew %si, %di
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovlew %si, %di
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovgw %si, %di
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovow (%rax), %di
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovnow (%rax), %di
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovbw (%rax), %di
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovaew (%rax), %di
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovew (%rax), %di
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovnew (%rax), %di
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovbew (%rax), %di
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovaw (%rax), %di
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovsw (%rax), %di
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovnsw (%rax), %di
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovpw (%rax), %di
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovnpw (%rax), %di
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovlw (%rax), %di
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovgew (%rax), %di
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovlew (%rax), %di
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovgw (%rax), %di
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovol %esi, %edi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovnol %esi, %edi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovbl %esi, %edi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovael %esi, %edi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovel %esi, %edi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovnel %esi, %edi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovbel %esi, %edi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmoval %esi, %edi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovsl %esi, %edi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovnsl %esi, %edi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovpl %esi, %edi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovnpl %esi, %edi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovll %esi, %edi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovgel %esi, %edi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovlel %esi, %edi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovgl %esi, %edi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovol (%rax), %edi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovnol (%rax), %edi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovbl (%rax), %edi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovael (%rax), %edi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovel (%rax), %edi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovnel (%rax), %edi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovbel (%rax), %edi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmoval (%rax), %edi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovsl (%rax), %edi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovnsl (%rax), %edi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovpl (%rax), %edi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovnpl (%rax), %edi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovll (%rax), %edi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovgel (%rax), %edi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovlel (%rax), %edi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovgl (%rax), %edi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovoq %rsi, %rdi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovnoq %rsi, %rdi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovbq %rsi, %rdi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovaeq %rsi, %rdi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmoveq %rsi, %rdi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovneq %rsi, %rdi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovbeq %rsi, %rdi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovaq %rsi, %rdi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovsq %rsi, %rdi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovnsq %rsi, %rdi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovpq %rsi, %rdi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovnpq %rsi, %rdi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovlq %rsi, %rdi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovgeq %rsi, %rdi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovleq %rsi, %rdi
+# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - cmovgq %rsi, %rdi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovoq (%rax), %rdi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovnoq (%rax), %rdi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovbq (%rax), %rdi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovaeq (%rax), %rdi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmoveq (%rax), %rdi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovneq (%rax), %rdi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovbeq (%rax), %rdi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovaq (%rax), %rdi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovsq (%rax), %rdi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovnsq (%rax), %rdi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovpq (%rax), %rdi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovnpq (%rax), %rdi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovlq (%rax), %rdi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovgeq (%rax), %rdi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovleq (%rax), %rdi
+# CHECK-NEXT: 1.00 - 0.33 0.33 - - 1.00 - - - - 0.33 - cmovgq (%rax), %rdi
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-f16c.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-f16c.s
index 7e4eeebfdaca..e59bcb413af3 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-f16c.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-f16c.s
@@ -23,7 +23,7 @@ vcvtps2ph $0, %ymm0, (%rax)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 2 6 1.00 vcvtph2ps %xmm0, %xmm2
-# CHECK-NEXT: 2 12 0.50 * vcvtph2ps (%rax), %xmm2
+# CHECK-NEXT: 2 11 0.50 * vcvtph2ps (%rax), %xmm2
# CHECK-NEXT: 2 8 1.00 vcvtph2ps %xmm0, %ymm2
# CHECK-NEXT: 2 12 0.50 * vcvtph2ps (%rax), %ymm2
# CHECK-NEXT: 2 6 1.00 vcvtps2ph $0, %xmm0, %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-fma.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-fma.s
index 63fc8dbaa44b..31419a89a27b 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-fma.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-fma.s
@@ -299,197 +299,197 @@ vfnmsub231ss (%rax), %xmm1, %xmm2
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 4 0.50 vfmadd132pd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmadd132pd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmadd132pd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmadd132pd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmadd213pd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmadd213pd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmadd213pd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmadd213pd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmadd231pd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmadd231pd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmadd231pd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmadd231pd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmadd132ps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmadd132ps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmadd132ps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmadd132ps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmadd213ps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmadd213ps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmadd213ps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmadd213ps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmadd231ps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmadd231ps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmadd231ps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmadd231ps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmadd132sd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmadd132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmadd132sd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmadd213sd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmadd213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmadd213sd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmadd231sd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmadd231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmadd231sd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmadd132ss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmadd132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmadd132ss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmadd213ss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmadd213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmadd213ss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmadd231ss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmadd231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmadd231ss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmaddsub132pd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmaddsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmaddsub132pd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmaddsub132pd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmaddsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmaddsub132pd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmaddsub213pd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmaddsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmaddsub213pd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmaddsub213pd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmaddsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmaddsub213pd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmaddsub231pd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmaddsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmaddsub231pd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmaddsub231pd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmaddsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmaddsub231pd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmaddsub132ps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmaddsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmaddsub132ps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmaddsub132ps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmaddsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmaddsub132ps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmaddsub213ps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmaddsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmaddsub213ps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmaddsub213ps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmaddsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmaddsub213ps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmaddsub231ps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmaddsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmaddsub231ps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmaddsub231ps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmaddsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmaddsub231ps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmsub132pd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmsub132pd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmsub132pd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmsub132pd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmsub213pd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmsub213pd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmsub213pd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmsub213pd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmsub231pd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmsub231pd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmsub231pd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmsub231pd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmsub132ps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmsub132ps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmsub132ps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmsub132ps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmsub213ps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmsub213ps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmsub213ps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmsub213ps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmsub231ps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmsub231ps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmsub231ps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmsub231ps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmsub132sd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmsub132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmsub132sd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmsub213sd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmsub213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmsub213sd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmsub231sd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmsub231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmsub231sd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmsub132ss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmsub132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmsub132ss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmsub213ss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmsub213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmsub213ss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmsub231ss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmsub231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmsub231ss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmsubadd132pd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmsubadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmsubadd132pd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmsubadd132pd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmsubadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmsubadd132pd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmsubadd213pd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmsubadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmsubadd213pd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmsubadd213pd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmsubadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmsubadd213pd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmsubadd231pd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmsubadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmsubadd231pd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmsubadd231pd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmsubadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmsubadd231pd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmsubadd132ps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmsubadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmsubadd132ps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmsubadd132ps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmsubadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmsubadd132ps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmsubadd213ps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmsubadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmsubadd213ps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmsubadd213ps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmsubadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmsubadd213ps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfmsubadd231ps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfmsubadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfmsubadd231ps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfmsubadd231ps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfmsubadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfmsubadd231ps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfnmadd132pd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmadd132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmadd132pd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmadd132pd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfnmadd132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfnmadd132pd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfnmadd213pd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmadd213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmadd213pd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmadd213pd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfnmadd213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfnmadd213pd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfnmadd231pd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmadd231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmadd231pd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmadd231pd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfnmadd231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfnmadd231pd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfnmadd132ps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmadd132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmadd132ps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmadd132ps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfnmadd132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfnmadd132ps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfnmadd213ps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmadd213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmadd213ps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmadd213ps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfnmadd213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfnmadd213ps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfnmadd231ps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmadd231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmadd231ps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmadd231ps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfnmadd231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfnmadd231ps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfnmadd132sd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmadd132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmadd132sd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmadd213sd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmadd213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmadd213sd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmadd231sd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmadd231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmadd231sd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmadd132ss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmadd132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmadd132ss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmadd213ss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmadd213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmadd213ss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmadd231ss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmadd231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmadd231ss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmsub132pd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmsub132pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmsub132pd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmsub132pd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfnmsub132pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfnmsub132pd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfnmsub213pd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmsub213pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmsub213pd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmsub213pd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfnmsub213pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfnmsub213pd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfnmsub231pd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmsub231pd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmsub231pd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmsub231pd %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfnmsub231pd (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfnmsub231pd (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfnmsub132ps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmsub132ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmsub132ps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmsub132ps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfnmsub132ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfnmsub132ps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfnmsub213ps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmsub213ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmsub213ps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmsub213ps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfnmsub213ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfnmsub213ps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfnmsub231ps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmsub231ps (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmsub231ps (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmsub231ps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 2 12 0.50 * vfnmsub231ps (%rax), %ymm1, %ymm2
+# CHECK-NEXT: 2 11 0.50 * vfnmsub231ps (%rax), %ymm1, %ymm2
# CHECK-NEXT: 1 4 0.50 vfnmsub132sd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmsub132sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmsub132sd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmsub213sd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmsub213sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmsub213sd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmsub231sd %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmsub231sd (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmsub231sd (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmsub132ss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmsub132ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmsub132ss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmsub213ss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmsub213ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmsub213ss (%rax), %xmm1, %xmm2
# CHECK-NEXT: 1 4 0.50 vfnmsub231ss %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2 11 0.50 * vfnmsub231ss (%rax), %xmm1, %xmm2
+# CHECK-NEXT: 2 10 0.50 * vfnmsub231ss (%rax), %xmm1, %xmm2
# CHECK: Resources:
# CHECK-NEXT: [0] - ADLPPort00
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-lea.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-lea.s
index 762b6d3caef2..3238a570f372 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-lea.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-lea.s
@@ -148,141 +148,141 @@ lea 1024(%rax, %rbx, 2), %rcx
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 2 2 1.00 leaw 0, %cx
-# CHECK-NEXT: 1 1 1.00 leal 0, %ecx
-# CHECK-NEXT: 1 1 1.00 leaq 0, %rcx
-# CHECK-NEXT: 2 2 1.00 leaw (%eax), %cx
-# CHECK-NEXT: 1 1 1.00 leal (%eax), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq (%eax), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw (%rax), %cx
-# CHECK-NEXT: 1 1 1.00 leal (%rax), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq (%rax), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw (,%ebx), %cx
-# CHECK-NEXT: 1 1 1.00 leal (,%ebx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq (,%ebx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw (,%rbx), %cx
-# CHECK-NEXT: 1 1 1.00 leal (,%rbx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq (,%rbx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw (,%ebx), %cx
-# CHECK-NEXT: 1 1 1.00 leal (,%ebx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq (,%ebx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw (,%rbx), %cx
-# CHECK-NEXT: 1 1 1.00 leal (,%rbx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq (,%rbx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw (,%ebx,2), %cx
-# CHECK-NEXT: 1 1 1.00 leal (,%ebx,2), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq (,%ebx,2), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw (,%rbx,2), %cx
-# CHECK-NEXT: 1 1 1.00 leal (,%rbx,2), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq (,%rbx,2), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw (%eax,%ebx), %cx
-# CHECK-NEXT: 1 1 1.00 leal (%eax,%ebx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq (%eax,%ebx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw (%rax,%rbx), %cx
-# CHECK-NEXT: 1 1 1.00 leal (%rax,%rbx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq (%rax,%rbx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw (%eax,%ebx), %cx
-# CHECK-NEXT: 1 1 1.00 leal (%eax,%ebx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq (%eax,%ebx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw (%rax,%rbx), %cx
-# CHECK-NEXT: 1 1 1.00 leal (%rax,%rbx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq (%rax,%rbx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw (%eax,%ebx,2), %cx
-# CHECK-NEXT: 1 1 1.00 leal (%eax,%ebx,2), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq (%eax,%ebx,2), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw (%rax,%rbx,2), %cx
-# CHECK-NEXT: 1 1 1.00 leal (%rax,%rbx,2), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq (%rax,%rbx,2), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw -16, %cx
-# CHECK-NEXT: 1 1 1.00 leal -16, %ecx
-# CHECK-NEXT: 1 1 1.00 leaq -16, %rcx
-# CHECK-NEXT: 2 2 1.00 leaw -16(%eax), %cx
-# CHECK-NEXT: 1 1 1.00 leal -16(%eax), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq -16(%eax), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw -16(%rax), %cx
-# CHECK-NEXT: 1 1 1.00 leal -16(%rax), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq -16(%rax), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw -16(,%ebx), %cx
-# CHECK-NEXT: 1 1 1.00 leal -16(,%ebx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq -16(,%ebx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw -16(,%rbx), %cx
-# CHECK-NEXT: 1 1 1.00 leal -16(,%rbx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq -16(,%rbx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw -16(,%ebx), %cx
-# CHECK-NEXT: 1 1 1.00 leal -16(,%ebx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq -16(,%ebx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw -16(,%rbx), %cx
-# CHECK-NEXT: 1 1 1.00 leal -16(,%rbx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq -16(,%rbx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw -16(,%ebx,2), %cx
-# CHECK-NEXT: 1 1 1.00 leal -16(,%ebx,2), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq -16(,%ebx,2), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw -16(,%rbx,2), %cx
-# CHECK-NEXT: 1 1 1.00 leal -16(,%rbx,2), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq -16(,%rbx,2), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw -16(%eax,%ebx), %cx
-# CHECK-NEXT: 1 1 1.00 leal -16(%eax,%ebx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq -16(%eax,%ebx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw -16(%rax,%rbx), %cx
-# CHECK-NEXT: 1 1 1.00 leal -16(%rax,%rbx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq -16(%rax,%rbx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw -16(%eax,%ebx), %cx
-# CHECK-NEXT: 1 1 1.00 leal -16(%eax,%ebx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq -16(%eax,%ebx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw -16(%rax,%rbx), %cx
-# CHECK-NEXT: 1 1 1.00 leal -16(%rax,%rbx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq -16(%rax,%rbx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw -16(%eax,%ebx,2), %cx
-# CHECK-NEXT: 1 1 1.00 leal -16(%eax,%ebx,2), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq -16(%eax,%ebx,2), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw -16(%rax,%rbx,2), %cx
-# CHECK-NEXT: 1 1 1.00 leal -16(%rax,%rbx,2), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq -16(%rax,%rbx,2), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw 1024, %cx
-# CHECK-NEXT: 1 1 1.00 leal 1024, %ecx
-# CHECK-NEXT: 1 1 1.00 leaq 1024, %rcx
-# CHECK-NEXT: 2 2 1.00 leaw 1024(%eax), %cx
-# CHECK-NEXT: 1 1 1.00 leal 1024(%eax), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq 1024(%eax), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw 1024(%rax), %cx
-# CHECK-NEXT: 1 1 1.00 leal 1024(%rax), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq 1024(%rax), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw 1024(,%ebx), %cx
-# CHECK-NEXT: 1 1 1.00 leal 1024(,%ebx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq 1024(,%ebx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw 1024(,%rbx), %cx
-# CHECK-NEXT: 1 1 1.00 leal 1024(,%rbx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq 1024(,%rbx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw 1024(,%ebx), %cx
-# CHECK-NEXT: 1 1 1.00 leal 1024(,%ebx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq 1024(,%ebx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw 1024(,%rbx), %cx
-# CHECK-NEXT: 1 1 1.00 leal 1024(,%rbx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq 1024(,%rbx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw 1024(,%ebx,2), %cx
-# CHECK-NEXT: 1 1 1.00 leal 1024(,%ebx,2), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq 1024(,%ebx,2), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw 1024(,%rbx,2), %cx
-# CHECK-NEXT: 1 1 1.00 leal 1024(,%rbx,2), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq 1024(,%rbx,2), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw 1024(%eax,%ebx), %cx
-# CHECK-NEXT: 1 1 1.00 leal 1024(%eax,%ebx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq 1024(%eax,%ebx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw 1024(%rax,%rbx), %cx
-# CHECK-NEXT: 1 1 1.00 leal 1024(%rax,%rbx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq 1024(%rax,%rbx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw 1024(%eax,%ebx), %cx
-# CHECK-NEXT: 1 1 1.00 leal 1024(%eax,%ebx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq 1024(%eax,%ebx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw 1024(%rax,%rbx), %cx
-# CHECK-NEXT: 1 1 1.00 leal 1024(%rax,%rbx), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq 1024(%rax,%rbx), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw 1024(%eax,%ebx,2), %cx
-# CHECK-NEXT: 1 1 1.00 leal 1024(%eax,%ebx,2), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq 1024(%eax,%ebx,2), %rcx
-# CHECK-NEXT: 2 2 1.00 leaw 1024(%rax,%rbx,2), %cx
-# CHECK-NEXT: 1 1 1.00 leal 1024(%rax,%rbx,2), %ecx
-# CHECK-NEXT: 1 1 1.00 leaq 1024(%rax,%rbx,2), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw 0, %cx
+# CHECK-NEXT: 1 1 0.20 leal 0, %ecx
+# CHECK-NEXT: 1 1 0.20 leaq 0, %rcx
+# CHECK-NEXT: 2 2 0.40 leaw (%eax), %cx
+# CHECK-NEXT: 1 1 0.20 leal (%eax), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq (%eax), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw (%rax), %cx
+# CHECK-NEXT: 1 1 0.20 leal (%rax), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq (%rax), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw (,%ebx), %cx
+# CHECK-NEXT: 1 1 0.20 leal (,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq (,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw (,%rbx), %cx
+# CHECK-NEXT: 1 1 0.20 leal (,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq (,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw (,%ebx), %cx
+# CHECK-NEXT: 1 1 0.20 leal (,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq (,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw (,%rbx), %cx
+# CHECK-NEXT: 1 1 0.20 leal (,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq (,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw (,%ebx,2), %cx
+# CHECK-NEXT: 1 1 0.20 leal (,%ebx,2), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq (,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw (,%rbx,2), %cx
+# CHECK-NEXT: 1 1 0.20 leal (,%rbx,2), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq (,%rbx,2), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw (%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 0.20 leal (%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw (%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 0.20 leal (%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw (%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 0.20 leal (%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw (%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 0.20 leal (%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw (%eax,%ebx,2), %cx
+# CHECK-NEXT: 1 1 0.20 leal (%eax,%ebx,2), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq (%eax,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw (%rax,%rbx,2), %cx
+# CHECK-NEXT: 1 1 0.20 leal (%rax,%rbx,2), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq (%rax,%rbx,2), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw -16, %cx
+# CHECK-NEXT: 1 1 0.20 leal -16, %ecx
+# CHECK-NEXT: 1 1 0.20 leaq -16, %rcx
+# CHECK-NEXT: 2 2 0.40 leaw -16(%eax), %cx
+# CHECK-NEXT: 1 1 0.20 leal -16(%eax), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq -16(%eax), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw -16(%rax), %cx
+# CHECK-NEXT: 1 1 0.20 leal -16(%rax), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq -16(%rax), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw -16(,%ebx), %cx
+# CHECK-NEXT: 1 1 0.20 leal -16(,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq -16(,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw -16(,%rbx), %cx
+# CHECK-NEXT: 1 1 0.20 leal -16(,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq -16(,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw -16(,%ebx), %cx
+# CHECK-NEXT: 1 1 0.20 leal -16(,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq -16(,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw -16(,%rbx), %cx
+# CHECK-NEXT: 1 1 0.20 leal -16(,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq -16(,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw -16(,%ebx,2), %cx
+# CHECK-NEXT: 1 1 0.20 leal -16(,%ebx,2), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq -16(,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw -16(,%rbx,2), %cx
+# CHECK-NEXT: 1 1 0.20 leal -16(,%rbx,2), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq -16(,%rbx,2), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 0.20 leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 0.20 leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 0.20 leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 0.20 leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw -16(%eax,%ebx,2), %cx
+# CHECK-NEXT: 1 1 0.20 leal -16(%eax,%ebx,2), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq -16(%eax,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw -16(%rax,%rbx,2), %cx
+# CHECK-NEXT: 1 1 0.20 leal -16(%rax,%rbx,2), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq -16(%rax,%rbx,2), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw 1024, %cx
+# CHECK-NEXT: 1 1 0.20 leal 1024, %ecx
+# CHECK-NEXT: 1 1 0.20 leaq 1024, %rcx
+# CHECK-NEXT: 2 2 0.40 leaw 1024(%eax), %cx
+# CHECK-NEXT: 1 1 0.20 leal 1024(%eax), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq 1024(%eax), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw 1024(%rax), %cx
+# CHECK-NEXT: 1 1 0.20 leal 1024(%rax), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq 1024(%rax), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw 1024(,%ebx), %cx
+# CHECK-NEXT: 1 1 0.20 leal 1024(,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw 1024(,%rbx), %cx
+# CHECK-NEXT: 1 1 0.20 leal 1024(,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw 1024(,%ebx), %cx
+# CHECK-NEXT: 1 1 0.20 leal 1024(,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw 1024(,%rbx), %cx
+# CHECK-NEXT: 1 1 0.20 leal 1024(,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw 1024(,%ebx,2), %cx
+# CHECK-NEXT: 1 1 0.20 leal 1024(,%ebx,2), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq 1024(,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw 1024(,%rbx,2), %cx
+# CHECK-NEXT: 1 1 0.20 leal 1024(,%rbx,2), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq 1024(,%rbx,2), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 0.20 leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 0.20 leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: 1 1 0.20 leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: 1 1 0.20 leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw 1024(%eax,%ebx,2), %cx
+# CHECK-NEXT: 1 1 0.20 leal 1024(%eax,%ebx,2), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq 1024(%eax,%ebx,2), %rcx
+# CHECK-NEXT: 2 2 0.40 leaw 1024(%rax,%rbx,2), %cx
+# CHECK-NEXT: 1 1 0.20 leal 1024(%rax,%rbx,2), %ecx
+# CHECK-NEXT: 1 1 0.20 leaq 1024(%rax,%rbx,2), %rcx
# CHECK: Resources:
# CHECK-NEXT: [0] - ADLPPort00
@@ -301,142 +301,142 @@ lea 1024(%rax, %rbx, 2), %rcx
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
-# CHECK-NEXT: 9.00 144.00 - - - 9.00 9.00 - - - 9.00 - -
+# CHECK-NEXT: 36.00 36.00 - - - 36.00 36.00 - - - 36.00 - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 0, %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 0, %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 0, %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (%eax), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (%eax), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (%eax), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (%rax), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (%rax), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (%rax), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (,%ebx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (,%ebx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (,%ebx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (,%rbx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (,%rbx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (,%rbx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (,%ebx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (,%ebx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (,%ebx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (,%rbx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (,%rbx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (,%rbx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (,%ebx,2), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (,%ebx,2), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (,%ebx,2), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (,%rbx,2), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (,%rbx,2), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (,%rbx,2), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (%eax,%ebx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (%eax,%ebx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (%eax,%ebx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (%rax,%rbx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (%rax,%rbx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (%rax,%rbx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (%eax,%ebx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (%eax,%ebx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (%eax,%ebx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (%rax,%rbx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (%rax,%rbx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (%rax,%rbx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (%eax,%ebx,2), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (%eax,%ebx,2), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (%eax,%ebx,2), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw (%rax,%rbx,2), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal (%rax,%rbx,2), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq (%rax,%rbx,2), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16, %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16, %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16, %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(%eax), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(%eax), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(%eax), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(%rax), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(%rax), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(%rax), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(,%ebx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(,%ebx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(,%ebx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(,%rbx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(,%rbx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(,%rbx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(,%ebx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(,%ebx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(,%ebx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(,%rbx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(,%rbx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(,%rbx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(,%ebx,2), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(,%ebx,2), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(,%ebx,2), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(,%rbx,2), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(,%rbx,2), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(,%rbx,2), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(%eax,%ebx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(%eax,%ebx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(%eax,%ebx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(%rax,%rbx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(%rax,%rbx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(%rax,%rbx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(%eax,%ebx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(%eax,%ebx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(%eax,%ebx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(%rax,%rbx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(%rax,%rbx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(%rax,%rbx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(%eax,%ebx,2), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(%eax,%ebx,2), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(%eax,%ebx,2), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw -16(%rax,%rbx,2), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal -16(%rax,%rbx,2), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq -16(%rax,%rbx,2), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024, %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024, %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024, %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(%eax), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(%eax), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(%eax), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(%rax), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(%rax), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(%rax), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(,%ebx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(,%ebx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(,%ebx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(,%rbx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(,%rbx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(,%rbx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(,%ebx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(,%ebx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(,%ebx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(,%rbx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(,%rbx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(,%rbx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(,%ebx,2), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(,%ebx,2), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(,%ebx,2), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(,%rbx,2), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(,%rbx,2), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(,%rbx,2), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(%eax,%ebx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(%eax,%ebx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(%eax,%ebx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(%rax,%rbx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(%rax,%rbx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(%rax,%rbx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(%eax,%ebx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(%eax,%ebx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(%eax,%ebx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(%rax,%rbx), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(%rax,%rbx), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(%rax,%rbx), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(%eax,%ebx,2), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(%eax,%ebx,2), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(%eax,%ebx,2), %rcx
-# CHECK-NEXT: 0.20 1.20 - - - 0.20 0.20 - - - 0.20 - - leaw 1024(%rax,%rbx,2), %cx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leal 1024(%rax,%rbx,2), %ecx
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - leaq 1024(%rax,%rbx,2), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw 0, %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal 0, %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq 0, %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw (%eax), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal (%eax), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq (%eax), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw (%rax), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal (%rax), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq (%rax), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw (,%ebx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal (,%ebx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq (,%ebx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw (,%rbx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal (,%rbx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq (,%rbx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw (,%ebx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal (,%ebx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq (,%ebx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw (,%rbx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal (,%rbx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq (,%rbx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw (,%ebx,2), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal (,%ebx,2), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq (,%ebx,2), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw (,%rbx,2), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal (,%rbx,2), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq (,%rbx,2), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw (%eax,%ebx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal (%eax,%ebx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw (%rax,%rbx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal (%rax,%rbx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw (%eax,%ebx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal (%eax,%ebx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq (%eax,%ebx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw (%rax,%rbx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal (%rax,%rbx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq (%rax,%rbx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw (%eax,%ebx,2), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal (%eax,%ebx,2), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq (%eax,%ebx,2), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw (%rax,%rbx,2), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal (%rax,%rbx,2), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq (%rax,%rbx,2), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw -16, %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal -16, %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq -16, %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw -16(%eax), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal -16(%eax), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq -16(%eax), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw -16(%rax), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal -16(%rax), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq -16(%rax), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw -16(,%ebx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal -16(,%ebx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq -16(,%ebx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw -16(,%rbx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal -16(,%rbx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq -16(,%rbx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw -16(,%ebx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal -16(,%ebx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq -16(,%ebx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw -16(,%rbx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal -16(,%rbx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq -16(,%rbx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw -16(,%ebx,2), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal -16(,%ebx,2), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq -16(,%ebx,2), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw -16(,%rbx,2), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal -16(,%rbx,2), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq -16(,%rbx,2), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw -16(%eax,%ebx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal -16(%eax,%ebx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq -16(%eax,%ebx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw -16(%rax,%rbx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal -16(%rax,%rbx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq -16(%rax,%rbx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw -16(%eax,%ebx,2), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal -16(%eax,%ebx,2), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq -16(%eax,%ebx,2), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw -16(%rax,%rbx,2), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal -16(%rax,%rbx,2), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq -16(%rax,%rbx,2), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw 1024, %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal 1024, %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq 1024, %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw 1024(%eax), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal 1024(%eax), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq 1024(%eax), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw 1024(%rax), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal 1024(%rax), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq 1024(%rax), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw 1024(,%ebx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal 1024(,%ebx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw 1024(,%rbx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal 1024(,%rbx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw 1024(,%ebx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal 1024(,%ebx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq 1024(,%ebx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw 1024(,%rbx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal 1024(,%rbx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq 1024(,%rbx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw 1024(,%ebx,2), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal 1024(,%ebx,2), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq 1024(,%ebx,2), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw 1024(,%rbx,2), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal 1024(,%rbx,2), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq 1024(,%rbx,2), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw 1024(%eax,%ebx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal 1024(%eax,%ebx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq 1024(%eax,%ebx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw 1024(%rax,%rbx), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal 1024(%rax,%rbx), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq 1024(%rax,%rbx), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw 1024(%eax,%ebx,2), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal 1024(%eax,%ebx,2), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq 1024(%eax,%ebx,2), %rcx
+# CHECK-NEXT: 0.40 0.40 - - - 0.40 0.40 - - - 0.40 - - leaw 1024(%rax,%rbx,2), %cx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leal 1024(%rax,%rbx,2), %ecx
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - leaq 1024(%rax,%rbx,2), %rcx
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-mmx.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-mmx.s
index c62ea2963323..689184293936 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-mmx.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-mmx.s
@@ -165,50 +165,50 @@ pxor (%rax), %mm2
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 10 10 4.50 * * U emms
-# CHECK-NEXT: 1 3 1.00 movd %eax, %mm2
-# CHECK-NEXT: 1 8 0.33 * movd (%rax), %mm2
+# CHECK-NEXT: 1 1 1.00 movd %eax, %mm2
+# CHECK-NEXT: 1 6 0.33 * movd (%rax), %mm2
# CHECK-NEXT: 1 3 1.00 movd %mm0, %ecx
-# CHECK-NEXT: 2 18 0.50 * U movd %mm0, (%rax)
-# CHECK-NEXT: 1 3 1.00 movq %rax, %mm2
-# CHECK-NEXT: 1 8 0.33 * movq (%rax), %mm2
+# CHECK-NEXT: 2 1 0.50 * U movd %mm0, (%rax)
+# CHECK-NEXT: 1 1 1.00 movq %rax, %mm2
+# CHECK-NEXT: 1 6 0.33 * movq (%rax), %mm2
# CHECK-NEXT: 1 3 1.00 movq %mm0, %rcx
-# CHECK-NEXT: 2 12 0.50 * movq %mm0, (%rax)
-# CHECK-NEXT: 2 4 2.00 packsswb %mm0, %mm2
-# CHECK-NEXT: 3 12 2.00 * packsswb (%rax), %mm2
-# CHECK-NEXT: 2 4 2.00 packssdw %mm0, %mm2
-# CHECK-NEXT: 3 12 2.00 * packssdw (%rax), %mm2
-# CHECK-NEXT: 2 4 2.00 packuswb %mm0, %mm2
-# CHECK-NEXT: 3 12 2.00 * packuswb (%rax), %mm2
+# CHECK-NEXT: 2 1 0.50 * movq %mm0, (%rax)
+# CHECK-NEXT: 3 4 2.00 packsswb %mm0, %mm2
+# CHECK-NEXT: 3 10 2.00 * packsswb (%rax), %mm2
+# CHECK-NEXT: 3 4 2.00 packssdw %mm0, %mm2
+# CHECK-NEXT: 3 10 2.00 * packssdw (%rax), %mm2
+# CHECK-NEXT: 3 4 2.00 packuswb %mm0, %mm2
+# CHECK-NEXT: 3 10 2.00 * packuswb (%rax), %mm2
# CHECK-NEXT: 1 1 0.50 paddb %mm0, %mm2
-# CHECK-NEXT: 2 9 0.50 * paddb (%rax), %mm2
+# CHECK-NEXT: 2 7 0.50 * paddb (%rax), %mm2
# CHECK-NEXT: 1 1 0.50 paddd %mm0, %mm2
-# CHECK-NEXT: 2 9 0.50 * paddd (%rax), %mm2
+# CHECK-NEXT: 2 7 0.50 * paddd (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 paddsb %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * paddsb (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * paddsb (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 paddsw %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * paddsw (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * paddsw (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 paddusb %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * paddusb (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * paddusb (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 paddusw %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * paddusw (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * paddusw (%rax), %mm2
# CHECK-NEXT: 1 1 0.50 paddw %mm0, %mm2
-# CHECK-NEXT: 2 9 0.50 * paddw (%rax), %mm2
+# CHECK-NEXT: 2 7 0.50 * paddw (%rax), %mm2
# CHECK-NEXT: 1 1 0.50 pand %mm0, %mm2
-# CHECK-NEXT: 2 9 0.50 * pand (%rax), %mm2
+# CHECK-NEXT: 2 7 0.50 * pand (%rax), %mm2
# CHECK-NEXT: 1 1 0.50 pandn %mm0, %mm2
-# CHECK-NEXT: 2 9 0.50 * pandn (%rax), %mm2
+# CHECK-NEXT: 2 7 0.50 * pandn (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 pcmpeqb %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * pcmpeqb (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * pcmpeqb (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 pcmpeqd %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * pcmpeqd (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * pcmpeqd (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 pcmpeqw %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * pcmpeqw (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * pcmpeqw (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 pcmpgtb %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * pcmpgtb (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * pcmpgtb (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 pcmpgtd %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * pcmpgtd (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * pcmpgtd (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 pcmpgtw %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * pcmpgtw (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * pcmpgtw (%rax), %mm2
# CHECK-NEXT: 1 5 1.00 pmaddwd %mm0, %mm2
# CHECK-NEXT: 2 13 1.00 * pmaddwd (%rax), %mm2
# CHECK-NEXT: 1 5 1.00 pmulhw %mm0, %mm2
@@ -216,59 +216,59 @@ pxor (%rax), %mm2
# CHECK-NEXT: 1 5 1.00 pmullw %mm0, %mm2
# CHECK-NEXT: 2 13 1.00 * pmullw (%rax), %mm2
# CHECK-NEXT: 1 1 0.50 por %mm0, %mm2
-# CHECK-NEXT: 2 9 0.50 * por (%rax), %mm2
+# CHECK-NEXT: 2 7 0.50 * por (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 pslld $1, %mm2
# CHECK-NEXT: 1 1 1.00 pslld %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * pslld (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * pslld (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 psllq $1, %mm2
# CHECK-NEXT: 1 1 1.00 psllq %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * psllq (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * psllq (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 psllw $1, %mm2
# CHECK-NEXT: 1 1 1.00 psllw %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * psllw (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * psllw (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 psrad $1, %mm2
# CHECK-NEXT: 1 1 1.00 psrad %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * psrad (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * psrad (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 psraw $1, %mm2
# CHECK-NEXT: 1 1 1.00 psraw %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * psraw (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * psraw (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 psrld $1, %mm2
# CHECK-NEXT: 1 1 1.00 psrld %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * psrld (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * psrld (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 psrlq $1, %mm2
# CHECK-NEXT: 1 1 1.00 psrlq %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * psrlq (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * psrlq (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 psrlw $1, %mm2
# CHECK-NEXT: 1 1 1.00 psrlw %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * psrlw (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * psrlw (%rax), %mm2
# CHECK-NEXT: 1 1 0.50 psubb %mm0, %mm2
-# CHECK-NEXT: 2 9 0.50 * psubb (%rax), %mm2
+# CHECK-NEXT: 2 7 0.50 * psubb (%rax), %mm2
# CHECK-NEXT: 1 1 0.50 psubd %mm0, %mm2
-# CHECK-NEXT: 2 9 0.50 * psubd (%rax), %mm2
+# CHECK-NEXT: 2 7 0.50 * psubd (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 psubsb %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * psubsb (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * psubsb (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 psubsw %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * psubsw (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * psubsw (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 psubusb %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * psubusb (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * psubusb (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 psubusw %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * psubusw (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * psubusw (%rax), %mm2
# CHECK-NEXT: 1 1 0.50 psubw %mm0, %mm2
-# CHECK-NEXT: 2 9 0.50 * psubw (%rax), %mm2
+# CHECK-NEXT: 2 7 0.50 * psubw (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 punpckhbw %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * punpckhbw (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * punpckhbw (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 punpckhdq %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * punpckhdq (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * punpckhdq (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 punpckhwd %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * punpckhwd (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * punpckhwd (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 punpcklbw %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * punpcklbw (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * punpcklbw (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 punpckldq %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * punpckldq (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * punpckldq (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 punpcklwd %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * punpcklwd (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * punpcklwd (%rax), %mm2
# CHECK-NEXT: 1 1 0.50 pxor %mm0, %mm2
-# CHECK-NEXT: 2 9 0.50 * pxor (%rax), %mm2
+# CHECK-NEXT: 2 7 0.50 * pxor (%rax), %mm2
# CHECK: Resources:
# CHECK-NEXT: [0] - ADLPPort00
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-pclmul.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-pclmul.s
index 871035dbe34a..e79f9b7c0e64 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-pclmul.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-pclmul.s
@@ -14,7 +14,7 @@ pclmulqdq $11, (%rax), %xmm2
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 pclmulqdq $11, %xmm0, %xmm2
-# CHECK-NEXT: 2 10 1.00 * pclmulqdq $11, (%rax), %xmm2
+# CHECK-NEXT: 2 9 1.00 * pclmulqdq $11, (%rax), %xmm2
# CHECK: Resources:
# CHECK-NEXT: [0] - ADLPPort00
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse1.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse1.s
index b292826913d9..8ca990b185a1 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse1.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse1.s
@@ -196,89 +196,89 @@ xorps (%rax), %xmm2
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 0.50 addps %xmm0, %xmm2
# CHECK-NEXT: 2 10 0.50 * addps (%rax), %xmm2
-# CHECK-NEXT: 1 3 0.50 addss %xmm0, %xmm2
-# CHECK-NEXT: 2 10 0.50 * addss (%rax), %xmm2
+# CHECK-NEXT: 1 2 0.50 addss %xmm0, %xmm2
+# CHECK-NEXT: 2 9 0.50 * addss (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 andnps %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.33 * andnps (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.33 * andnps (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 andps %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.33 * andps (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.33 * andps (%rax), %xmm2
# CHECK-NEXT: 1 4 0.50 cmpeqps %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * cmpeqps (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * cmpeqps (%rax), %xmm2
# CHECK-NEXT: 1 4 0.50 cmpeqss %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * cmpeqss (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * cmpeqss (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 comiss %xmm0, %xmm1
-# CHECK-NEXT: 2 8 1.00 * comiss (%rax), %xmm1
-# CHECK-NEXT: 2 7 1.00 cvtpi2ps %mm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * cvtpi2ps (%rax), %xmm2
+# CHECK-NEXT: 2 9 1.00 * comiss (%rax), %xmm1
+# CHECK-NEXT: 2 6 1.00 cvtpi2ps %mm0, %xmm2
+# CHECK-NEXT: 2 10 0.50 * cvtpi2ps (%rax), %xmm2
# CHECK-NEXT: 2 9 1.00 cvtps2pi %xmm0, %mm2
-# CHECK-NEXT: 2 13 1.00 * cvtps2pi (%rax), %mm2
-# CHECK-NEXT: 2 7 1.00 cvtsi2ss %ecx, %xmm2
-# CHECK-NEXT: 3 8 2.00 cvtsi2ss %rcx, %xmm2
-# CHECK-NEXT: 2 11 0.50 * cvtsi2ssl (%rax), %xmm2
-# CHECK-NEXT: 2 11 0.50 * cvtsi2ssl (%rax), %xmm2
+# CHECK-NEXT: 2 11 1.00 * cvtps2pi (%rax), %mm2
+# CHECK-NEXT: 2 5 1.00 cvtsi2ss %ecx, %xmm2
+# CHECK-NEXT: 3 6 2.00 cvtsi2ss %rcx, %xmm2
+# CHECK-NEXT: 2 10 0.50 * cvtsi2ssl (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * cvtsi2ssl (%rax), %xmm2
# CHECK-NEXT: 2 7 1.00 cvtss2si %xmm0, %ecx
# CHECK-NEXT: 3 8 1.00 cvtss2si %xmm0, %rcx
# CHECK-NEXT: 3 12 1.00 * cvtss2si (%rax), %ecx
# CHECK-NEXT: 3 12 1.00 * cvtss2si (%rax), %rcx
# CHECK-NEXT: 2 9 1.00 cvttps2pi %xmm0, %mm2
-# CHECK-NEXT: 2 13 1.00 * cvttps2pi (%rax), %mm2
+# CHECK-NEXT: 2 11 1.00 * cvttps2pi (%rax), %mm2
# CHECK-NEXT: 2 7 1.00 cvttss2si %xmm0, %ecx
# CHECK-NEXT: 3 8 1.00 cvttss2si %xmm0, %rcx
# CHECK-NEXT: 3 12 1.00 * cvttss2si (%rax), %ecx
# CHECK-NEXT: 3 12 1.00 * cvttss2si (%rax), %rcx
# CHECK-NEXT: 1 11 1.00 divps %xmm0, %xmm2
-# CHECK-NEXT: 2 18 1.00 * divps (%rax), %xmm2
+# CHECK-NEXT: 2 17 1.00 * divps (%rax), %xmm2
# CHECK-NEXT: 1 11 1.00 divss %xmm0, %xmm2
-# CHECK-NEXT: 2 18 1.00 * divss (%rax), %xmm2
+# CHECK-NEXT: 2 17 1.00 * divss (%rax), %xmm2
# CHECK-NEXT: 4 7 1.00 * * U ldmxcsr (%rax)
# CHECK-NEXT: 4 12 2.00 * * U maskmovq %mm0, %mm1
# CHECK-NEXT: 1 4 0.50 maxps %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * maxps (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * maxps (%rax), %xmm2
# CHECK-NEXT: 1 4 0.50 maxss %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * maxss (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * maxss (%rax), %xmm2
# CHECK-NEXT: 1 4 0.50 minps %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * minps (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * minps (%rax), %xmm2
# CHECK-NEXT: 1 4 0.50 minss %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * minss (%rax), %xmm2
-# CHECK-NEXT: 0 1 0.00 movaps %xmm0, %xmm2
-# CHECK-NEXT: 2 12 0.50 * movaps %xmm0, (%rax)
-# CHECK-NEXT: 1 7 0.33 * movaps (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * minss (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.33 movaps %xmm0, %xmm2
+# CHECK-NEXT: 2 1 0.50 * movaps %xmm0, (%rax)
+# CHECK-NEXT: 1 6 0.33 * movaps (%rax), %xmm2
# CHECK-NEXT: 1 1 1.00 movhlps %xmm0, %xmm2
# CHECK-NEXT: 1 1 1.00 movlhps %xmm0, %xmm2
-# CHECK-NEXT: 2 12 0.50 * movhps %xmm0, (%rax)
-# CHECK-NEXT: 2 8 1.00 * movhps (%rax), %xmm2
+# CHECK-NEXT: 2 1 0.50 * movhps %xmm0, (%rax)
+# CHECK-NEXT: 2 7 1.00 * movhps (%rax), %xmm2
# CHECK-NEXT: 2 12 0.50 * movlps %xmm0, (%rax)
-# CHECK-NEXT: 2 8 0.50 * movlps (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * movlps (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 movmskps %xmm0, %ecx
# CHECK-NEXT: 2 518 0.50 * movntps %xmm0, (%rax)
# CHECK-NEXT: 2 511 0.50 * * U movntq %mm0, (%rax)
# CHECK-NEXT: 1 1 0.33 movss %xmm0, %xmm2
-# CHECK-NEXT: 2 12 0.50 * movss %xmm0, (%rax)
-# CHECK-NEXT: 1 7 0.33 * movss (%rax), %xmm2
-# CHECK-NEXT: 0 1 0.00 movups %xmm0, %xmm2
-# CHECK-NEXT: 2 12 0.50 * movups %xmm0, (%rax)
-# CHECK-NEXT: 1 7 0.33 * movups (%rax), %xmm2
+# CHECK-NEXT: 2 1 0.50 * movss %xmm0, (%rax)
+# CHECK-NEXT: 1 6 0.33 * movss (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.33 movups %xmm0, %xmm2
+# CHECK-NEXT: 2 1 0.50 * movups %xmm0, (%rax)
+# CHECK-NEXT: 1 6 0.33 * movups (%rax), %xmm2
# CHECK-NEXT: 1 4 0.50 mulps %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * mulps (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * mulps (%rax), %xmm2
# CHECK-NEXT: 1 4 0.50 mulss %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * mulss (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * mulss (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 orps %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.33 * orps (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.33 * orps (%rax), %xmm2
# CHECK-NEXT: 1 1 1.00 pavgb %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * pavgb (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * pavgb (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 pavgw %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * pavgw (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * pavgw (%rax), %mm2
# CHECK-NEXT: 2 4 1.00 pextrw $1, %mm0, %ecx
-# CHECK-NEXT: 2 4 2.00 pinsrw $1, %eax, %mm2
-# CHECK-NEXT: 2 9 1.00 * pinsrw $1, (%rax), %mm2
+# CHECK-NEXT: 2 2 2.00 pinsrw $1, %eax, %mm2
+# CHECK-NEXT: 2 7 1.00 * pinsrw $1, (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 pmaxsw %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * pmaxsw (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * pmaxsw (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 pmaxub %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * pmaxub (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * pmaxub (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 pminsw %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * pminsw (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * pminsw (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 pminub %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * pminub (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * pminub (%rax), %mm2
# CHECK-NEXT: 1 3 1.00 pmovmskb %mm0, %ecx
# CHECK-NEXT: 1 5 1.00 pmulhuw %mm0, %mm2
# CHECK-NEXT: 2 13 1.00 * pmulhuw (%rax), %mm2
@@ -287,37 +287,37 @@ xorps (%rax), %xmm2
# CHECK-NEXT: 1 0 0.33 * * prefetcht2 (%rax)
# CHECK-NEXT: 1 0 0.33 * * prefetchnta (%rax)
# CHECK-NEXT: 1 3 1.00 psadbw %mm0, %mm2
-# CHECK-NEXT: 2 11 1.00 * psadbw (%rax), %mm2
+# CHECK-NEXT: 2 9 1.00 * psadbw (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 pshufw $1, %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * pshufw $1, (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * pshufw $1, (%rax), %mm2
# CHECK-NEXT: 1 4 1.00 rcpps %xmm0, %xmm2
-# CHECK-NEXT: 2 11 1.00 * rcpps (%rax), %xmm2
+# CHECK-NEXT: 2 10 1.00 * rcpps (%rax), %xmm2
# CHECK-NEXT: 1 4 1.00 rcpss %xmm0, %xmm2
-# CHECK-NEXT: 2 11 1.00 * rcpss (%rax), %xmm2
+# CHECK-NEXT: 2 10 1.00 * rcpss (%rax), %xmm2
# CHECK-NEXT: 1 4 1.00 rsqrtps %xmm0, %xmm2
-# CHECK-NEXT: 2 11 1.00 * rsqrtps (%rax), %xmm2
+# CHECK-NEXT: 2 10 1.00 * rsqrtps (%rax), %xmm2
# CHECK-NEXT: 1 4 1.00 rsqrtss %xmm0, %xmm2
-# CHECK-NEXT: 2 11 1.00 * rsqrtss (%rax), %xmm2
+# CHECK-NEXT: 2 10 1.00 * rsqrtss (%rax), %xmm2
# CHECK-NEXT: 2 2 0.50 * * U sfence
# CHECK-NEXT: 1 1 0.50 shufps $1, %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * shufps $1, (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * shufps $1, (%rax), %xmm2
# CHECK-NEXT: 1 12 1.00 sqrtps %xmm0, %xmm2
-# CHECK-NEXT: 2 19 1.00 * sqrtps (%rax), %xmm2
+# CHECK-NEXT: 2 18 1.00 * sqrtps (%rax), %xmm2
# CHECK-NEXT: 1 12 1.00 sqrtss %xmm0, %xmm2
-# CHECK-NEXT: 2 19 1.00 * sqrtss (%rax), %xmm2
+# CHECK-NEXT: 2 18 1.00 * sqrtss (%rax), %xmm2
# CHECK-NEXT: 4 12 1.00 * U stmxcsr (%rax)
# CHECK-NEXT: 1 3 0.50 subps %xmm0, %xmm2
# CHECK-NEXT: 2 10 0.50 * subps (%rax), %xmm2
-# CHECK-NEXT: 1 3 0.50 subss %xmm0, %xmm2
-# CHECK-NEXT: 2 10 0.50 * subss (%rax), %xmm2
+# CHECK-NEXT: 1 2 0.50 subss %xmm0, %xmm2
+# CHECK-NEXT: 2 9 0.50 * subss (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 ucomiss %xmm0, %xmm1
-# CHECK-NEXT: 2 8 1.00 * ucomiss (%rax), %xmm1
+# CHECK-NEXT: 2 9 1.00 * ucomiss (%rax), %xmm1
# CHECK-NEXT: 1 1 1.00 unpckhps %xmm0, %xmm2
-# CHECK-NEXT: 2 8 1.00 * unpckhps (%rax), %xmm2
+# CHECK-NEXT: 2 7 1.00 * unpckhps (%rax), %xmm2
# CHECK-NEXT: 1 1 1.00 unpcklps %xmm0, %xmm2
-# CHECK-NEXT: 2 8 1.00 * unpcklps (%rax), %xmm2
+# CHECK-NEXT: 2 7 1.00 * unpcklps (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 xorps %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.33 * xorps (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.33 * xorps (%rax), %xmm2
# CHECK: Resources:
# CHECK-NEXT: [0] - ADLPPort00
@@ -336,7 +336,7 @@ xorps (%rax), %xmm2
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
-# CHECK-NEXT: 74.00 24.50 19.33 19.33 5.00 29.50 1.00 5.00 5.00 5.00 - 19.33 -
+# CHECK-NEXT: 73.67 25.17 19.33 19.33 5.00 30.17 2.00 5.00 5.00 5.00 - 19.33 -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
@@ -376,7 +376,7 @@ xorps (%rax), %xmm2
# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - divps (%rax), %xmm2
# CHECK-NEXT: 1.00 - - - - - - - - - - - - divss %xmm0, %xmm2
# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - divss (%rax), %xmm2
-# CHECK-NEXT: 1.83 0.33 0.33 0.33 - 0.33 0.50 - - - - 0.33 - ldmxcsr (%rax)
+# CHECK-NEXT: 1.33 0.33 0.33 0.33 - 0.33 1.00 - - - - 0.33 - ldmxcsr (%rax)
# CHECK-NEXT: 2.00 - - - 0.50 - - 0.50 0.50 0.50 - - - maskmovq %mm0, %mm1
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - maxps %xmm0, %xmm2
# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - maxps (%rax), %xmm2
@@ -386,7 +386,7 @@ xorps (%rax), %xmm2
# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - minps (%rax), %xmm2
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - minss %xmm0, %xmm2
# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - minss (%rax), %xmm2
-# CHECK-NEXT: - - - - - - - - - - - - - movaps %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - movaps %xmm0, %xmm2
# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movaps %xmm0, (%rax)
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movaps (%rax), %xmm2
# CHECK-NEXT: - - - - - 1.00 - - - - - - - movhlps %xmm0, %xmm2
@@ -401,7 +401,7 @@ xorps (%rax), %xmm2
# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - movss %xmm0, %xmm2
# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movss %xmm0, (%rax)
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movss (%rax), %xmm2
-# CHECK-NEXT: - - - - - - - - - - - - - movups %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - movups %xmm0, %xmm2
# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movups %xmm0, (%rax)
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movups (%rax), %xmm2
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - mulps %xmm0, %xmm2
@@ -451,7 +451,7 @@ xorps (%rax), %xmm2
# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - sqrtps (%rax), %xmm2
# CHECK-NEXT: 1.00 - - - - - - - - - - - - sqrtss %xmm0, %xmm2
# CHECK-NEXT: 1.00 - 0.33 0.33 - - - - - - - 0.33 - sqrtss (%rax), %xmm2
-# CHECK-NEXT: 1.50 - - - 0.50 - 0.50 0.50 0.50 0.50 - - - stmxcsr (%rax)
+# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - stmxcsr (%rax)
# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - subps %xmm0, %xmm2
# CHECK-NEXT: - 0.50 0.33 0.33 - 0.50 - - - - - 0.33 - subps (%rax), %xmm2
# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - subss %xmm0, %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse2.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse2.s
index 964caa1d7f73..415089499bd5 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse2.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse2.s
@@ -407,58 +407,58 @@ xorpd (%rax), %xmm2
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 3 0.50 addpd %xmm0, %xmm2
-# CHECK-NEXT: 2 10 0.50 * addpd (%rax), %xmm2
-# CHECK-NEXT: 1 3 0.50 addsd %xmm0, %xmm2
-# CHECK-NEXT: 2 10 0.50 * addsd (%rax), %xmm2
+# CHECK-NEXT: 1 2 0.50 addpd %xmm0, %xmm2
+# CHECK-NEXT: 2 9 0.50 * addpd (%rax), %xmm2
+# CHECK-NEXT: 1 2 0.50 addsd %xmm0, %xmm2
+# CHECK-NEXT: 2 9 0.50 * addsd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 andnpd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.33 * andnpd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.33 * andnpd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 andpd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.33 * andpd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.33 * andpd (%rax), %xmm2
# CHECK-NEXT: 4 2 0.50 * * U clflush (%rax)
# CHECK-NEXT: 1 4 0.50 cmpeqpd %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * cmpeqpd (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * cmpeqpd (%rax), %xmm2
# CHECK-NEXT: 1 4 0.50 cmpeqsd %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * cmpeqsd (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * cmpeqsd (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 comisd %xmm0, %xmm1
-# CHECK-NEXT: 2 8 1.00 * comisd (%rax), %xmm1
+# CHECK-NEXT: 2 9 1.00 * comisd (%rax), %xmm1
# CHECK-NEXT: 2 5 1.00 cvtdq2pd %xmm0, %xmm2
# CHECK-NEXT: 2 11 0.50 * cvtdq2pd (%rax), %xmm2
# CHECK-NEXT: 1 4 0.50 cvtdq2ps %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * cvtdq2ps (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * cvtdq2ps (%rax), %xmm2
# CHECK-NEXT: 2 5 1.00 cvtpd2dq %xmm0, %xmm2
# CHECK-NEXT: 3 12 1.00 * cvtpd2dq (%rax), %xmm2
# CHECK-NEXT: 2 8 1.00 cvtpd2pi %xmm0, %mm2
-# CHECK-NEXT: 3 24 1.00 * cvtpd2pi (%rax), %mm2
+# CHECK-NEXT: 3 11 1.00 * cvtpd2pi (%rax), %mm2
# CHECK-NEXT: 2 5 1.00 cvtpd2ps %xmm0, %xmm2
# CHECK-NEXT: 3 12 1.00 * cvtpd2ps (%rax), %xmm2
# CHECK-NEXT: 2 6 1.00 cvtpi2pd %mm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * cvtpi2pd (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * cvtpi2pd (%rax), %xmm2
# CHECK-NEXT: 1 4 0.50 cvtps2dq %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * cvtps2dq (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * cvtps2dq (%rax), %xmm2
# CHECK-NEXT: 2 5 1.00 cvtps2pd %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * cvtps2pd (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * cvtps2pd (%rax), %xmm2
# CHECK-NEXT: 2 7 1.00 cvtsd2si %xmm0, %ecx
# CHECK-NEXT: 2 7 1.00 cvtsd2si %xmm0, %rcx
-# CHECK-NEXT: 3 26 1.00 * cvtsd2si (%rax), %ecx
+# CHECK-NEXT: 3 12 1.00 * cvtsd2si (%rax), %ecx
# CHECK-NEXT: 3 12 1.00 * cvtsd2si (%rax), %rcx
# CHECK-NEXT: 2 5 1.00 cvtsd2ss %xmm0, %xmm2
-# CHECK-NEXT: 3 12 1.00 * cvtsd2ss (%rax), %xmm2
-# CHECK-NEXT: 2 7 1.00 cvtsi2sd %ecx, %xmm2
-# CHECK-NEXT: 2 7 1.00 cvtsi2sd %rcx, %xmm2
-# CHECK-NEXT: 2 11 0.50 * cvtsi2sdl (%rax), %xmm2
-# CHECK-NEXT: 2 11 0.50 * cvtsi2sdl (%rax), %xmm2
+# CHECK-NEXT: 3 11 1.00 * cvtsd2ss (%rax), %xmm2
+# CHECK-NEXT: 2 5 1.00 cvtsi2sd %ecx, %xmm2
+# CHECK-NEXT: 2 5 1.00 cvtsi2sd %rcx, %xmm2
+# CHECK-NEXT: 2 10 0.50 * cvtsi2sdl (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * cvtsi2sdl (%rax), %xmm2
# CHECK-NEXT: 2 5 1.00 cvtss2sd %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * cvtss2sd (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * cvtss2sd (%rax), %xmm2
# CHECK-NEXT: 2 5 1.00 cvttpd2dq %xmm0, %xmm2
# CHECK-NEXT: 3 12 1.00 * cvttpd2dq (%rax), %xmm2
# CHECK-NEXT: 2 8 1.00 cvttpd2pi %xmm0, %mm2
-# CHECK-NEXT: 3 24 1.00 * cvttpd2pi (%rax), %mm2
+# CHECK-NEXT: 3 11 1.00 * cvttpd2pi (%rax), %mm2
# CHECK-NEXT: 1 4 0.50 cvttps2dq %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * cvttps2dq (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * cvttps2dq (%rax), %xmm2
# CHECK-NEXT: 2 7 1.00 cvttsd2si %xmm0, %ecx
# CHECK-NEXT: 2 7 1.00 cvttsd2si %xmm0, %rcx
-# CHECK-NEXT: 3 26 1.00 * cvttsd2si (%rax), %ecx
+# CHECK-NEXT: 3 12 1.00 * cvttsd2si (%rax), %ecx
# CHECK-NEXT: 3 12 1.00 * cvttsd2si (%rax), %rcx
# CHECK-NEXT: 1 14 1.00 divpd %xmm0, %xmm2
# CHECK-NEXT: 2 20 1.00 * divpd (%rax), %xmm2
@@ -467,213 +467,213 @@ xorpd (%rax), %xmm2
# CHECK-NEXT: 1 2 0.50 * * U lfence
# CHECK-NEXT: 2 1 1.00 * * U maskmovdqu %xmm0, %xmm1
# CHECK-NEXT: 1 4 0.50 maxpd %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * maxpd (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * maxpd (%rax), %xmm2
# CHECK-NEXT: 1 4 0.50 maxsd %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * maxsd (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * maxsd (%rax), %xmm2
# CHECK-NEXT: 2 3 0.50 * * U mfence
# CHECK-NEXT: 1 4 0.50 minpd %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * minpd (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * minpd (%rax), %xmm2
# CHECK-NEXT: 1 4 0.50 minsd %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * minsd (%rax), %xmm2
-# CHECK-NEXT: 0 1 0.00 movapd %xmm0, %xmm2
-# CHECK-NEXT: 2 12 0.50 * movapd %xmm0, (%rax)
-# CHECK-NEXT: 1 7 0.33 * movapd (%rax), %xmm2
-# CHECK-NEXT: 1 3 1.00 movd %eax, %xmm2
-# CHECK-NEXT: 1 7 0.33 * movd (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * minsd (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.33 movapd %xmm0, %xmm2
+# CHECK-NEXT: 2 1 0.50 * movapd %xmm0, (%rax)
+# CHECK-NEXT: 1 6 0.33 * movapd (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 movd %eax, %xmm2
+# CHECK-NEXT: 1 6 0.33 * movd (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 movd %xmm0, %ecx
-# CHECK-NEXT: 2 12 0.50 * movd %xmm0, (%rax)
-# CHECK-NEXT: 0 1 0.00 movdqa %xmm0, %xmm2
-# CHECK-NEXT: 2 12 0.50 * movdqa %xmm0, (%rax)
-# CHECK-NEXT: 1 7 0.33 * movdqa (%rax), %xmm2
-# CHECK-NEXT: 0 1 0.00 movdqu %xmm0, %xmm2
-# CHECK-NEXT: 2 12 0.50 * movdqu %xmm0, (%rax)
-# CHECK-NEXT: 1 7 0.33 * movdqu (%rax), %xmm2
-# CHECK-NEXT: 2 3 0.67 movdq2q %xmm0, %mm2
-# CHECK-NEXT: 2 12 0.50 * movhpd %xmm0, (%rax)
-# CHECK-NEXT: 2 8 1.00 * movhpd (%rax), %xmm2
-# CHECK-NEXT: 2 12 0.50 * movlpd %xmm0, (%rax)
-# CHECK-NEXT: 2 8 0.50 * movlpd (%rax), %xmm2
+# CHECK-NEXT: 2 1 0.50 * movd %xmm0, (%rax)
+# CHECK-NEXT: 1 0 0.33 movdqa %xmm0, %xmm2
+# CHECK-NEXT: 2 1 0.50 * movdqa %xmm0, (%rax)
+# CHECK-NEXT: 1 6 0.33 * movdqa (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.33 movdqu %xmm0, %xmm2
+# CHECK-NEXT: 2 1 0.50 * movdqu %xmm0, (%rax)
+# CHECK-NEXT: 1 6 0.33 * movdqu (%rax), %xmm2
+# CHECK-NEXT: 2 1 0.67 movdq2q %xmm0, %mm2
+# CHECK-NEXT: 2 1 0.50 * movhpd %xmm0, (%rax)
+# CHECK-NEXT: 2 7 1.00 * movhpd (%rax), %xmm2
+# CHECK-NEXT: 2 1 0.50 * movlpd %xmm0, (%rax)
+# CHECK-NEXT: 2 7 0.50 * movlpd (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 movmskpd %xmm0, %ecx
# CHECK-NEXT: 2 518 0.50 * movntil %eax, (%rax)
# CHECK-NEXT: 2 512 0.50 * movntiq %rax, (%rax)
# CHECK-NEXT: 2 512 0.50 * movntdq %xmm0, (%rax)
# CHECK-NEXT: 2 518 0.50 * movntpd %xmm0, (%rax)
# CHECK-NEXT: 1 1 0.33 movq %xmm0, %xmm2
-# CHECK-NEXT: 1 3 1.00 movq %rax, %xmm2
-# CHECK-NEXT: 1 7 0.33 * movq (%rax), %xmm2
+# CHECK-NEXT: 1 1 1.00 movq %rax, %xmm2
+# CHECK-NEXT: 1 6 0.33 * movq (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 movq %xmm0, %rcx
-# CHECK-NEXT: 2 12 0.50 * movq %xmm0, (%rax)
+# CHECK-NEXT: 2 1 0.50 * movq %xmm0, (%rax)
# CHECK-NEXT: 2 3 1.00 movq2dq %mm0, %xmm2
# CHECK-NEXT: 1 1 0.33 movsd %xmm0, %xmm2
-# CHECK-NEXT: 2 12 0.50 * movsd %xmm0, (%rax)
-# CHECK-NEXT: 1 7 0.33 * movsd (%rax), %xmm2
-# CHECK-NEXT: 0 1 0.00 movupd %xmm0, %xmm2
-# CHECK-NEXT: 2 12 0.50 * movupd %xmm0, (%rax)
-# CHECK-NEXT: 1 7 0.33 * movupd (%rax), %xmm2
+# CHECK-NEXT: 2 1 0.50 * movsd %xmm0, (%rax)
+# CHECK-NEXT: 1 6 0.33 * movsd (%rax), %xmm2
+# CHECK-NEXT: 1 0 0.33 movupd %xmm0, %xmm2
+# CHECK-NEXT: 2 1 0.50 * movupd %xmm0, (%rax)
+# CHECK-NEXT: 1 6 0.33 * movupd (%rax), %xmm2
# CHECK-NEXT: 1 4 0.50 mulpd %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * mulpd (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * mulpd (%rax), %xmm2
# CHECK-NEXT: 1 4 0.50 mulsd %xmm0, %xmm2
-# CHECK-NEXT: 2 11 0.50 * mulsd (%rax), %xmm2
+# CHECK-NEXT: 2 10 0.50 * mulsd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 orpd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.33 * orpd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.33 * orpd (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 packssdw %xmm0, %xmm2
-# CHECK-NEXT: 2 10 1.00 * packssdw (%rax), %xmm2
+# CHECK-NEXT: 2 9 1.00 * packssdw (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 packsswb %xmm0, %xmm2
-# CHECK-NEXT: 2 10 1.00 * packsswb (%rax), %xmm2
+# CHECK-NEXT: 2 9 1.00 * packsswb (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 packuswb %xmm0, %xmm2
-# CHECK-NEXT: 2 10 1.00 * packuswb (%rax), %xmm2
+# CHECK-NEXT: 2 9 1.00 * packuswb (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 paddb %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.33 * paddb (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.33 * paddb (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 paddd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.33 * paddd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.33 * paddd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 paddq %mm0, %mm2
-# CHECK-NEXT: 2 9 0.50 * paddq (%rax), %mm2
+# CHECK-NEXT: 2 7 0.50 * paddq (%rax), %mm2
# CHECK-NEXT: 1 1 0.33 paddq %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.33 * paddq (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.33 * paddq (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 paddsb %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * paddsb (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * paddsb (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 paddsw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * paddsw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * paddsw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 paddusb %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * paddusb (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * paddusb (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 paddusw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * paddusw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * paddusw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 paddw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.33 * paddw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.33 * paddw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 pand %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.33 * pand (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.33 * pand (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 pandn %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.33 * pandn (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.33 * pandn (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pavgb %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pavgb (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pavgb (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pavgw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pavgw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pavgw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pcmpeqb %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pcmpeqb (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pcmpeqb (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pcmpeqd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pcmpeqd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pcmpeqd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pcmpeqw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pcmpeqw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pcmpeqw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pcmpgtb %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pcmpgtb (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pcmpgtb (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pcmpgtd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pcmpgtd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pcmpgtd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pcmpgtw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pcmpgtw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pcmpgtw (%rax), %xmm2
# CHECK-NEXT: 2 4 1.00 pextrw $1, %xmm0, %ecx
-# CHECK-NEXT: 2 4 1.00 pinsrw $1, %eax, %xmm0
+# CHECK-NEXT: 2 2 1.00 pinsrw $1, %eax, %xmm0
# CHECK-NEXT: 2 8 0.50 * pinsrw $1, (%rax), %xmm0
# CHECK-NEXT: 1 5 0.50 pmaddwd %xmm0, %xmm2
-# CHECK-NEXT: 2 13 0.50 * pmaddwd (%rax), %xmm2
+# CHECK-NEXT: 2 11 0.50 * pmaddwd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pmaxsw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pmaxsw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pmaxsw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pmaxub %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pmaxub (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pmaxub (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pminsw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pminsw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pminsw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pminub %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pminub (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pminub (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 pmovmskb %xmm0, %ecx
# CHECK-NEXT: 1 5 0.50 pmulhuw %xmm0, %xmm2
-# CHECK-NEXT: 2 13 0.50 * pmulhuw (%rax), %xmm2
+# CHECK-NEXT: 2 11 0.50 * pmulhuw (%rax), %xmm2
# CHECK-NEXT: 1 5 0.50 pmulhw %xmm0, %xmm2
-# CHECK-NEXT: 2 13 0.50 * pmulhw (%rax), %xmm2
+# CHECK-NEXT: 2 11 0.50 * pmulhw (%rax), %xmm2
# CHECK-NEXT: 1 5 0.50 pmullw %xmm0, %xmm2
-# CHECK-NEXT: 2 13 0.50 * pmullw (%rax), %xmm2
+# CHECK-NEXT: 2 11 0.50 * pmullw (%rax), %xmm2
# CHECK-NEXT: 1 5 1.00 pmuludq %mm0, %mm2
# CHECK-NEXT: 2 13 1.00 * pmuludq (%rax), %mm2
# CHECK-NEXT: 1 5 0.50 pmuludq %xmm0, %xmm2
-# CHECK-NEXT: 2 13 0.50 * pmuludq (%rax), %xmm2
+# CHECK-NEXT: 2 11 0.50 * pmuludq (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 por %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.33 * por (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.33 * por (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 psadbw %xmm0, %xmm2
-# CHECK-NEXT: 2 10 1.00 * psadbw (%rax), %xmm2
+# CHECK-NEXT: 2 9 1.00 * psadbw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pshufd $1, %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pshufd $1, (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pshufd $1, (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pshufhw $1, %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pshufhw $1, (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pshufhw $1, (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pshuflw $1, %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pshuflw $1, (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pshuflw $1, (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pslld $1, %xmm2
# CHECK-NEXT: 2 2 0.67 pslld %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pslld (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pslld (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pslldq $1, %xmm2
# CHECK-NEXT: 1 1 0.50 psllq $1, %xmm2
# CHECK-NEXT: 2 2 0.67 psllq %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * psllq (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * psllq (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 psllw $1, %xmm2
# CHECK-NEXT: 2 2 0.67 psllw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * psllw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * psllw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 psrad $1, %xmm2
# CHECK-NEXT: 2 2 0.67 psrad %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * psrad (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * psrad (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 psraw $1, %xmm2
# CHECK-NEXT: 2 2 0.67 psraw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * psraw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * psraw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 psrld $1, %xmm2
# CHECK-NEXT: 2 2 0.67 psrld %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * psrld (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * psrld (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 psrldq $1, %xmm2
# CHECK-NEXT: 1 1 0.50 psrlq $1, %xmm2
# CHECK-NEXT: 2 2 0.67 psrlq %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * psrlq (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * psrlq (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 psrlw $1, %xmm2
# CHECK-NEXT: 2 2 0.67 psrlw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * psrlw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * psrlw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 psubb %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.33 * psubb (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.33 * psubb (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 psubd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.33 * psubd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.33 * psubd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 psubq %mm0, %mm2
-# CHECK-NEXT: 2 9 0.50 * psubq (%rax), %mm2
+# CHECK-NEXT: 2 7 0.50 * psubq (%rax), %mm2
# CHECK-NEXT: 1 1 0.33 psubq %xmm0, %xmm2
# CHECK-NEXT: 2 8 0.33 * psubq (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 psubsb %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * psubsb (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * psubsb (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 psubsw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * psubsw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * psubsw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 psubusb %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * psubusb (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * psubusb (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 psubusw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * psubusw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * psubusw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 psubw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.33 * psubw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.33 * psubw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 punpckhbw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * punpckhbw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * punpckhbw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 punpckhdq %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * punpckhdq (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * punpckhdq (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 punpckhqdq %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * punpckhqdq (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * punpckhqdq (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 punpckhwd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * punpckhwd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * punpckhwd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 punpcklbw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * punpcklbw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * punpcklbw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 punpckldq %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * punpckldq (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * punpckldq (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 punpcklqdq %xmm0, %xmm2
# CHECK-NEXT: 2 8 0.50 * punpcklqdq (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 punpcklwd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * punpcklwd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * punpcklwd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 pxor %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.33 * pxor (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.33 * pxor (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 shufpd $1, %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * shufpd $1, (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * shufpd $1, (%rax), %xmm2
# CHECK-NEXT: 1 18 1.00 sqrtpd %xmm0, %xmm2
# CHECK-NEXT: 2 24 1.00 * sqrtpd (%rax), %xmm2
# CHECK-NEXT: 1 18 1.00 sqrtsd %xmm0, %xmm2
# CHECK-NEXT: 2 24 1.00 * sqrtsd (%rax), %xmm2
-# CHECK-NEXT: 1 3 0.50 subpd %xmm0, %xmm2
-# CHECK-NEXT: 2 10 0.50 * subpd (%rax), %xmm2
-# CHECK-NEXT: 1 3 0.50 subsd %xmm0, %xmm2
-# CHECK-NEXT: 2 10 0.50 * subsd (%rax), %xmm2
+# CHECK-NEXT: 1 2 0.50 subpd %xmm0, %xmm2
+# CHECK-NEXT: 2 9 0.50 * subpd (%rax), %xmm2
+# CHECK-NEXT: 1 2 0.50 subsd %xmm0, %xmm2
+# CHECK-NEXT: 2 9 0.50 * subsd (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 ucomisd %xmm0, %xmm1
-# CHECK-NEXT: 2 8 1.00 * ucomisd (%rax), %xmm1
+# CHECK-NEXT: 2 9 1.00 * ucomisd (%rax), %xmm1
# CHECK-NEXT: 1 1 1.00 unpckhpd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 1.00 * unpckhpd (%rax), %xmm2
+# CHECK-NEXT: 2 7 1.00 * unpckhpd (%rax), %xmm2
# CHECK-NEXT: 1 1 1.00 unpcklpd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 1.00 * unpcklpd (%rax), %xmm2
+# CHECK-NEXT: 2 7 1.00 * unpcklpd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 xorpd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.33 * xorpd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.33 * xorpd (%rax), %xmm2
# CHECK: Resources:
# CHECK-NEXT: [0] - ADLPPort00
@@ -692,7 +692,7 @@ xorpd (%rax), %xmm2
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
-# CHECK-NEXT: 107.70 99.20 39.33 39.33 8.50 71.70 1.20 7.83 7.50 7.50 0.20 39.00 -
+# CHECK-NEXT: 109.03 100.53 39.33 39.33 8.50 73.03 1.20 7.83 7.50 7.50 0.20 39.00 -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
@@ -764,17 +764,17 @@ xorpd (%rax), %xmm2
# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - minpd (%rax), %xmm2
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - minsd %xmm0, %xmm2
# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - - 0.33 - minsd (%rax), %xmm2
-# CHECK-NEXT: - - - - - - - - - - - - - movapd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - movapd %xmm0, %xmm2
# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movapd %xmm0, (%rax)
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movapd (%rax), %xmm2
# CHECK-NEXT: - - - - - 1.00 - - - - - - - movd %eax, %xmm2
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movd (%rax), %xmm2
# CHECK-NEXT: 1.00 - - - - - - - - - - - - movd %xmm0, %ecx
# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movd %xmm0, (%rax)
-# CHECK-NEXT: - - - - - - - - - - - - - movdqa %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - movdqa %xmm0, %xmm2
# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movdqa %xmm0, (%rax)
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movdqa (%rax), %xmm2
-# CHECK-NEXT: - - - - - - - - - - - - - movdqu %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - movdqu %xmm0, %xmm2
# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movdqu %xmm0, (%rax)
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movdqu (%rax), %xmm2
# CHECK-NEXT: 0.83 0.33 - - - 0.83 - - - - - - - movdq2q %xmm0, %mm2
@@ -796,7 +796,7 @@ xorpd (%rax), %xmm2
# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - movsd %xmm0, %xmm2
# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movsd %xmm0, (%rax)
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movsd (%rax), %xmm2
-# CHECK-NEXT: - - - - - - - - - - - - - movupd %xmm0, %xmm2
+# CHECK-NEXT: 0.33 0.33 - - - 0.33 - - - - - - - movupd %xmm0, %xmm2
# CHECK-NEXT: - - - - 0.50 - - 0.50 0.50 0.50 - - - movupd %xmm0, (%rax)
# CHECK-NEXT: - - 0.33 0.33 - - - - - - - 0.33 - movupd (%rax), %xmm2
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - mulpd %xmm0, %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse3.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse3.s
index 15baea9604c7..5b92e7c422f4 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse3.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse3.s
@@ -43,19 +43,19 @@ mwait
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 3 0.50 addsubpd %xmm0, %xmm2
-# CHECK-NEXT: 2 10 0.50 * addsubpd (%rax), %xmm2
-# CHECK-NEXT: 1 3 0.50 addsubps %xmm0, %xmm2
-# CHECK-NEXT: 2 10 0.50 * addsubps (%rax), %xmm2
-# CHECK-NEXT: 3 6 2.00 haddpd %xmm0, %xmm2
-# CHECK-NEXT: 4 12 2.00 * haddpd (%rax), %xmm2
+# CHECK-NEXT: 1 2 0.50 addsubpd %xmm0, %xmm2
+# CHECK-NEXT: 2 9 0.50 * addsubpd (%rax), %xmm2
+# CHECK-NEXT: 1 2 0.50 addsubps %xmm0, %xmm2
+# CHECK-NEXT: 2 9 0.50 * addsubps (%rax), %xmm2
+# CHECK-NEXT: 3 5 2.00 haddpd %xmm0, %xmm2
+# CHECK-NEXT: 4 11 2.00 * haddpd (%rax), %xmm2
# CHECK-NEXT: 3 6 2.00 haddps %xmm0, %xmm2
# CHECK-NEXT: 4 12 2.00 * haddps (%rax), %xmm2
-# CHECK-NEXT: 3 6 2.00 hsubpd %xmm0, %xmm2
-# CHECK-NEXT: 4 12 2.00 * hsubpd (%rax), %xmm2
+# CHECK-NEXT: 3 5 2.00 hsubpd %xmm0, %xmm2
+# CHECK-NEXT: 4 11 2.00 * hsubpd (%rax), %xmm2
# CHECK-NEXT: 3 6 2.00 hsubps %xmm0, %xmm2
# CHECK-NEXT: 4 12 2.00 * hsubps (%rax), %xmm2
-# CHECK-NEXT: 1 7 0.33 * lddqu (%rax), %xmm2
+# CHECK-NEXT: 1 6 0.33 * lddqu (%rax), %xmm2
# CHECK-NEXT: 1 100 0.25 U monitor
# CHECK-NEXT: 1 1 1.00 movddup %xmm0, %xmm2
# CHECK-NEXT: 1 7 0.33 * movddup (%rax), %xmm2
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse41.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse41.s
index ffe9150cc591..39daa2aee561 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse41.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse41.s
@@ -156,101 +156,101 @@ roundss $1, (%rax), %xmm2
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 1 0.33 blendpd $11, %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.33 * blendpd $11, (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.33 * blendpd $11, (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 blendps $11, %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.33 * blendps $11, (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.33 * blendps $11, (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 blendvpd %xmm0, %xmm0, %xmm2
# CHECK-NEXT: 2 8 0.33 * blendvpd %xmm0, (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 blendvps %xmm0, %xmm0, %xmm2
# CHECK-NEXT: 2 8 0.33 * blendvps %xmm0, (%rax), %xmm2
# CHECK-NEXT: 3 9 1.00 dppd $22, %xmm0, %xmm2
-# CHECK-NEXT: 4 16 1.00 * dppd $22, (%rax), %xmm2
+# CHECK-NEXT: 4 15 1.00 * dppd $22, (%rax), %xmm2
# CHECK-NEXT: 6 14 1.67 dpps $22, %xmm0, %xmm2
# CHECK-NEXT: 7 21 1.67 * dpps $22, (%rax), %xmm2
# CHECK-NEXT: 2 4 1.00 extractps $1, %xmm0, %ecx
-# CHECK-NEXT: 3 12 1.00 * extractps $1, %xmm0, (%rax)
+# CHECK-NEXT: 3 2 1.00 * extractps $1, %xmm0, (%rax)
# CHECK-NEXT: 1 1 1.00 insertps $1, %xmm0, %xmm2
# CHECK-NEXT: 2 8 1.00 * insertps $1, (%rax), %xmm2
# CHECK-NEXT: 1 7 0.33 * movntdqa (%rax), %xmm2
# CHECK-NEXT: 2 4 1.00 mpsadbw $1, %xmm0, %xmm2
-# CHECK-NEXT: 3 11 1.00 * mpsadbw $1, (%rax), %xmm2
+# CHECK-NEXT: 3 10 1.00 * mpsadbw $1, (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 packusdw %xmm0, %xmm2
-# CHECK-NEXT: 2 10 1.00 * packusdw (%rax), %xmm2
+# CHECK-NEXT: 2 9 1.00 * packusdw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.33 pblendvb %xmm0, %xmm0, %xmm2
# CHECK-NEXT: 2 8 0.33 * pblendvb %xmm0, (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pblendw $11, %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pblendw $11, (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pblendw $11, (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pcmpeqq %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pcmpeqq (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pcmpeqq (%rax), %xmm2
# CHECK-NEXT: 2 4 1.00 pextrb $1, %xmm0, %ecx
# CHECK-NEXT: 3 19 0.50 * pextrb $1, %xmm0, (%rax)
# CHECK-NEXT: 2 4 1.00 pextrd $1, %xmm0, %ecx
-# CHECK-NEXT: 3 12 0.50 * pextrd $1, %xmm0, (%rax)
+# CHECK-NEXT: 3 2 0.50 * pextrd $1, %xmm0, (%rax)
# CHECK-NEXT: 2 4 1.00 pextrq $1, %xmm0, %rcx
-# CHECK-NEXT: 3 12 0.50 * pextrq $1, %xmm0, (%rax)
-# CHECK-NEXT: 3 19 0.50 * pextrw $1, %xmm0, (%rax)
+# CHECK-NEXT: 3 2 0.50 * pextrq $1, %xmm0, (%rax)
+# CHECK-NEXT: 3 2 0.50 * pextrw $1, %xmm0, (%rax)
# CHECK-NEXT: 1 4 1.00 phminposuw %xmm0, %xmm2
# CHECK-NEXT: 2 11 1.00 * phminposuw (%rax), %xmm2
-# CHECK-NEXT: 2 4 1.00 pinsrb $1, %eax, %xmm1
-# CHECK-NEXT: 2 8 0.50 * pinsrb $1, (%rax), %xmm1
-# CHECK-NEXT: 2 4 1.00 pinsrd $1, %eax, %xmm1
-# CHECK-NEXT: 2 8 0.50 * pinsrd $1, (%rax), %xmm1
-# CHECK-NEXT: 2 4 1.00 pinsrq $1, %rax, %xmm1
-# CHECK-NEXT: 2 8 0.50 * pinsrq $1, (%rax), %xmm1
+# CHECK-NEXT: 2 2 1.00 pinsrb $1, %eax, %xmm1
+# CHECK-NEXT: 2 7 0.50 * pinsrb $1, (%rax), %xmm1
+# CHECK-NEXT: 2 2 1.00 pinsrd $1, %eax, %xmm1
+# CHECK-NEXT: 2 7 0.50 * pinsrd $1, (%rax), %xmm1
+# CHECK-NEXT: 2 2 1.00 pinsrq $1, %rax, %xmm1
+# CHECK-NEXT: 2 7 0.50 * pinsrq $1, (%rax), %xmm1
# CHECK-NEXT: 1 1 0.50 pmaxsb %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pmaxsb (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pmaxsb (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pmaxsd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pmaxsd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pmaxsd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pmaxud %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pmaxud (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pmaxud (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pmaxuw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pmaxuw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pmaxuw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pminsb %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pminsb (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pminsb (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pminsd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pminsd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pminsd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pminud %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pminud (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pminud (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pminuw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pminuw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pminuw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pmovsxbd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pmovsxbd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pmovsxbd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pmovsxbq %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pmovsxbq (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pmovsxbq (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pmovsxbw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pmovsxbw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pmovsxbw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pmovsxdq %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pmovsxdq (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pmovsxdq (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pmovsxwd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pmovsxwd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pmovsxwd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pmovsxwq %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pmovsxwq (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pmovsxwq (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pmovzxbd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pmovzxbd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pmovzxbd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pmovzxbq %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pmovzxbq (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pmovzxbq (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pmovzxbw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pmovzxbw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pmovzxbw (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pmovzxdq %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pmovzxdq (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pmovzxdq (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pmovzxwd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pmovzxwd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pmovzxwd (%rax), %xmm2
# CHECK-NEXT: 1 1 0.50 pmovzxwq %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pmovzxwq (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pmovzxwq (%rax), %xmm2
# CHECK-NEXT: 1 5 0.50 pmuldq %xmm0, %xmm2
-# CHECK-NEXT: 2 13 0.50 * pmuldq (%rax), %xmm2
+# CHECK-NEXT: 2 11 0.50 * pmuldq (%rax), %xmm2
# CHECK-NEXT: 2 10 1.00 pmulld %xmm0, %xmm2
-# CHECK-NEXT: 3 18 1.00 * pmulld (%rax), %xmm2
+# CHECK-NEXT: 3 16 1.00 * pmulld (%rax), %xmm2
# CHECK-NEXT: 2 4 1.00 ptest %xmm0, %xmm1
# CHECK-NEXT: 3 9 1.00 * ptest (%rax), %xmm1
# CHECK-NEXT: 2 8 1.00 roundpd $1, %xmm0, %xmm2
-# CHECK-NEXT: 3 15 1.00 * roundpd $1, (%rax), %xmm2
+# CHECK-NEXT: 3 14 1.00 * roundpd $1, (%rax), %xmm2
# CHECK-NEXT: 2 8 1.00 roundps $1, %xmm0, %xmm2
-# CHECK-NEXT: 3 15 1.00 * roundps $1, (%rax), %xmm2
+# CHECK-NEXT: 3 14 1.00 * roundps $1, (%rax), %xmm2
# CHECK-NEXT: 2 8 1.00 roundsd $1, %xmm0, %xmm2
-# CHECK-NEXT: 3 15 1.00 * roundsd $1, (%rax), %xmm2
+# CHECK-NEXT: 3 14 1.00 * roundsd $1, (%rax), %xmm2
# CHECK-NEXT: 2 8 1.00 roundss $1, %xmm0, %xmm2
-# CHECK-NEXT: 3 15 1.00 * roundss $1, (%rax), %xmm2
+# CHECK-NEXT: 3 14 1.00 * roundss $1, (%rax), %xmm2
# CHECK: Resources:
# CHECK-NEXT: [0] - ADLPPort00
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse42.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse42.s
index cb5b34e9b646..63bd12c06020 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse42.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-sse42.s
@@ -59,7 +59,7 @@ pcmpgtq (%rax), %xmm2
# CHECK-NEXT: 3 11 3.00 pcmpistrm $1, %xmm0, %xmm2
# CHECK-NEXT: 4 16 3.00 * pcmpistrm $1, (%rax), %xmm2
# CHECK-NEXT: 1 3 1.00 pcmpgtq %xmm0, %xmm2
-# CHECK-NEXT: 2 10 1.00 * pcmpgtq (%rax), %xmm2
+# CHECK-NEXT: 2 9 1.00 * pcmpgtq (%rax), %xmm2
# CHECK: Resources:
# CHECK-NEXT: [0] - ADLPPort00
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-ssse3.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-ssse3.s
index 33ec9b0fa64d..fa01796ba382 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-ssse3.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-ssse3.s
@@ -107,69 +107,69 @@ psignw (%rax), %xmm2
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 1 1.00 pabsb %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * pabsb (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * pabsb (%rax), %mm2
# CHECK-NEXT: 1 1 0.50 pabsb %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pabsb (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pabsb (%rax), %xmm2
# CHECK-NEXT: 1 1 1.00 pabsd %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * pabsd (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * pabsd (%rax), %mm2
# CHECK-NEXT: 1 1 0.50 pabsd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pabsd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pabsd (%rax), %xmm2
# CHECK-NEXT: 1 1 1.00 pabsw %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * pabsw (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * pabsw (%rax), %mm2
# CHECK-NEXT: 1 1 0.50 pabsw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pabsw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pabsw (%rax), %xmm2
# CHECK-NEXT: 1 1 1.00 palignr $1, %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * palignr $1, (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * palignr $1, (%rax), %mm2
# CHECK-NEXT: 1 1 1.00 palignr $1, %xmm0, %xmm2
-# CHECK-NEXT: 2 8 1.00 * palignr $1, (%rax), %xmm2
+# CHECK-NEXT: 2 7 1.00 * palignr $1, (%rax), %xmm2
# CHECK-NEXT: 3 3 2.00 phaddd %mm0, %mm2
-# CHECK-NEXT: 4 11 2.00 * phaddd (%rax), %mm2
+# CHECK-NEXT: 4 9 2.00 * phaddd (%rax), %mm2
# CHECK-NEXT: 3 2 1.00 phaddd %xmm0, %xmm2
-# CHECK-NEXT: 4 9 1.00 * phaddd (%rax), %xmm2
+# CHECK-NEXT: 4 8 1.00 * phaddd (%rax), %xmm2
# CHECK-NEXT: 3 3 2.00 phaddsw %mm0, %mm2
# CHECK-NEXT: 4 11 2.00 * phaddsw (%rax), %mm2
# CHECK-NEXT: 3 2 1.00 phaddsw %xmm0, %xmm2
-# CHECK-NEXT: 4 9 1.00 * phaddsw (%rax), %xmm2
+# CHECK-NEXT: 4 8 1.00 * phaddsw (%rax), %xmm2
# CHECK-NEXT: 3 3 2.00 phaddw %mm0, %mm2
-# CHECK-NEXT: 4 11 2.00 * phaddw (%rax), %mm2
+# CHECK-NEXT: 4 9 2.00 * phaddw (%rax), %mm2
# CHECK-NEXT: 3 2 1.00 phaddw %xmm0, %xmm2
-# CHECK-NEXT: 4 9 1.00 * phaddw (%rax), %xmm2
+# CHECK-NEXT: 4 8 1.00 * phaddw (%rax), %xmm2
# CHECK-NEXT: 3 3 2.00 phsubd %mm0, %mm2
-# CHECK-NEXT: 4 11 2.00 * phsubd (%rax), %mm2
+# CHECK-NEXT: 4 9 2.00 * phsubd (%rax), %mm2
# CHECK-NEXT: 3 2 1.00 phsubd %xmm0, %xmm2
-# CHECK-NEXT: 4 9 1.00 * phsubd (%rax), %xmm2
+# CHECK-NEXT: 4 8 1.00 * phsubd (%rax), %xmm2
# CHECK-NEXT: 3 3 2.00 phsubsw %mm0, %mm2
# CHECK-NEXT: 4 11 2.00 * phsubsw (%rax), %mm2
# CHECK-NEXT: 3 2 1.00 phsubsw %xmm0, %xmm2
-# CHECK-NEXT: 4 9 1.00 * phsubsw (%rax), %xmm2
+# CHECK-NEXT: 4 8 1.00 * phsubsw (%rax), %xmm2
# CHECK-NEXT: 3 3 2.00 phsubw %mm0, %mm2
-# CHECK-NEXT: 4 11 2.00 * phsubw (%rax), %mm2
+# CHECK-NEXT: 4 9 2.00 * phsubw (%rax), %mm2
# CHECK-NEXT: 3 2 1.00 phsubw %xmm0, %xmm2
-# CHECK-NEXT: 4 9 1.00 * phsubw (%rax), %xmm2
+# CHECK-NEXT: 4 8 1.00 * phsubw (%rax), %xmm2
# CHECK-NEXT: 1 5 1.00 pmaddubsw %mm0, %mm2
# CHECK-NEXT: 2 13 1.00 * pmaddubsw (%rax), %mm2
# CHECK-NEXT: 1 5 0.50 pmaddubsw %xmm0, %xmm2
-# CHECK-NEXT: 2 13 0.50 * pmaddubsw (%rax), %xmm2
+# CHECK-NEXT: 2 11 0.50 * pmaddubsw (%rax), %xmm2
# CHECK-NEXT: 1 5 1.00 pmulhrsw %mm0, %mm2
# CHECK-NEXT: 2 13 1.00 * pmulhrsw (%rax), %mm2
# CHECK-NEXT: 1 5 0.50 pmulhrsw %xmm0, %xmm2
-# CHECK-NEXT: 2 13 0.50 * pmulhrsw (%rax), %xmm2
-# CHECK-NEXT: 2 3 1.00 pshufb %mm0, %mm2
-# CHECK-NEXT: 3 11 1.00 * pshufb (%rax), %mm2
+# CHECK-NEXT: 2 11 0.50 * pmulhrsw (%rax), %xmm2
+# CHECK-NEXT: 3 3 1.00 pshufb %mm0, %mm2
+# CHECK-NEXT: 3 9 1.00 * pshufb (%rax), %mm2
# CHECK-NEXT: 1 1 0.50 pshufb %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * pshufb (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * pshufb (%rax), %xmm2
# CHECK-NEXT: 1 1 1.00 psignb %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * psignb (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * psignb (%rax), %mm2
# CHECK-NEXT: 1 1 0.50 psignb %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * psignb (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * psignb (%rax), %xmm2
# CHECK-NEXT: 1 1 1.00 psignd %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * psignd (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * psignd (%rax), %mm2
# CHECK-NEXT: 1 1 0.50 psignd %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * psignd (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * psignd (%rax), %xmm2
# CHECK-NEXT: 1 1 1.00 psignw %mm0, %mm2
-# CHECK-NEXT: 2 9 1.00 * psignw (%rax), %mm2
+# CHECK-NEXT: 2 7 1.00 * psignw (%rax), %mm2
# CHECK-NEXT: 1 1 0.50 psignw %xmm0, %xmm2
-# CHECK-NEXT: 2 8 0.50 * psignw (%rax), %xmm2
+# CHECK-NEXT: 2 7 0.50 * psignw (%rax), %xmm2
# CHECK: Resources:
# CHECK-NEXT: [0] - ADLPPort00
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-vaes.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-vaes.s
index 74b19b968bec..0e33a9af13e3 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-vaes.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-vaes.s
@@ -22,14 +22,14 @@ vaesenclast (%rax), %ymm1, %ymm3
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 5 0.50 vaesdec %ymm0, %ymm1, %ymm3
-# CHECK-NEXT: 2 12 0.50 * vaesdec (%rax), %ymm1, %ymm3
-# CHECK-NEXT: 1 5 0.50 vaesdeclast %ymm0, %ymm1, %ymm3
-# CHECK-NEXT: 2 12 0.50 * vaesdeclast (%rax), %ymm1, %ymm3
-# CHECK-NEXT: 1 5 0.50 vaesenc %ymm0, %ymm1, %ymm3
-# CHECK-NEXT: 2 12 0.50 * vaesenc (%rax), %ymm1, %ymm3
-# CHECK-NEXT: 1 5 0.50 vaesenclast %ymm0, %ymm1, %ymm3
-# CHECK-NEXT: 2 12 0.50 * vaesenclast (%rax), %ymm1, %ymm3
+# CHECK-NEXT: 1 3 0.50 vaesdec %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 2 11 0.50 * vaesdec (%rax), %ymm1, %ymm3
+# CHECK-NEXT: 1 3 0.50 vaesdeclast %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 2 11 0.50 * vaesdeclast (%rax), %ymm1, %ymm3
+# CHECK-NEXT: 1 3 0.50 vaesenc %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 2 11 0.50 * vaesenc (%rax), %ymm1, %ymm3
+# CHECK-NEXT: 1 3 0.50 vaesenclast %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: 2 11 0.50 * vaesenclast (%rax), %ymm1, %ymm3
# CHECK: Resources:
# CHECK-NEXT: [0] - ADLPPort00
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-vpclmulqdq.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-vpclmulqdq.s
index cd834d35c43d..890f977450a7 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-vpclmulqdq.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-vpclmulqdq.s
@@ -14,7 +14,7 @@ vpclmulqdq $11, (%rax), %ymm1, %ymm3
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 vpclmulqdq $11, %ymm0, %ymm1, %ymm3
-# CHECK-NEXT: 2 11 1.00 * vpclmulqdq $11, (%rax), %ymm1, %ymm3
+# CHECK-NEXT: 2 10 1.00 * vpclmulqdq $11, (%rax), %ymm1, %ymm3
# CHECK: Resources:
# CHECK-NEXT: [0] - ADLPPort00
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_64.s
index b502ab3bf321..9d529a344a5e 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-x86_64.s
@@ -1043,8 +1043,8 @@ xorq (%rax), %rdi
# CHECK-NEXT: 5 13 0.50 * * adcb $7, (%rax)
# CHECK-NEXT: 5 13 0.50 * * lock adcb $7, (%rax)
# CHECK-NEXT: 1 1 0.50 adcb %sil, %dil
-# CHECK-NEXT: 6 13 0.60 * * adcb %sil, (%rax)
-# CHECK-NEXT: 6 13 0.60 * * lock adcb %sil, (%rax)
+# CHECK-NEXT: 6 7 0.60 * * adcb %sil, (%rax)
+# CHECK-NEXT: 6 7 0.60 * * lock adcb %sil, (%rax)
# CHECK-NEXT: 2 6 0.50 * adcb (%rax), %dil
# CHECK-NEXT: 1 1 0.50 adcw $0, %ax
# CHECK-NEXT: 1 1 0.50 adcw $0, %di
@@ -1058,8 +1058,8 @@ xorq (%rax), %rdi
# CHECK-NEXT: 5 12 0.50 * * adcw $7, (%rax)
# CHECK-NEXT: 5 12 0.50 * * lock adcw $7, (%rax)
# CHECK-NEXT: 1 1 0.50 adcw %si, %di
-# CHECK-NEXT: 6 12 0.60 * * adcw %si, (%rax)
-# CHECK-NEXT: 6 12 0.60 * * lock adcw %si, (%rax)
+# CHECK-NEXT: 6 7 0.60 * * adcw %si, (%rax)
+# CHECK-NEXT: 6 7 0.60 * * lock adcw %si, (%rax)
# CHECK-NEXT: 2 6 0.50 * adcw (%rax), %di
# CHECK-NEXT: 1 1 0.50 adcl $0, %eax
# CHECK-NEXT: 1 1 0.50 adcl $0, %edi
@@ -1073,8 +1073,8 @@ xorq (%rax), %rdi
# CHECK-NEXT: 5 12 0.50 * * adcl $7, (%rax)
# CHECK-NEXT: 5 12 0.50 * * lock adcl $7, (%rax)
# CHECK-NEXT: 1 1 0.50 adcl %esi, %edi
-# CHECK-NEXT: 6 12 0.60 * * adcl %esi, (%rax)
-# CHECK-NEXT: 6 12 0.60 * * lock adcl %esi, (%rax)
+# CHECK-NEXT: 6 7 0.60 * * adcl %esi, (%rax)
+# CHECK-NEXT: 6 7 0.60 * * lock adcl %esi, (%rax)
# CHECK-NEXT: 2 6 0.50 * adcl (%rax), %edi
# CHECK-NEXT: 1 1 0.50 adcq $0, %rax
# CHECK-NEXT: 1 1 0.50 adcq $0, %rdi
@@ -1088,91 +1088,91 @@ xorq (%rax), %rdi
# CHECK-NEXT: 5 12 0.50 * * adcq $7, (%rax)
# CHECK-NEXT: 5 12 0.50 * * lock adcq $7, (%rax)
# CHECK-NEXT: 1 1 0.50 adcq %rsi, %rdi
-# CHECK-NEXT: 6 12 0.60 * * adcq %rsi, (%rax)
-# CHECK-NEXT: 6 12 0.60 * * lock adcq %rsi, (%rax)
+# CHECK-NEXT: 6 7 0.60 * * adcq %rsi, (%rax)
+# CHECK-NEXT: 6 7 0.60 * * lock adcq %rsi, (%rax)
# CHECK-NEXT: 2 6 0.50 * adcq (%rax), %rdi
# CHECK-NEXT: 1 1 0.20 addb $7, %al
# CHECK-NEXT: 1 1 0.20 addb $7, %dil
-# CHECK-NEXT: 4 13 0.50 * * addb $7, (%rax)
-# CHECK-NEXT: 4 13 0.50 * * lock addb $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * addb $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock addb $7, (%rax)
# CHECK-NEXT: 1 1 0.20 addb %sil, %dil
-# CHECK-NEXT: 4 13 0.50 * * addb %sil, (%rax)
-# CHECK-NEXT: 4 13 0.50 * * lock addb %sil, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * addb %sil, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock addb %sil, (%rax)
# CHECK-NEXT: 2 6 0.33 * addb (%rax), %dil
# CHECK-NEXT: 1 1 0.20 addw $511, %ax
# CHECK-NEXT: 1 1 0.20 addw $511, %di
-# CHECK-NEXT: 4 12 0.50 * * addw $511, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock addw $511, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * addw $511, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock addw $511, (%rax)
# CHECK-NEXT: 1 1 0.20 addw $7, %di
-# CHECK-NEXT: 4 12 0.50 * * addw $7, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock addw $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * addw $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock addw $7, (%rax)
# CHECK-NEXT: 1 1 0.20 addw %si, %di
-# CHECK-NEXT: 4 12 0.50 * * addw %si, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock addw %si, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * addw %si, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock addw %si, (%rax)
# CHECK-NEXT: 2 6 0.33 * addw (%rax), %di
# CHECK-NEXT: 1 1 0.20 addl $665536, %eax
# CHECK-NEXT: 1 1 0.20 addl $665536, %edi
-# CHECK-NEXT: 4 12 0.50 * * addl $665536, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock addl $665536, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * addl $665536, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock addl $665536, (%rax)
# CHECK-NEXT: 1 1 0.20 addl $7, %edi
-# CHECK-NEXT: 4 12 0.50 * * addl $7, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock addl $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * addl $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock addl $7, (%rax)
# CHECK-NEXT: 1 1 0.20 addl %esi, %edi
-# CHECK-NEXT: 4 12 0.50 * * addl %esi, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock addl %esi, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * addl %esi, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock addl %esi, (%rax)
# CHECK-NEXT: 2 6 0.33 * addl (%rax), %edi
# CHECK-NEXT: 1 1 0.20 addq $665536, %rax
# CHECK-NEXT: 1 1 0.20 addq $665536, %rdi
-# CHECK-NEXT: 4 12 0.50 * * addq $665536, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock addq $665536, (%rax)
-# CHECK-NEXT: 0 1 0.00 addq $7, %rdi
-# CHECK-NEXT: 4 12 0.50 * * addq $7, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock addq $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * addq $665536, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock addq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.20 addq $7, %rdi
+# CHECK-NEXT: 4 7 0.50 * * addq $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock addq $7, (%rax)
# CHECK-NEXT: 1 1 0.20 addq %rsi, %rdi
-# CHECK-NEXT: 4 12 0.50 * * addq %rsi, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock addq %rsi, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * addq %rsi, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock addq %rsi, (%rax)
# CHECK-NEXT: 2 6 0.33 * addq (%rax), %rdi
-# CHECK-NEXT: 1 2 0.20 andb $7, %al
-# CHECK-NEXT: 1 2 0.20 andb $7, %dil
-# CHECK-NEXT: 4 13 0.50 * * andb $7, (%rax)
-# CHECK-NEXT: 4 13 0.50 * * lock andb $7, (%rax)
-# CHECK-NEXT: 1 2 0.20 andb %sil, %dil
-# CHECK-NEXT: 4 13 0.50 * * andb %sil, (%rax)
-# CHECK-NEXT: 4 13 0.50 * * lock andb %sil, (%rax)
+# CHECK-NEXT: 1 1 0.20 andb $7, %al
+# CHECK-NEXT: 1 1 0.20 andb $7, %dil
+# CHECK-NEXT: 4 7 0.50 * * andb $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock andb $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 andb %sil, %dil
+# CHECK-NEXT: 4 7 0.50 * * andb %sil, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock andb %sil, (%rax)
# CHECK-NEXT: 2 6 0.33 * andb (%rax), %dil
# CHECK-NEXT: 1 1 0.20 andw $511, %ax
# CHECK-NEXT: 1 1 0.20 andw $511, %di
-# CHECK-NEXT: 4 12 0.50 * * andw $511, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock andw $511, (%rax)
-# CHECK-NEXT: 1 2 0.20 andw $7, %di
-# CHECK-NEXT: 4 12 0.50 * * andw $7, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock andw $7, (%rax)
-# CHECK-NEXT: 1 2 0.20 andw %si, %di
-# CHECK-NEXT: 4 12 0.50 * * andw %si, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock andw %si, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * andw $511, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock andw $511, (%rax)
+# CHECK-NEXT: 1 1 0.20 andw $7, %di
+# CHECK-NEXT: 4 7 0.50 * * andw $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock andw $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 andw %si, %di
+# CHECK-NEXT: 4 7 0.50 * * andw %si, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock andw %si, (%rax)
# CHECK-NEXT: 2 6 0.33 * andw (%rax), %di
# CHECK-NEXT: 1 2 0.20 andl $665536, %eax
-# CHECK-NEXT: 1 2 0.20 andl $665536, %edi
-# CHECK-NEXT: 4 12 0.50 * * andl $665536, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock andl $665536, (%rax)
-# CHECK-NEXT: 1 2 0.20 andl $7, %edi
-# CHECK-NEXT: 4 12 0.50 * * andl $7, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock andl $7, (%rax)
-# CHECK-NEXT: 1 2 0.20 andl %esi, %edi
-# CHECK-NEXT: 4 12 0.50 * * andl %esi, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock andl %esi, (%rax)
+# CHECK-NEXT: 1 1 0.20 andl $665536, %edi
+# CHECK-NEXT: 4 7 0.50 * * andl $665536, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock andl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.20 andl $7, %edi
+# CHECK-NEXT: 4 7 0.50 * * andl $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock andl $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 andl %esi, %edi
+# CHECK-NEXT: 4 7 0.50 * * andl %esi, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock andl %esi, (%rax)
# CHECK-NEXT: 2 6 0.33 * andl (%rax), %edi
# CHECK-NEXT: 1 2 0.20 andq $665536, %rax
-# CHECK-NEXT: 1 2 0.20 andq $665536, %rdi
-# CHECK-NEXT: 4 12 0.50 * * andq $665536, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock andq $665536, (%rax)
-# CHECK-NEXT: 1 2 0.20 andq $7, %rdi
-# CHECK-NEXT: 4 12 0.50 * * andq $7, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock andq $7, (%rax)
-# CHECK-NEXT: 1 2 0.20 andq %rsi, %rdi
-# CHECK-NEXT: 4 12 0.50 * * andq %rsi, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock andq %rsi, (%rax)
-# CHECK-NEXT: 2 7 0.33 * andq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.20 andq $665536, %rdi
+# CHECK-NEXT: 4 7 0.50 * * andq $665536, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock andq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.20 andq $7, %rdi
+# CHECK-NEXT: 4 7 0.50 * * andq $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock andq $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 andq %rsi, %rdi
+# CHECK-NEXT: 4 7 0.50 * * andq %rsi, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock andq %rsi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * andq (%rax), %rdi
# CHECK-NEXT: 1 3 1.00 bsfw %si, %di
# CHECK-NEXT: 1 3 1.00 bsrw %si, %di
# CHECK-NEXT: 2 8 1.00 * bsfw (%rax), %di
@@ -1203,12 +1203,12 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 1 1.00 btrw $7, %di
# CHECK-NEXT: 1 1 1.00 btsw $7, %di
# CHECK-NEXT: 2 6 1.00 * btw $7, (%rax)
-# CHECK-NEXT: 4 12 1.00 * * btcw $7, (%rax)
-# CHECK-NEXT: 4 12 1.00 * * btrw $7, (%rax)
-# CHECK-NEXT: 4 12 1.00 * * btsw $7, (%rax)
-# CHECK-NEXT: 4 12 1.00 * * lock btcw $7, (%rax)
-# CHECK-NEXT: 4 12 1.00 * * lock btrw $7, (%rax)
-# CHECK-NEXT: 4 12 1.00 * * lock btsw $7, (%rax)
+# CHECK-NEXT: 4 7 1.00 * * btcw $7, (%rax)
+# CHECK-NEXT: 4 7 1.00 * * btrw $7, (%rax)
+# CHECK-NEXT: 4 7 1.00 * * btsw $7, (%rax)
+# CHECK-NEXT: 4 7 1.00 * * lock btcw $7, (%rax)
+# CHECK-NEXT: 4 7 1.00 * * lock btrw $7, (%rax)
+# CHECK-NEXT: 4 7 1.00 * * lock btsw $7, (%rax)
# CHECK-NEXT: 1 1 1.00 btl %esi, %edi
# CHECK-NEXT: 1 1 1.00 btcl %esi, %edi
# CHECK-NEXT: 1 1 1.00 btrl %esi, %edi
@@ -1225,16 +1225,16 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 1 1.00 btrl $7, %edi
# CHECK-NEXT: 1 1 1.00 btsl $7, %edi
# CHECK-NEXT: 2 6 1.00 * btl $7, (%rax)
-# CHECK-NEXT: 4 12 1.00 * * btcl $7, (%rax)
-# CHECK-NEXT: 4 12 1.00 * * btrl $7, (%rax)
-# CHECK-NEXT: 4 12 1.00 * * btsl $7, (%rax)
-# CHECK-NEXT: 4 12 1.00 * * lock btcl $7, (%rax)
-# CHECK-NEXT: 4 12 1.00 * * lock btrl $7, (%rax)
-# CHECK-NEXT: 4 12 1.00 * * lock btsl $7, (%rax)
-# CHECK-NEXT: 1 3 1.00 btq %rsi, %rdi
-# CHECK-NEXT: 1 3 1.00 btcq %rsi, %rdi
-# CHECK-NEXT: 1 3 1.00 btrq %rsi, %rdi
-# CHECK-NEXT: 1 3 1.00 btsq %rsi, %rdi
+# CHECK-NEXT: 4 7 1.00 * * btcl $7, (%rax)
+# CHECK-NEXT: 4 7 1.00 * * btrl $7, (%rax)
+# CHECK-NEXT: 4 7 1.00 * * btsl $7, (%rax)
+# CHECK-NEXT: 4 7 1.00 * * lock btcl $7, (%rax)
+# CHECK-NEXT: 4 7 1.00 * * lock btrl $7, (%rax)
+# CHECK-NEXT: 4 7 1.00 * * lock btsl $7, (%rax)
+# CHECK-NEXT: 1 1 1.00 btq %rsi, %rdi
+# CHECK-NEXT: 1 1 1.00 btcq %rsi, %rdi
+# CHECK-NEXT: 1 1 1.00 btrq %rsi, %rdi
+# CHECK-NEXT: 1 1 1.00 btsq %rsi, %rdi
# CHECK-NEXT: 9 10 1.60 * btq %rsi, (%rax)
# CHECK-NEXT: 10 17 1.40 * * btcq %rsi, (%rax)
# CHECK-NEXT: 10 17 1.40 * * btrq %rsi, (%rax)
@@ -1247,15 +1247,15 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 1 1.00 btrq $7, %rdi
# CHECK-NEXT: 1 1 1.00 btsq $7, %rdi
# CHECK-NEXT: 2 6 1.00 * btq $7, (%rax)
-# CHECK-NEXT: 4 12 1.00 * * btcq $7, (%rax)
-# CHECK-NEXT: 4 12 1.00 * * btrq $7, (%rax)
-# CHECK-NEXT: 4 12 1.00 * * btsq $7, (%rax)
-# CHECK-NEXT: 4 12 1.00 * * lock btcq $7, (%rax)
-# CHECK-NEXT: 4 12 1.00 * * lock btrq $7, (%rax)
-# CHECK-NEXT: 4 12 1.00 * * lock btsq $7, (%rax)
-# CHECK-NEXT: 1 1 0.50 cbtw
-# CHECK-NEXT: 1 1 0.50 cwtl
-# CHECK-NEXT: 1 1 0.50 cltq
+# CHECK-NEXT: 4 7 1.00 * * btcq $7, (%rax)
+# CHECK-NEXT: 4 7 1.00 * * btrq $7, (%rax)
+# CHECK-NEXT: 4 7 1.00 * * btsq $7, (%rax)
+# CHECK-NEXT: 4 7 1.00 * * lock btcq $7, (%rax)
+# CHECK-NEXT: 4 7 1.00 * * lock btrq $7, (%rax)
+# CHECK-NEXT: 4 7 1.00 * * lock btsq $7, (%rax)
+# CHECK-NEXT: 1 1 0.33 cbtw
+# CHECK-NEXT: 1 1 0.33 cwtl
+# CHECK-NEXT: 1 1 0.33 cltq
# CHECK-NEXT: 2 2 0.50 cwtd
# CHECK-NEXT: 1 1 0.50 cltd
# CHECK-NEXT: 1 1 0.50 cqto
@@ -1310,34 +1310,34 @@ xorq (%rax), %rdi
# CHECK-NEXT: 6 12 1.00 * * lock cmpxchgq %rcx, (%rbx)
# CHECK-NEXT: 26 18 6.00 U cpuid
# CHECK-NEXT: 1 1 0.20 decb %dil
-# CHECK-NEXT: 4 13 0.50 * * decb (%rax)
-# CHECK-NEXT: 4 13 0.50 * * lock decb (%rax)
+# CHECK-NEXT: 4 7 0.50 * * decb (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock decb (%rax)
# CHECK-NEXT: 1 1 0.20 decw %di
-# CHECK-NEXT: 4 12 0.50 * * decw (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock decw (%rax)
+# CHECK-NEXT: 4 7 0.50 * * decw (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock decw (%rax)
# CHECK-NEXT: 1 1 0.20 decl %edi
-# CHECK-NEXT: 4 12 0.50 * * decl (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock decl (%rax)
-# CHECK-NEXT: 0 1 0.00 decq %rdi
-# CHECK-NEXT: 4 12 0.50 * * decq (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock decq (%rax)
-# CHECK-NEXT: 3 17 3.00 U divb %dil
-# CHECK-NEXT: 3 22 3.00 * U divb (%rax)
+# CHECK-NEXT: 4 7 0.50 * * decl (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock decl (%rax)
+# CHECK-NEXT: 1 1 0.20 decq %rdi
+# CHECK-NEXT: 4 7 0.50 * * decq (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock decq (%rax)
+# CHECK-NEXT: 4 17 3.00 U divb %dil
+# CHECK-NEXT: 5 22 3.00 * U divb (%rax)
# CHECK-NEXT: 4 16 3.00 U divw %si
# CHECK-NEXT: 5 20 3.00 * U divw (%rax)
# CHECK-NEXT: 4 15 3.00 U divl %edx
# CHECK-NEXT: 5 19 3.00 * U divl (%rax)
-# CHECK-NEXT: 3 18 3.00 U divq %rcx
-# CHECK-NEXT: 4 23 3.00 * U divq (%rax)
+# CHECK-NEXT: 5 18 3.00 U divq %rcx
+# CHECK-NEXT: 5 23 3.00 * U divq (%rax)
# CHECK-NEXT: 57 126 11.50 U enter $7, $4095
-# CHECK-NEXT: 3 17 3.00 U idivb %dil
-# CHECK-NEXT: 3 22 3.00 * U idivb (%rax)
+# CHECK-NEXT: 4 17 3.00 U idivb %dil
+# CHECK-NEXT: 5 22 3.00 * U idivb (%rax)
# CHECK-NEXT: 4 16 3.00 U idivw %si
# CHECK-NEXT: 5 20 3.00 * U idivw (%rax)
# CHECK-NEXT: 4 15 3.00 U idivl %edx
# CHECK-NEXT: 5 19 3.00 * U idivl (%rax)
-# CHECK-NEXT: 3 18 3.00 U idivq %rcx
-# CHECK-NEXT: 4 23 3.00 * U idivq (%rax)
+# CHECK-NEXT: 5 18 3.00 U idivq %rcx
+# CHECK-NEXT: 5 23 3.00 * U idivq (%rax)
# CHECK-NEXT: 1 3 1.00 imulb %dil
# CHECK-NEXT: 2 8 1.00 * imulb (%rax)
# CHECK-NEXT: 4 5 1.00 imulw %di
@@ -1369,19 +1369,19 @@ xorq (%rax), %rdi
# CHECK-NEXT: 87 35 21.00 U inw $7, %ax
# CHECK-NEXT: 87 35 20.00 U inw %dx, %ax
# CHECK-NEXT: 94 35 21.00 U inl $7, %eax
-# CHECK-NEXT: 99 1 21.00 U inl %dx, %eax
+# CHECK-NEXT: 2 1 0.20 U inl %dx, %eax
# CHECK-NEXT: 1 1 0.20 incb %dil
-# CHECK-NEXT: 4 13 0.50 * * incb (%rax)
-# CHECK-NEXT: 4 13 0.50 * * lock incb (%rax)
+# CHECK-NEXT: 4 7 0.50 * * incb (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock incb (%rax)
# CHECK-NEXT: 1 1 0.20 incw %di
-# CHECK-NEXT: 4 12 0.50 * * incw (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock incw (%rax)
+# CHECK-NEXT: 4 7 0.50 * * incw (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock incw (%rax)
# CHECK-NEXT: 1 1 0.20 incl %edi
-# CHECK-NEXT: 4 12 0.50 * * incl (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock incl (%rax)
-# CHECK-NEXT: 0 1 0.00 incq %rdi
-# CHECK-NEXT: 4 12 0.50 * * incq (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock incq (%rax)
+# CHECK-NEXT: 4 7 0.50 * * incl (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock incl (%rax)
+# CHECK-NEXT: 1 1 0.20 incq %rdi
+# CHECK-NEXT: 4 7 0.50 * * incq (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock incq (%rax)
# CHECK-NEXT: 83 20 19.00 U insb %dx, %es:(%rdi)
# CHECK-NEXT: 86 20 19.00 U insw %dx, %es:(%rdi)
# CHECK-NEXT: 92 20 21.00 U insl %dx, %es:(%rdi)
@@ -1432,17 +1432,17 @@ xorq (%rax), %rdi
# CHECK-NEXT: 2 4 1.00 mulq %rcx
# CHECK-NEXT: 3 9 1.00 * mulq (%rax)
# CHECK-NEXT: 1 1 0.20 negb %dil
-# CHECK-NEXT: 4 13 0.50 * * negb (%r8)
-# CHECK-NEXT: 4 13 0.50 * * lock negb (%r8)
+# CHECK-NEXT: 4 7 0.50 * * negb (%r8)
+# CHECK-NEXT: 4 7 0.50 * * lock negb (%r8)
# CHECK-NEXT: 1 1 0.20 negw %si
-# CHECK-NEXT: 4 12 0.50 * * negw (%r9)
-# CHECK-NEXT: 4 12 0.50 * * lock negw (%r9)
+# CHECK-NEXT: 4 7 0.50 * * negw (%r9)
+# CHECK-NEXT: 4 7 0.50 * * lock negw (%r9)
# CHECK-NEXT: 1 1 0.20 negl %edx
-# CHECK-NEXT: 4 12 0.50 * * negl (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock negl (%rax)
+# CHECK-NEXT: 4 7 0.50 * * negl (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock negl (%rax)
# CHECK-NEXT: 1 1 0.20 negq %rcx
-# CHECK-NEXT: 4 12 0.50 * * negq (%r10)
-# CHECK-NEXT: 4 12 0.50 * * lock negq (%r10)
+# CHECK-NEXT: 4 7 0.50 * * negq (%r10)
+# CHECK-NEXT: 4 7 0.50 * * lock negq (%r10)
# CHECK-NEXT: 0 1 0.00 nop
# CHECK-NEXT: 0 1 0.00 nopw %di
# CHECK-NEXT: 0 1 0.00 nopw (%rcx)
@@ -1451,58 +1451,58 @@ xorq (%rax), %rdi
# CHECK-NEXT: 0 1 0.00 nopq %rdx
# CHECK-NEXT: 0 1 0.00 nopq (%r9)
# CHECK-NEXT: 1 1 0.20 notb %dil
-# CHECK-NEXT: 4 13 0.50 * * notb (%r8)
-# CHECK-NEXT: 4 13 0.50 * * lock notb (%r8)
+# CHECK-NEXT: 4 7 0.50 * * notb (%r8)
+# CHECK-NEXT: 4 7 0.50 * * lock notb (%r8)
# CHECK-NEXT: 1 1 0.20 notw %si
-# CHECK-NEXT: 4 12 0.50 * * notw (%r9)
-# CHECK-NEXT: 4 12 0.50 * * lock notw (%r9)
+# CHECK-NEXT: 4 7 0.50 * * notw (%r9)
+# CHECK-NEXT: 4 7 0.50 * * lock notw (%r9)
# CHECK-NEXT: 1 1 0.20 notl %edx
-# CHECK-NEXT: 4 12 0.50 * * notl (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock notl (%rax)
+# CHECK-NEXT: 4 7 0.50 * * notl (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock notl (%rax)
# CHECK-NEXT: 1 1 0.20 notq %rcx
-# CHECK-NEXT: 4 12 0.50 * * notq (%r10)
-# CHECK-NEXT: 4 12 0.50 * * lock notq (%r10)
-# CHECK-NEXT: 1 2 0.20 orb $7, %al
-# CHECK-NEXT: 1 2 0.20 orb $7, %dil
-# CHECK-NEXT: 4 13 0.50 * * orb $7, (%rax)
-# CHECK-NEXT: 4 13 0.50 * * lock orb $7, (%rax)
-# CHECK-NEXT: 1 2 0.20 orb %sil, %dil
-# CHECK-NEXT: 4 13 0.50 * * orb %sil, (%rax)
-# CHECK-NEXT: 4 13 0.50 * * lock orb %sil, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * notq (%r10)
+# CHECK-NEXT: 4 7 0.50 * * lock notq (%r10)
+# CHECK-NEXT: 1 1 0.20 orb $7, %al
+# CHECK-NEXT: 1 1 0.20 orb $7, %dil
+# CHECK-NEXT: 4 7 0.50 * * orb $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock orb $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 orb %sil, %dil
+# CHECK-NEXT: 4 7 0.50 * * orb %sil, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock orb %sil, (%rax)
# CHECK-NEXT: 2 6 0.33 * orb (%rax), %dil
# CHECK-NEXT: 1 1 0.20 orw $511, %ax
# CHECK-NEXT: 1 1 0.20 orw $511, %di
-# CHECK-NEXT: 4 12 0.50 * * orw $511, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock orw $511, (%rax)
-# CHECK-NEXT: 1 2 0.20 orw $7, %di
-# CHECK-NEXT: 4 12 0.50 * * orw $7, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock orw $7, (%rax)
-# CHECK-NEXT: 1 2 0.20 orw %si, %di
-# CHECK-NEXT: 4 12 0.50 * * orw %si, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock orw %si, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * orw $511, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock orw $511, (%rax)
+# CHECK-NEXT: 1 1 0.20 orw $7, %di
+# CHECK-NEXT: 4 7 0.50 * * orw $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock orw $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 orw %si, %di
+# CHECK-NEXT: 4 7 0.50 * * orw %si, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock orw %si, (%rax)
# CHECK-NEXT: 2 6 0.33 * orw (%rax), %di
# CHECK-NEXT: 1 2 0.20 orl $665536, %eax
-# CHECK-NEXT: 1 2 0.20 orl $665536, %edi
-# CHECK-NEXT: 4 12 0.50 * * orl $665536, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock orl $665536, (%rax)
-# CHECK-NEXT: 1 2 0.20 orl $7, %edi
-# CHECK-NEXT: 4 12 0.50 * * orl $7, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock orl $7, (%rax)
-# CHECK-NEXT: 1 2 0.20 orl %esi, %edi
-# CHECK-NEXT: 4 12 0.50 * * orl %esi, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock orl %esi, (%rax)
+# CHECK-NEXT: 1 1 0.20 orl $665536, %edi
+# CHECK-NEXT: 4 7 0.50 * * orl $665536, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock orl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.20 orl $7, %edi
+# CHECK-NEXT: 4 7 0.50 * * orl $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock orl $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 orl %esi, %edi
+# CHECK-NEXT: 4 7 0.50 * * orl %esi, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock orl %esi, (%rax)
# CHECK-NEXT: 2 6 0.33 * orl (%rax), %edi
# CHECK-NEXT: 1 2 0.20 orq $665536, %rax
-# CHECK-NEXT: 1 2 0.20 orq $665536, %rdi
-# CHECK-NEXT: 4 12 0.50 * * orq $665536, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock orq $665536, (%rax)
-# CHECK-NEXT: 1 2 0.20 orq $7, %rdi
-# CHECK-NEXT: 4 12 0.50 * * orq $7, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock orq $7, (%rax)
-# CHECK-NEXT: 1 2 0.20 orq %rsi, %rdi
-# CHECK-NEXT: 4 12 0.50 * * orq %rsi, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock orq %rsi, (%rax)
-# CHECK-NEXT: 2 7 0.33 * orq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.20 orq $665536, %rdi
+# CHECK-NEXT: 4 7 0.50 * * orq $665536, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock orq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.20 orq $7, %rdi
+# CHECK-NEXT: 4 7 0.50 * * orq $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock orq $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 orq %rsi, %rdi
+# CHECK-NEXT: 4 7 0.50 * * orq %rsi, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock orq %rsi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * orq (%rax), %rdi
# CHECK-NEXT: 73 35 15.33 U outb %al, $7
# CHECK-NEXT: 73 35 15.50 U outb %al, %dx
# CHECK-NEXT: 79 35 17.00 U outw %ax, $7
@@ -1569,50 +1569,50 @@ xorq (%rax), %rdi
# CHECK-NEXT: 2 1 1.00 rorb %dil
# CHECK-NEXT: 5 13 1.00 * * rolb (%rax)
# CHECK-NEXT: 5 13 1.00 * * rorb (%rax)
-# CHECK-NEXT: 2 1 1.00 rolb $7, %dil
-# CHECK-NEXT: 2 1 1.00 rorb $7, %dil
-# CHECK-NEXT: 5 13 1.00 * * rolb $7, (%rax)
-# CHECK-NEXT: 5 13 1.00 * * rorb $7, (%rax)
-# CHECK-NEXT: 2 2 1.00 rolb %cl, %dil
-# CHECK-NEXT: 2 2 1.00 rorb %cl, %dil
-# CHECK-NEXT: 5 13 1.00 * * rolb %cl, (%rax)
-# CHECK-NEXT: 5 13 1.00 * * rorb %cl, (%rax)
+# CHECK-NEXT: 1 1 0.50 rolb $7, %dil
+# CHECK-NEXT: 3 1 0.60 rorb $7, %dil
+# CHECK-NEXT: 5 7 1.00 * * rolb $7, (%rax)
+# CHECK-NEXT: 5 7 1.00 * * rorb $7, (%rax)
+# CHECK-NEXT: 2 1 1.00 rolb %cl, %dil
+# CHECK-NEXT: 2 1 1.00 rorb %cl, %dil
+# CHECK-NEXT: 5 7 1.00 * * rolb %cl, (%rax)
+# CHECK-NEXT: 5 7 1.00 * * rorb %cl, (%rax)
# CHECK-NEXT: 2 1 1.00 rolw %di
# CHECK-NEXT: 2 1 1.00 rorw %di
# CHECK-NEXT: 5 12 1.00 * * rolw (%rax)
# CHECK-NEXT: 5 12 1.00 * * rorw (%rax)
-# CHECK-NEXT: 2 1 1.00 rolw $7, %di
-# CHECK-NEXT: 2 1 1.00 rorw $7, %di
-# CHECK-NEXT: 5 12 1.00 * * rolw $7, (%rax)
-# CHECK-NEXT: 5 12 1.00 * * rorw $7, (%rax)
-# CHECK-NEXT: 2 2 1.00 rolw %cl, %di
-# CHECK-NEXT: 2 2 1.00 rorw %cl, %di
-# CHECK-NEXT: 5 12 1.00 * * rolw %cl, (%rax)
-# CHECK-NEXT: 5 12 1.00 * * rorw %cl, (%rax)
+# CHECK-NEXT: 1 1 0.50 rolw $7, %di
+# CHECK-NEXT: 1 1 0.50 rorw $7, %di
+# CHECK-NEXT: 5 7 1.00 * * rolw $7, (%rax)
+# CHECK-NEXT: 5 7 1.00 * * rorw $7, (%rax)
+# CHECK-NEXT: 2 1 1.00 rolw %cl, %di
+# CHECK-NEXT: 2 1 1.00 rorw %cl, %di
+# CHECK-NEXT: 5 7 1.00 * * rolw %cl, (%rax)
+# CHECK-NEXT: 5 7 1.00 * * rorw %cl, (%rax)
# CHECK-NEXT: 2 1 1.00 roll %edi
# CHECK-NEXT: 2 1 1.00 rorl %edi
# CHECK-NEXT: 5 12 1.00 * * roll (%rax)
# CHECK-NEXT: 5 12 1.00 * * rorl (%rax)
-# CHECK-NEXT: 2 1 1.00 roll $7, %edi
-# CHECK-NEXT: 2 1 1.00 rorl $7, %edi
-# CHECK-NEXT: 5 12 1.00 * * roll $7, (%rax)
-# CHECK-NEXT: 5 12 1.00 * * rorl $7, (%rax)
-# CHECK-NEXT: 2 2 1.00 roll %cl, %edi
-# CHECK-NEXT: 2 2 1.00 rorl %cl, %edi
-# CHECK-NEXT: 5 12 1.00 * * roll %cl, (%rax)
-# CHECK-NEXT: 5 12 1.00 * * rorl %cl, (%rax)
+# CHECK-NEXT: 1 1 0.50 roll $7, %edi
+# CHECK-NEXT: 1 1 0.50 rorl $7, %edi
+# CHECK-NEXT: 5 7 1.00 * * roll $7, (%rax)
+# CHECK-NEXT: 5 7 1.00 * * rorl $7, (%rax)
+# CHECK-NEXT: 2 1 1.00 roll %cl, %edi
+# CHECK-NEXT: 2 1 1.00 rorl %cl, %edi
+# CHECK-NEXT: 5 7 1.00 * * roll %cl, (%rax)
+# CHECK-NEXT: 5 7 1.00 * * rorl %cl, (%rax)
# CHECK-NEXT: 2 1 1.00 rolq %rdi
# CHECK-NEXT: 2 1 1.00 rorq %rdi
# CHECK-NEXT: 5 12 1.00 * * rolq (%rax)
# CHECK-NEXT: 5 12 1.00 * * rorq (%rax)
-# CHECK-NEXT: 2 1 1.00 rolq $7, %rdi
-# CHECK-NEXT: 2 1 1.00 rorq $7, %rdi
-# CHECK-NEXT: 5 12 1.00 * * rolq $7, (%rax)
-# CHECK-NEXT: 5 12 1.00 * * rorq $7, (%rax)
-# CHECK-NEXT: 2 2 1.00 rolq %cl, %rdi
-# CHECK-NEXT: 2 2 1.00 rorq %cl, %rdi
-# CHECK-NEXT: 5 12 1.00 * * rolq %cl, (%rax)
-# CHECK-NEXT: 5 12 1.00 * * rorq %cl, (%rax)
+# CHECK-NEXT: 1 1 0.50 rolq $7, %rdi
+# CHECK-NEXT: 1 1 0.50 rorq $7, %rdi
+# CHECK-NEXT: 5 7 1.00 * * rolq $7, (%rax)
+# CHECK-NEXT: 5 7 1.00 * * rorq $7, (%rax)
+# CHECK-NEXT: 2 1 1.00 rolq %cl, %rdi
+# CHECK-NEXT: 2 1 1.00 rorq %cl, %rdi
+# CHECK-NEXT: 5 7 1.00 * * rolq %cl, (%rax)
+# CHECK-NEXT: 5 7 1.00 * * rorq %cl, (%rax)
# CHECK-NEXT: 2 4 1.00 sahf
# CHECK-NEXT: 1 1 0.50 sarb %dil
# CHECK-NEXT: 1 1 0.50 shlb %dil
@@ -1623,15 +1623,15 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 1 0.50 sarb $7, %dil
# CHECK-NEXT: 1 1 0.50 shlb $7, %dil
# CHECK-NEXT: 1 1 0.50 shrb $7, %dil
-# CHECK-NEXT: 4 13 0.50 * * sarb $7, (%rax)
-# CHECK-NEXT: 4 13 0.50 * * shlb $7, (%rax)
-# CHECK-NEXT: 4 13 0.50 * * shrb $7, (%rax)
-# CHECK-NEXT: 2 2 1.00 sarb %cl, %dil
-# CHECK-NEXT: 2 2 1.00 shlb %cl, %dil
-# CHECK-NEXT: 2 2 1.00 shrb %cl, %dil
-# CHECK-NEXT: 5 13 1.00 * * sarb %cl, (%rax)
-# CHECK-NEXT: 5 13 1.00 * * shlb %cl, (%rax)
-# CHECK-NEXT: 5 13 1.00 * * shrb %cl, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * sarb $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * shlb $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * shrb $7, (%rax)
+# CHECK-NEXT: 2 1 1.00 sarb %cl, %dil
+# CHECK-NEXT: 2 1 1.00 shlb %cl, %dil
+# CHECK-NEXT: 2 1 1.00 shrb %cl, %dil
+# CHECK-NEXT: 5 7 1.00 * * sarb %cl, (%rax)
+# CHECK-NEXT: 5 7 1.00 * * shlb %cl, (%rax)
+# CHECK-NEXT: 5 7 1.00 * * shrb %cl, (%rax)
# CHECK-NEXT: 1 1 0.50 sarw %di
# CHECK-NEXT: 1 1 0.50 shlw %di
# CHECK-NEXT: 1 1 0.50 shrw %di
@@ -1641,15 +1641,15 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 1 0.50 sarw $7, %di
# CHECK-NEXT: 1 1 0.50 shlw $7, %di
# CHECK-NEXT: 1 1 0.50 shrw $7, %di
-# CHECK-NEXT: 4 12 0.50 * * sarw $7, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * shlw $7, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * shrw $7, (%rax)
-# CHECK-NEXT: 2 2 1.00 sarw %cl, %di
-# CHECK-NEXT: 2 2 1.00 shlw %cl, %di
-# CHECK-NEXT: 2 2 1.00 shrw %cl, %di
-# CHECK-NEXT: 5 12 1.00 * * sarw %cl, (%rax)
-# CHECK-NEXT: 5 12 1.00 * * shlw %cl, (%rax)
-# CHECK-NEXT: 5 12 1.00 * * shrw %cl, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * sarw $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * shlw $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * shrw $7, (%rax)
+# CHECK-NEXT: 2 1 1.00 sarw %cl, %di
+# CHECK-NEXT: 2 1 1.00 shlw %cl, %di
+# CHECK-NEXT: 2 1 1.00 shrw %cl, %di
+# CHECK-NEXT: 5 7 1.00 * * sarw %cl, (%rax)
+# CHECK-NEXT: 5 7 1.00 * * shlw %cl, (%rax)
+# CHECK-NEXT: 5 7 1.00 * * shrw %cl, (%rax)
# CHECK-NEXT: 1 1 0.50 sarl %edi
# CHECK-NEXT: 1 1 0.50 shll %edi
# CHECK-NEXT: 1 1 0.50 shrl %edi
@@ -1659,15 +1659,15 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 1 0.50 sarl $7, %edi
# CHECK-NEXT: 1 1 0.50 shll $7, %edi
# CHECK-NEXT: 1 1 0.50 shrl $7, %edi
-# CHECK-NEXT: 4 12 0.50 * * sarl $7, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * shll $7, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * shrl $7, (%rax)
-# CHECK-NEXT: 2 2 1.00 sarl %cl, %edi
-# CHECK-NEXT: 2 2 1.00 shll %cl, %edi
-# CHECK-NEXT: 2 2 1.00 shrl %cl, %edi
-# CHECK-NEXT: 5 12 1.00 * * sarl %cl, (%rax)
-# CHECK-NEXT: 5 12 1.00 * * shll %cl, (%rax)
-# CHECK-NEXT: 5 12 1.00 * * shrl %cl, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * sarl $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * shll $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * shrl $7, (%rax)
+# CHECK-NEXT: 2 1 1.00 sarl %cl, %edi
+# CHECK-NEXT: 2 1 1.00 shll %cl, %edi
+# CHECK-NEXT: 2 1 1.00 shrl %cl, %edi
+# CHECK-NEXT: 5 7 1.00 * * sarl %cl, (%rax)
+# CHECK-NEXT: 5 7 1.00 * * shll %cl, (%rax)
+# CHECK-NEXT: 5 7 1.00 * * shrl %cl, (%rax)
# CHECK-NEXT: 1 1 0.50 sarq %rdi
# CHECK-NEXT: 1 1 0.50 shlq %rdi
# CHECK-NEXT: 1 1 0.50 shrq %rdi
@@ -1677,15 +1677,15 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 1 0.50 sarq $7, %rdi
# CHECK-NEXT: 1 1 0.50 shlq $7, %rdi
# CHECK-NEXT: 1 1 0.50 shrq $7, %rdi
-# CHECK-NEXT: 4 12 0.50 * * sarq $7, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * shlq $7, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * shrq $7, (%rax)
-# CHECK-NEXT: 2 2 1.00 sarq %cl, %rdi
-# CHECK-NEXT: 2 2 1.00 shlq %cl, %rdi
-# CHECK-NEXT: 2 2 1.00 shrq %cl, %rdi
-# CHECK-NEXT: 5 12 1.00 * * sarq %cl, (%rax)
-# CHECK-NEXT: 5 12 1.00 * * shlq %cl, (%rax)
-# CHECK-NEXT: 5 12 1.00 * * shrq %cl, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * sarq $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * shlq $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * shrq $7, (%rax)
+# CHECK-NEXT: 2 1 1.00 sarq %cl, %rdi
+# CHECK-NEXT: 2 1 1.00 shlq %cl, %rdi
+# CHECK-NEXT: 2 1 1.00 shrq %cl, %rdi
+# CHECK-NEXT: 5 7 1.00 * * sarq %cl, (%rax)
+# CHECK-NEXT: 5 7 1.00 * * shlq %cl, (%rax)
+# CHECK-NEXT: 5 7 1.00 * * shrq %cl, (%rax)
# CHECK-NEXT: 1 1 0.50 sbbb $0, %al
# CHECK-NEXT: 1 1 0.50 sbbb $0, %dil
# CHECK-NEXT: 5 13 0.50 * * sbbb $0, (%rax)
@@ -1695,8 +1695,8 @@ xorq (%rax), %rdi
# CHECK-NEXT: 5 13 0.50 * * sbbb $7, (%rax)
# CHECK-NEXT: 5 13 0.50 * * lock sbbb $7, (%rax)
# CHECK-NEXT: 1 1 0.50 sbbb %sil, %dil
-# CHECK-NEXT: 6 13 0.60 * * sbbb %sil, (%rax)
-# CHECK-NEXT: 6 13 0.60 * * lock sbbb %sil, (%rax)
+# CHECK-NEXT: 6 7 0.60 * * sbbb %sil, (%rax)
+# CHECK-NEXT: 6 7 0.60 * * lock sbbb %sil, (%rax)
# CHECK-NEXT: 2 6 0.50 * sbbb (%rax), %dil
# CHECK-NEXT: 1 1 0.50 sbbw $0, %ax
# CHECK-NEXT: 1 1 0.50 sbbw $0, %di
@@ -1710,8 +1710,8 @@ xorq (%rax), %rdi
# CHECK-NEXT: 5 12 0.50 * * sbbw $7, (%rax)
# CHECK-NEXT: 5 12 0.50 * * lock sbbw $7, (%rax)
# CHECK-NEXT: 1 1 0.50 sbbw %si, %di
-# CHECK-NEXT: 6 12 0.60 * * sbbw %si, (%rax)
-# CHECK-NEXT: 6 12 0.60 * * lock sbbw %si, (%rax)
+# CHECK-NEXT: 6 7 0.60 * * sbbw %si, (%rax)
+# CHECK-NEXT: 6 7 0.60 * * lock sbbw %si, (%rax)
# CHECK-NEXT: 2 6 0.50 * sbbw (%rax), %di
# CHECK-NEXT: 1 1 0.50 sbbl $0, %eax
# CHECK-NEXT: 1 1 0.50 sbbl $0, %edi
@@ -1725,8 +1725,8 @@ xorq (%rax), %rdi
# CHECK-NEXT: 5 12 0.50 * * sbbl $7, (%rax)
# CHECK-NEXT: 5 12 0.50 * * lock sbbl $7, (%rax)
# CHECK-NEXT: 1 1 0.50 sbbl %esi, %edi
-# CHECK-NEXT: 6 12 0.60 * * sbbl %esi, (%rax)
-# CHECK-NEXT: 6 12 0.60 * * lock sbbl %esi, (%rax)
+# CHECK-NEXT: 6 7 0.60 * * sbbl %esi, (%rax)
+# CHECK-NEXT: 6 7 0.60 * * lock sbbl %esi, (%rax)
# CHECK-NEXT: 2 6 0.50 * sbbl (%rax), %edi
# CHECK-NEXT: 1 1 0.50 sbbq $0, %rax
# CHECK-NEXT: 1 1 0.50 sbbq $0, %rdi
@@ -1740,46 +1740,46 @@ xorq (%rax), %rdi
# CHECK-NEXT: 5 12 0.50 * * sbbq $7, (%rax)
# CHECK-NEXT: 5 12 0.50 * * lock sbbq $7, (%rax)
# CHECK-NEXT: 1 1 0.50 sbbq %rsi, %rdi
-# CHECK-NEXT: 6 12 0.60 * * sbbq %rsi, (%rax)
-# CHECK-NEXT: 6 12 0.60 * * lock sbbq %rsi, (%rax)
+# CHECK-NEXT: 6 7 0.60 * * sbbq %rsi, (%rax)
+# CHECK-NEXT: 6 7 0.60 * * lock sbbq %rsi, (%rax)
# CHECK-NEXT: 2 6 0.50 * sbbq (%rax), %rdi
# CHECK-NEXT: 4 6 0.60 U scasb %es:(%rdi), %al
# CHECK-NEXT: 4 6 0.60 U scasw %es:(%rdi), %ax
# CHECK-NEXT: 4 6 0.60 U scasl %es:(%rdi), %eax
# CHECK-NEXT: 4 6 0.60 U scasq %es:(%rdi), %rax
-# CHECK-NEXT: 2 2 1.00 seto %al
-# CHECK-NEXT: 4 13 1.00 * seto (%rax)
-# CHECK-NEXT: 2 2 1.00 setno %al
-# CHECK-NEXT: 4 13 1.00 * setno (%rax)
-# CHECK-NEXT: 2 2 1.00 setb %al
-# CHECK-NEXT: 4 13 1.00 * setb (%rax)
-# CHECK-NEXT: 2 2 1.00 setae %al
-# CHECK-NEXT: 4 13 1.00 * setae (%rax)
-# CHECK-NEXT: 2 2 1.00 sete %al
-# CHECK-NEXT: 4 13 1.00 * sete (%rax)
-# CHECK-NEXT: 2 2 1.00 setne %al
-# CHECK-NEXT: 4 13 1.00 * setne (%rax)
-# CHECK-NEXT: 2 2 1.00 seta %al
-# CHECK-NEXT: 4 13 1.00 * seta (%rax)
-# CHECK-NEXT: 2 2 1.00 setbe %al
-# CHECK-NEXT: 4 13 1.00 * setbe (%rax)
-# CHECK-NEXT: 2 2 1.00 sets %al
-# CHECK-NEXT: 4 13 1.00 * sets (%rax)
-# CHECK-NEXT: 2 2 1.00 setns %al
-# CHECK-NEXT: 4 13 1.00 * setns (%rax)
-# CHECK-NEXT: 2 2 1.00 setp %al
-# CHECK-NEXT: 4 13 1.00 * setp (%rax)
-# CHECK-NEXT: 2 2 1.00 setnp %al
-# CHECK-NEXT: 4 13 1.00 * setnp (%rax)
-# CHECK-NEXT: 2 2 1.00 setl %al
-# CHECK-NEXT: 4 13 1.00 * setl (%rax)
-# CHECK-NEXT: 2 2 1.00 setge %al
-# CHECK-NEXT: 4 13 1.00 * setge (%rax)
-# CHECK-NEXT: 2 2 1.00 setg %al
-# CHECK-NEXT: 4 13 1.00 * setg (%rax)
-# CHECK-NEXT: 2 2 1.00 setle %al
-# CHECK-NEXT: 4 13 1.00 * setle (%rax)
-# CHECK-NEXT: 3 5 1.00 shldw %cl, %si, %di
+# CHECK-NEXT: 1 1 0.50 seto %al
+# CHECK-NEXT: 3 2 0.50 * seto (%rax)
+# CHECK-NEXT: 1 1 0.50 setno %al
+# CHECK-NEXT: 3 2 0.50 * setno (%rax)
+# CHECK-NEXT: 1 1 0.50 setb %al
+# CHECK-NEXT: 3 2 0.50 * setb (%rax)
+# CHECK-NEXT: 1 1 0.50 setae %al
+# CHECK-NEXT: 3 2 0.50 * setae (%rax)
+# CHECK-NEXT: 1 1 0.50 sete %al
+# CHECK-NEXT: 3 2 0.50 * sete (%rax)
+# CHECK-NEXT: 1 1 0.50 setne %al
+# CHECK-NEXT: 3 2 0.50 * setne (%rax)
+# CHECK-NEXT: 1 1 0.50 seta %al
+# CHECK-NEXT: 3 2 0.50 * seta (%rax)
+# CHECK-NEXT: 1 1 0.50 setbe %al
+# CHECK-NEXT: 3 2 0.50 * setbe (%rax)
+# CHECK-NEXT: 1 1 0.50 sets %al
+# CHECK-NEXT: 3 2 0.50 * sets (%rax)
+# CHECK-NEXT: 1 1 0.50 setns %al
+# CHECK-NEXT: 3 2 0.50 * setns (%rax)
+# CHECK-NEXT: 1 1 0.50 setp %al
+# CHECK-NEXT: 3 2 0.50 * setp (%rax)
+# CHECK-NEXT: 1 1 0.50 setnp %al
+# CHECK-NEXT: 3 2 0.50 * setnp (%rax)
+# CHECK-NEXT: 1 1 0.50 setl %al
+# CHECK-NEXT: 3 2 0.50 * setl (%rax)
+# CHECK-NEXT: 1 1 0.50 setge %al
+# CHECK-NEXT: 3 2 0.50 * setge (%rax)
+# CHECK-NEXT: 1 1 0.50 setg %al
+# CHECK-NEXT: 3 2 0.50 * setg (%rax)
+# CHECK-NEXT: 1 1 0.50 setle %al
+# CHECK-NEXT: 3 2 0.50 * setle (%rax)
+# CHECK-NEXT: 3 4 1.00 shldw %cl, %si, %di
# CHECK-NEXT: 3 5 1.00 shrdw %cl, %si, %di
# CHECK-NEXT: 6 12 1.00 * * shldw %cl, %si, (%rax)
# CHECK-NEXT: 6 12 1.00 * * shrdw %cl, %si, (%rax)
@@ -1787,16 +1787,16 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 3 1.00 shrdw $7, %si, %di
# CHECK-NEXT: 5 12 1.00 * * shldw $7, %si, (%rax)
# CHECK-NEXT: 5 13 1.00 * * shrdw $7, %si, (%rax)
-# CHECK-NEXT: 3 5 1.00 shldl %cl, %esi, %edi
-# CHECK-NEXT: 3 5 1.00 shrdl %cl, %esi, %edi
+# CHECK-NEXT: 3 4 1.00 shldl %cl, %esi, %edi
+# CHECK-NEXT: 3 4 1.00 shrdl %cl, %esi, %edi
# CHECK-NEXT: 6 12 1.00 * * shldl %cl, %esi, (%rax)
# CHECK-NEXT: 6 12 1.00 * * shrdl %cl, %esi, (%rax)
# CHECK-NEXT: 1 3 1.00 shldl $7, %esi, %edi
# CHECK-NEXT: 1 3 1.00 shrdl $7, %esi, %edi
# CHECK-NEXT: 5 12 1.00 * * shldl $7, %esi, (%rax)
# CHECK-NEXT: 5 12 1.00 * * shrdl $7, %esi, (%rax)
-# CHECK-NEXT: 3 5 1.00 shldq %cl, %rsi, %rdi
-# CHECK-NEXT: 3 5 1.00 shrdq %cl, %rsi, %rdi
+# CHECK-NEXT: 3 4 1.00 shldq %cl, %rsi, %rdi
+# CHECK-NEXT: 3 4 1.00 shrdq %cl, %rsi, %rdi
# CHECK-NEXT: 6 12 1.00 * * shldq %cl, %rsi, (%rax)
# CHECK-NEXT: 6 12 1.00 * * shrdq %cl, %rsi, (%rax)
# CHECK-NEXT: 1 3 1.00 shldq $7, %rsi, %rdi
@@ -1805,91 +1805,91 @@ xorq (%rax), %rdi
# CHECK-NEXT: 5 12 1.00 * * shrdq $7, %rsi, (%rax)
# CHECK-NEXT: 1 1 0.20 U stc
# CHECK-NEXT: 2 6 0.50 U std
-# CHECK-NEXT: 4 8 0.50 U stosb %al, %es:(%rdi)
+# CHECK-NEXT: 1 6 0.33 U stosb %al, %es:(%rdi)
# CHECK-NEXT: 4 7 0.50 U stosw %ax, %es:(%rdi)
# CHECK-NEXT: 4 7 0.50 U stosl %eax, %es:(%rdi)
# CHECK-NEXT: 4 7 0.50 U stosq %rax, %es:(%rdi)
# CHECK-NEXT: 1 1 0.20 subb $7, %al
# CHECK-NEXT: 1 1 0.20 subb $7, %dil
-# CHECK-NEXT: 4 13 0.50 * * subb $7, (%rax)
-# CHECK-NEXT: 4 13 0.50 * * lock subb $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * subb $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock subb $7, (%rax)
# CHECK-NEXT: 1 1 0.20 subb %sil, %dil
-# CHECK-NEXT: 4 13 0.50 * * subb %sil, (%rax)
-# CHECK-NEXT: 4 13 0.50 * * lock subb %sil, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * subb %sil, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock subb %sil, (%rax)
# CHECK-NEXT: 2 6 0.33 * subb (%rax), %dil
# CHECK-NEXT: 1 1 0.20 subw $511, %ax
# CHECK-NEXT: 1 1 0.20 subw $511, %di
-# CHECK-NEXT: 4 12 0.50 * * subw $511, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock subw $511, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * subw $511, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock subw $511, (%rax)
# CHECK-NEXT: 1 1 0.20 subw $7, %di
-# CHECK-NEXT: 4 12 0.50 * * subw $7, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock subw $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * subw $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock subw $7, (%rax)
# CHECK-NEXT: 1 1 0.20 subw %si, %di
-# CHECK-NEXT: 4 12 0.50 * * subw %si, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock subw %si, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * subw %si, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock subw %si, (%rax)
# CHECK-NEXT: 2 6 0.33 * subw (%rax), %di
# CHECK-NEXT: 1 1 0.20 subl $665536, %eax
# CHECK-NEXT: 1 1 0.20 subl $665536, %edi
-# CHECK-NEXT: 4 12 0.50 * * subl $665536, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock subl $665536, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * subl $665536, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock subl $665536, (%rax)
# CHECK-NEXT: 1 1 0.20 subl $7, %edi
-# CHECK-NEXT: 4 12 0.50 * * subl $7, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock subl $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * subl $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock subl $7, (%rax)
# CHECK-NEXT: 1 1 0.20 subl %esi, %edi
-# CHECK-NEXT: 4 12 0.50 * * subl %esi, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock subl %esi, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * subl %esi, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock subl %esi, (%rax)
# CHECK-NEXT: 2 6 0.33 * subl (%rax), %edi
# CHECK-NEXT: 1 1 0.20 subq $665536, %rax
# CHECK-NEXT: 1 1 0.20 subq $665536, %rdi
-# CHECK-NEXT: 4 12 0.50 * * subq $665536, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock subq $665536, (%rax)
-# CHECK-NEXT: 0 1 0.00 subq $7, %rdi
-# CHECK-NEXT: 4 12 0.50 * * subq $7, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock subq $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * subq $665536, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock subq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.20 subq $7, %rdi
+# CHECK-NEXT: 4 7 0.50 * * subq $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock subq $7, (%rax)
# CHECK-NEXT: 1 1 0.20 subq %rsi, %rdi
-# CHECK-NEXT: 4 12 0.50 * * subq %rsi, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock subq %rsi, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * subq %rsi, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock subq %rsi, (%rax)
# CHECK-NEXT: 2 6 0.33 * subq (%rax), %rdi
-# CHECK-NEXT: 1 2 0.20 testb $7, %al
-# CHECK-NEXT: 1 2 0.20 testb $7, %dil
-# CHECK-NEXT: 2 7 0.33 * testb $7, (%rax)
-# CHECK-NEXT: 1 2 0.20 testb %sil, %dil
-# CHECK-NEXT: 2 7 0.33 * testb %sil, (%rax)
+# CHECK-NEXT: 1 1 0.20 testb $7, %al
+# CHECK-NEXT: 1 1 0.20 testb $7, %dil
+# CHECK-NEXT: 2 6 0.33 * testb $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 testb %sil, %dil
+# CHECK-NEXT: 2 6 0.33 * testb %sil, (%rax)
# CHECK-NEXT: 1 1 0.20 testw $511, %ax
# CHECK-NEXT: 1 1 0.20 testw $511, %di
-# CHECK-NEXT: 2 7 0.33 * testw $511, (%rax)
+# CHECK-NEXT: 2 6 0.33 * testw $511, (%rax)
# CHECK-NEXT: 1 1 0.20 testw $7, %di
-# CHECK-NEXT: 2 7 0.33 * testw $7, (%rax)
-# CHECK-NEXT: 1 2 0.20 testw %si, %di
-# CHECK-NEXT: 2 7 0.33 * testw %si, (%rax)
+# CHECK-NEXT: 2 6 0.33 * testw $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 testw %si, %di
+# CHECK-NEXT: 2 6 0.33 * testw %si, (%rax)
# CHECK-NEXT: 1 2 0.20 testl $665536, %eax
-# CHECK-NEXT: 1 2 0.20 testl $665536, %edi
-# CHECK-NEXT: 2 7 0.33 * testl $665536, (%rax)
-# CHECK-NEXT: 1 2 0.20 testl $7, %edi
-# CHECK-NEXT: 2 7 0.33 * testl $7, (%rax)
-# CHECK-NEXT: 1 2 0.20 testl %esi, %edi
-# CHECK-NEXT: 2 7 0.33 * testl %esi, (%rax)
+# CHECK-NEXT: 1 1 0.20 testl $665536, %edi
+# CHECK-NEXT: 2 6 0.33 * testl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.20 testl $7, %edi
+# CHECK-NEXT: 2 6 0.33 * testl $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 testl %esi, %edi
+# CHECK-NEXT: 2 6 0.33 * testl %esi, (%rax)
# CHECK-NEXT: 1 2 0.20 testq $665536, %rax
-# CHECK-NEXT: 1 2 0.20 testq $665536, %rdi
-# CHECK-NEXT: 2 7 0.33 * testq $665536, (%rax)
-# CHECK-NEXT: 1 2 0.20 testq $7, %rdi
-# CHECK-NEXT: 2 7 0.33 * testq $7, (%rax)
-# CHECK-NEXT: 1 2 0.20 testq %rsi, %rdi
-# CHECK-NEXT: 2 7 0.33 * testq %rsi, (%rax)
+# CHECK-NEXT: 1 1 0.20 testq $665536, %rdi
+# CHECK-NEXT: 2 6 0.33 * testq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.20 testq $7, %rdi
+# CHECK-NEXT: 2 6 0.33 * testq $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 testq %rsi, %rdi
+# CHECK-NEXT: 2 6 0.33 * testq %rsi, (%rax)
# CHECK-NEXT: 1 100 0.25 * U ud2
# CHECK-NEXT: 144 100 35.50 U wrmsr
# CHECK-NEXT: 3 2 0.60 xaddb %bl, %cl
-# CHECK-NEXT: 5 13 0.50 * * xaddb %bl, (%rcx)
-# CHECK-NEXT: 5 13 0.50 * * lock xaddb %bl, (%rcx)
+# CHECK-NEXT: 5 7 0.50 * * xaddb %bl, (%rcx)
+# CHECK-NEXT: 5 7 0.50 * * lock xaddb %bl, (%rcx)
# CHECK-NEXT: 3 2 0.60 xaddw %bx, %cx
-# CHECK-NEXT: 5 12 0.50 * * xaddw %ax, (%rbx)
-# CHECK-NEXT: 5 12 0.50 * * lock xaddw %ax, (%rbx)
+# CHECK-NEXT: 5 7 0.50 * * xaddw %ax, (%rbx)
+# CHECK-NEXT: 5 7 0.50 * * lock xaddw %ax, (%rbx)
# CHECK-NEXT: 3 2 0.60 xaddl %ebx, %ecx
-# CHECK-NEXT: 5 12 0.50 * * xaddl %eax, (%rbx)
-# CHECK-NEXT: 5 12 0.50 * * lock xaddl %eax, (%rbx)
+# CHECK-NEXT: 5 7 0.50 * * xaddl %eax, (%rbx)
+# CHECK-NEXT: 5 7 0.50 * * lock xaddl %eax, (%rbx)
# CHECK-NEXT: 3 2 0.60 xaddq %rbx, %rcx
-# CHECK-NEXT: 5 12 0.50 * * xaddq %rax, (%rbx)
-# CHECK-NEXT: 5 12 0.50 * * lock xaddq %rax, (%rbx)
+# CHECK-NEXT: 5 7 0.50 * * xaddq %rax, (%rbx)
+# CHECK-NEXT: 5 7 0.50 * * lock xaddq %rax, (%rbx)
# CHECK-NEXT: 3 2 0.60 xchgb %bl, %cl
# CHECK-NEXT: 8 40 1.00 * * xchgb %bl, (%rbx)
# CHECK-NEXT: 8 40 1.00 * * lock xchgb %bl, (%rbx)
@@ -1906,47 +1906,47 @@ xorq (%rax), %rdi
# CHECK-NEXT: 9 39 1.20 * * xchgq %rax, (%rbx)
# CHECK-NEXT: 9 39 1.20 * * lock xchgq %rax, (%rbx)
# CHECK-NEXT: 3 7 0.40 * xlatb
-# CHECK-NEXT: 1 2 0.20 xorb $7, %al
-# CHECK-NEXT: 1 2 0.20 xorb $7, %dil
-# CHECK-NEXT: 4 13 0.50 * * xorb $7, (%rax)
-# CHECK-NEXT: 4 13 0.50 * * lock xorb $7, (%rax)
-# CHECK-NEXT: 1 2 0.20 xorb %sil, %dil
-# CHECK-NEXT: 4 13 0.50 * * xorb %sil, (%rax)
-# CHECK-NEXT: 4 13 0.50 * * lock xorb %sil, (%rax)
+# CHECK-NEXT: 1 1 0.20 xorb $7, %al
+# CHECK-NEXT: 1 1 0.20 xorb $7, %dil
+# CHECK-NEXT: 4 7 0.50 * * xorb $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock xorb $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 xorb %sil, %dil
+# CHECK-NEXT: 4 7 0.50 * * xorb %sil, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock xorb %sil, (%rax)
# CHECK-NEXT: 2 6 0.33 * xorb (%rax), %dil
# CHECK-NEXT: 1 1 0.20 xorw $511, %ax
# CHECK-NEXT: 1 1 0.20 xorw $511, %di
-# CHECK-NEXT: 4 12 0.50 * * xorw $511, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock xorw $511, (%rax)
-# CHECK-NEXT: 1 2 0.20 xorw $7, %di
-# CHECK-NEXT: 4 12 0.50 * * xorw $7, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock xorw $7, (%rax)
-# CHECK-NEXT: 1 2 0.20 xorw %si, %di
-# CHECK-NEXT: 4 12 0.50 * * xorw %si, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock xorw %si, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * xorw $511, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock xorw $511, (%rax)
+# CHECK-NEXT: 1 1 0.20 xorw $7, %di
+# CHECK-NEXT: 4 7 0.50 * * xorw $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock xorw $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 xorw %si, %di
+# CHECK-NEXT: 4 7 0.50 * * xorw %si, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock xorw %si, (%rax)
# CHECK-NEXT: 2 6 0.33 * xorw (%rax), %di
# CHECK-NEXT: 1 2 0.20 xorl $665536, %eax
-# CHECK-NEXT: 1 2 0.20 xorl $665536, %edi
-# CHECK-NEXT: 4 12 0.50 * * xorl $665536, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock xorl $665536, (%rax)
-# CHECK-NEXT: 1 2 0.20 xorl $7, %edi
-# CHECK-NEXT: 4 12 0.50 * * xorl $7, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock xorl $7, (%rax)
-# CHECK-NEXT: 1 2 0.20 xorl %esi, %edi
-# CHECK-NEXT: 4 12 0.50 * * xorl %esi, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock xorl %esi, (%rax)
+# CHECK-NEXT: 1 1 0.20 xorl $665536, %edi
+# CHECK-NEXT: 4 7 0.50 * * xorl $665536, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock xorl $665536, (%rax)
+# CHECK-NEXT: 1 1 0.20 xorl $7, %edi
+# CHECK-NEXT: 4 7 0.50 * * xorl $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock xorl $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 xorl %esi, %edi
+# CHECK-NEXT: 4 7 0.50 * * xorl %esi, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock xorl %esi, (%rax)
# CHECK-NEXT: 2 6 0.33 * xorl (%rax), %edi
# CHECK-NEXT: 1 2 0.20 xorq $665536, %rax
-# CHECK-NEXT: 1 2 0.20 xorq $665536, %rdi
-# CHECK-NEXT: 4 12 0.50 * * xorq $665536, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock xorq $665536, (%rax)
-# CHECK-NEXT: 1 2 0.20 xorq $7, %rdi
-# CHECK-NEXT: 4 12 0.50 * * xorq $7, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock xorq $7, (%rax)
-# CHECK-NEXT: 1 2 0.20 xorq %rsi, %rdi
-# CHECK-NEXT: 4 12 0.50 * * xorq %rsi, (%rax)
-# CHECK-NEXT: 4 12 0.50 * * lock xorq %rsi, (%rax)
-# CHECK-NEXT: 2 7 0.33 * xorq (%rax), %rdi
+# CHECK-NEXT: 1 1 0.20 xorq $665536, %rdi
+# CHECK-NEXT: 4 7 0.50 * * xorq $665536, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock xorq $665536, (%rax)
+# CHECK-NEXT: 1 1 0.20 xorq $7, %rdi
+# CHECK-NEXT: 4 7 0.50 * * xorq $7, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock xorq $7, (%rax)
+# CHECK-NEXT: 1 1 0.20 xorq %rsi, %rdi
+# CHECK-NEXT: 4 7 0.50 * * xorq %rsi, (%rax)
+# CHECK-NEXT: 4 7 0.50 * * lock xorq %rsi, (%rax)
+# CHECK-NEXT: 2 6 0.33 * xorq (%rax), %rdi
# CHECK: Resources:
# CHECK-NEXT: [0] - ADLPPort00
@@ -1965,7 +1965,7 @@ xorq (%rax), %rdi
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
-# CHECK-NEXT: 949.92 794.58 213.00 213.00 202.50 599.75 793.42 203.00 203.00 202.50 191.33 213.00 -
+# CHECK-NEXT: 909.92 773.42 210.33 210.33 202.00 578.58 760.42 202.50 202.50 202.00 192.67 210.33 -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
@@ -2060,7 +2060,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - addq $665536, %rdi
# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - addq $665536, (%rax)
# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock addq $665536, (%rax)
-# CHECK-NEXT: - - - - - - - - - - - - - addq $7, %rdi
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - addq $7, %rdi
# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - addq $7, (%rax)
# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock addq $7, (%rax)
# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - addq %rsi, %rdi
@@ -2188,9 +2188,9 @@ xorq (%rax), %rdi
# CHECK-NEXT: - 1.00 0.33 0.33 0.50 - - 0.50 0.50 0.50 - 0.33 - lock btcq $7, (%rax)
# CHECK-NEXT: - 1.00 0.33 0.33 0.50 - - 0.50 0.50 0.50 - 0.33 - lock btrq $7, (%rax)
# CHECK-NEXT: - 1.00 0.33 0.33 0.50 - - 0.50 0.50 0.50 - 0.33 - lock btsq $7, (%rax)
-# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - cbtw
-# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - cwtl
-# CHECK-NEXT: - 0.50 - - - 0.50 - - - - - - - cltq
+# CHECK-NEXT: - 0.33 - - - 0.33 - - - - 0.33 - - cbtw
+# CHECK-NEXT: - 0.33 - - - 0.33 - - - - 0.33 - - cwtl
+# CHECK-NEXT: - 0.33 - - - 0.33 - - - - 0.33 - - cltq
# CHECK-NEXT: 0.70 0.20 - - - 0.20 0.70 - - - 0.20 - - cwtd
# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cltd
# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - cqto
@@ -2253,26 +2253,26 @@ xorq (%rax), %rdi
# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - decl %edi
# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - decl (%rax)
# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock decl (%rax)
-# CHECK-NEXT: - - - - - - - - - - - - - decq %rdi
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - decq %rdi
# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - decq (%rax)
# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock decq (%rax)
-# CHECK-NEXT: - 3.00 - - - - - - - - - - - divb %dil
-# CHECK-NEXT: - 3.00 - - - - - - - - - - - divb (%rax)
+# CHECK-NEXT: 0.20 3.20 - - - 0.20 0.20 - - - 0.20 - - divb %dil
+# CHECK-NEXT: 0.20 3.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - divb (%rax)
# CHECK-NEXT: 0.20 3.20 - - - 0.20 0.20 - - - 0.20 - - divw %si
# CHECK-NEXT: 0.20 3.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - divw (%rax)
# CHECK-NEXT: 0.20 3.20 - - - 0.20 0.20 - - - 0.20 - - divl %edx
# CHECK-NEXT: 0.20 3.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - divl (%rax)
-# CHECK-NEXT: - 3.00 - - - - - - - - - - - divq %rcx
-# CHECK-NEXT: - 3.00 0.33 0.33 - - - - - - - 0.33 - divq (%rax)
+# CHECK-NEXT: 0.20 3.20 - - - 0.20 0.20 - - - 0.20 - - divq %rcx
+# CHECK-NEXT: 0.20 3.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - divq (%rax)
# CHECK-NEXT: 12.50 2.00 4.67 4.67 2.00 9.00 10.50 2.50 2.50 2.00 - 4.67 - enter $7, $4095
-# CHECK-NEXT: - 3.00 - - - - - - - - - - - idivb %dil
-# CHECK-NEXT: - 3.00 - - - - - - - - - - - idivb (%rax)
+# CHECK-NEXT: 0.20 3.20 - - - 0.20 0.20 - - - 0.20 - - idivb %dil
+# CHECK-NEXT: 0.20 3.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - idivb (%rax)
# CHECK-NEXT: 0.20 3.20 - - - 0.20 0.20 - - - 0.20 - - idivw %si
# CHECK-NEXT: 0.20 3.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - idivw (%rax)
# CHECK-NEXT: 0.20 3.20 - - - 0.20 0.20 - - - 0.20 - - idivl %edx
# CHECK-NEXT: 0.20 3.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - idivl (%rax)
-# CHECK-NEXT: - 3.00 - - - - - - - - - - - idivq %rcx
-# CHECK-NEXT: - 3.00 0.33 0.33 - - - - - - - 0.33 - idivq (%rax)
+# CHECK-NEXT: 0.20 3.20 - - - 0.20 0.20 - - - 0.20 - - idivq %rcx
+# CHECK-NEXT: 0.20 3.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - idivq (%rax)
# CHECK-NEXT: - 1.00 - - - - - - - - - - - imulb %dil
# CHECK-NEXT: - 1.00 0.33 0.33 - - - - - - - 0.33 - imulb (%rax)
# CHECK-NEXT: 0.90 1.40 - - - 0.40 0.90 - - - 0.40 - - imulw %di
@@ -2304,7 +2304,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 21.00 20.67 2.33 2.33 - 22.67 14.00 - - - 1.67 2.33 - inw $7, %ax
# CHECK-NEXT: 21.30 21.30 2.33 2.33 - 21.80 13.80 - - - 1.80 2.33 - inw %dx, %ax
# CHECK-NEXT: 22.20 22.87 3.33 3.33 - 21.87 15.20 - - - 1.87 3.33 - inl $7, %eax
-# CHECK-NEXT: 22.80 23.47 3.67 3.67 - 23.47 15.80 - - - 2.47 3.67 - inl %dx, %eax
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - inl %dx, %eax
# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - incb %dil
# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - incb (%rax)
# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock incb (%rax)
@@ -2314,7 +2314,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - incl %edi
# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - incl (%rax)
# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock incl (%rax)
-# CHECK-NEXT: - - - - - - - - - - - - - incq %rdi
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - incq %rdi
# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - incq (%rax)
# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock incq (%rax)
# CHECK-NEXT: 20.20 18.20 2.67 2.67 0.50 20.20 13.20 0.50 0.50 0.50 1.20 2.67 - insb %dx, %es:(%rdi)
@@ -2504,8 +2504,8 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rorb %dil
# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rolb (%rax)
# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rorb (%rax)
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rolb $7, %dil
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rorb $7, %dil
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - rolb $7, %dil
+# CHECK-NEXT: 0.90 0.40 - - - 0.40 0.90 - - - 0.40 - - rorb $7, %dil
# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rolb $7, (%rax)
# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rorb $7, (%rax)
# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rolb %cl, %dil
@@ -2516,8 +2516,8 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rorw %di
# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rolw (%rax)
# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rorw (%rax)
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rolw $7, %di
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rorw $7, %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - rolw $7, %di
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - rorw $7, %di
# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rolw $7, (%rax)
# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rorw $7, (%rax)
# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rolw %cl, %di
@@ -2528,8 +2528,8 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rorl %edi
# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - roll (%rax)
# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rorl (%rax)
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - roll $7, %edi
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rorl $7, %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - roll $7, %edi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - rorl $7, %edi
# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - roll $7, (%rax)
# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rorl $7, (%rax)
# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - roll %cl, %edi
@@ -2540,8 +2540,8 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rorq %rdi
# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rolq (%rax)
# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rorq (%rax)
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rolq $7, %rdi
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rorq $7, %rdi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - rolq $7, %rdi
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - rorq $7, %rdi
# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rolq $7, (%rax)
# CHECK-NEXT: 1.00 - 0.33 0.33 0.50 - 1.00 0.50 0.50 0.50 - 0.33 - rorq $7, (%rax)
# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - rolq %cl, %rdi
@@ -2682,38 +2682,38 @@ xorq (%rax), %rdi
# CHECK-NEXT: 0.60 0.60 0.33 0.33 - 0.60 0.60 - - - 0.60 0.33 - scasw %es:(%rdi), %ax
# CHECK-NEXT: 0.60 0.60 0.33 0.33 - 0.60 0.60 - - - 0.60 0.33 - scasl %es:(%rdi), %eax
# CHECK-NEXT: 0.60 0.60 0.33 0.33 - 0.60 0.60 - - - 0.60 0.33 - scasq %es:(%rdi), %rax
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - seto %al
-# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - seto (%rax)
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setno %al
-# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setno (%rax)
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setb %al
-# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setb (%rax)
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setae %al
-# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setae (%rax)
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - sete %al
-# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - sete (%rax)
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setne %al
-# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setne (%rax)
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - seta %al
-# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - seta (%rax)
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setbe %al
-# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setbe (%rax)
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - sets %al
-# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - sets (%rax)
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setns %al
-# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setns (%rax)
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setp %al
-# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setp (%rax)
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setnp %al
-# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setnp (%rax)
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setl %al
-# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setl (%rax)
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setge %al
-# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setge (%rax)
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setg %al
-# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setg (%rax)
-# CHECK-NEXT: 1.00 - - - - - 1.00 - - - - - - setle %al
-# CHECK-NEXT: 1.00 - - - 0.50 - 1.00 0.50 0.50 0.50 - - - setle (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - seto %al
+# CHECK-NEXT: 0.50 - - - 0.50 - 0.50 0.50 0.50 0.50 - - - seto (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - setno %al
+# CHECK-NEXT: 0.50 - - - 0.50 - 0.50 0.50 0.50 0.50 - - - setno (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - setb %al
+# CHECK-NEXT: 0.50 - - - 0.50 - 0.50 0.50 0.50 0.50 - - - setb (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - setae %al
+# CHECK-NEXT: 0.50 - - - 0.50 - 0.50 0.50 0.50 0.50 - - - setae (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sete %al
+# CHECK-NEXT: 0.50 - - - 0.50 - 0.50 0.50 0.50 0.50 - - - sete (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - setne %al
+# CHECK-NEXT: 0.50 - - - 0.50 - 0.50 0.50 0.50 0.50 - - - setne (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - seta %al
+# CHECK-NEXT: 0.50 - - - 0.50 - 0.50 0.50 0.50 0.50 - - - seta (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - setbe %al
+# CHECK-NEXT: 0.50 - - - 0.50 - 0.50 0.50 0.50 0.50 - - - setbe (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - sets %al
+# CHECK-NEXT: 0.50 - - - 0.50 - 0.50 0.50 0.50 0.50 - - - sets (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - setns %al
+# CHECK-NEXT: 0.50 - - - 0.50 - 0.50 0.50 0.50 0.50 - - - setns (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - setp %al
+# CHECK-NEXT: 0.50 - - - 0.50 - 0.50 0.50 0.50 0.50 - - - setp (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - setnp %al
+# CHECK-NEXT: 0.50 - - - 0.50 - 0.50 0.50 0.50 0.50 - - - setnp (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - setl %al
+# CHECK-NEXT: 0.50 - - - 0.50 - 0.50 0.50 0.50 0.50 - - - setl (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - setge %al
+# CHECK-NEXT: 0.50 - - - 0.50 - 0.50 0.50 0.50 0.50 - - - setge (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - setg %al
+# CHECK-NEXT: 0.50 - - - 0.50 - 0.50 0.50 0.50 0.50 - - - setg (%rax)
+# CHECK-NEXT: 0.50 - - - - - 0.50 - - - - - - setle %al
+# CHECK-NEXT: 0.50 - - - 0.50 - 0.50 0.50 0.50 0.50 - - - setle (%rax)
# CHECK-NEXT: 0.70 1.20 - - - 0.20 0.70 - - - 0.20 - - shldw %cl, %si, %di
# CHECK-NEXT: 0.70 1.20 - - - 0.20 0.70 - - - 0.20 - - shrdw %cl, %si, %di
# CHECK-NEXT: 0.70 1.20 0.33 0.33 0.50 0.20 0.70 0.50 0.50 0.50 0.20 0.33 - shldw %cl, %si, (%rax)
@@ -2740,7 +2740,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 0.20 1.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - shrdq $7, %rsi, (%rax)
# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - stc
# CHECK-NEXT: 0.70 0.20 - - - 0.20 0.70 - - - 0.20 - - std
-# CHECK-NEXT: 0.40 0.40 - - 0.50 0.40 0.40 0.50 0.50 0.50 0.40 - - stosb %al, %es:(%rdi)
+# CHECK-NEXT: 0.20 0.20 0.33 0.33 - 0.20 0.20 - - - 0.20 0.33 - stosb %al, %es:(%rdi)
# CHECK-NEXT: 0.40 0.40 - - 0.50 0.40 0.40 0.50 0.50 0.50 0.40 - - stosw %ax, %es:(%rdi)
# CHECK-NEXT: 0.40 0.40 - - 0.50 0.40 0.40 0.50 0.50 0.50 0.40 - - stosl %eax, %es:(%rdi)
# CHECK-NEXT: 0.40 0.40 - - 0.50 0.40 0.40 0.50 0.50 0.50 0.40 - - stosq %rax, %es:(%rdi)
@@ -2778,7 +2778,7 @@ xorq (%rax), %rdi
# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - subq $665536, %rdi
# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - subq $665536, (%rax)
# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock subq $665536, (%rax)
-# CHECK-NEXT: - - - - - - - - - - - - - subq $7, %rdi
+# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - subq $7, %rdi
# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - subq $7, (%rax)
# CHECK-NEXT: 0.20 0.20 0.33 0.33 0.50 0.20 0.20 0.50 0.50 0.50 0.20 0.33 - lock subq $7, (%rax)
# CHECK-NEXT: 0.20 0.20 - - - 0.20 0.20 - - - 0.20 - - subq %rsi, %rdi
diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/zero-idioms.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/zero-idioms.s
index 90fea632be66..bb0c4bfb4ac2 100644
--- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/zero-idioms.s
+++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/zero-idioms.s
@@ -124,8 +124,8 @@ vpxor %ymm3, %ymm3, %ymm5
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 1 0.20 subl %eax, %eax
# CHECK-NEXT: 1 1 0.20 subq %rax, %rax
-# CHECK-NEXT: 1 2 0.20 xorl %eax, %eax
-# CHECK-NEXT: 1 2 0.20 xorq %rax, %rax
+# CHECK-NEXT: 1 1 0.20 xorl %eax, %eax
+# CHECK-NEXT: 1 1 0.20 xorq %rax, %rax
# CHECK-NEXT: 1 1 1.00 pcmpgtb %mm2, %mm2
# CHECK-NEXT: 1 1 1.00 pcmpgtd %mm2, %mm2
# CHECK-NEXT: 1 1 1.00 pcmpgtw %mm2, %mm2
@@ -321,13 +321,13 @@ vpxor %ymm3, %ymm3, %ymm5
# CHECK: [0,0] DeER . . . . . . . subl %eax, %eax
# CHECK-NEXT: [0,1] D=eER. . . . . . . subq %rax, %rax
-# CHECK-NEXT: [0,2] D==eeER . . . . . . xorl %eax, %eax
-# CHECK-NEXT: [0,3] D====eeER . . . . . . xorq %rax, %rax
-# CHECK-NEXT: [0,4] DeE-----R . . . . . . pcmpgtb %mm2, %mm2
-# CHECK-NEXT: [0,5] D=eE----R . . . . . . pcmpgtd %mm2, %mm2
-# CHECK-NEXT: [0,6] .D=eE---R . . . . . . pcmpgtw %mm2, %mm2
-# CHECK-NEXT: [0,7] .DeE----R . . . . . . pcmpgtb %xmm2, %xmm2
-# CHECK-NEXT: [0,8] .D=eE---R . . . . . . pcmpgtd %xmm2, %xmm2
+# CHECK-NEXT: [0,2] D==eER . . . . . . xorl %eax, %eax
+# CHECK-NEXT: [0,3] D===eER . . . . . . xorq %rax, %rax
+# CHECK-NEXT: [0,4] DeE---R . . . . . . pcmpgtb %mm2, %mm2
+# CHECK-NEXT: [0,5] D=eE--R . . . . . . pcmpgtd %mm2, %mm2
+# CHECK-NEXT: [0,6] .D=eE-R . . . . . . pcmpgtw %mm2, %mm2
+# CHECK-NEXT: [0,7] .DeE--R . . . . . . pcmpgtb %xmm2, %xmm2
+# CHECK-NEXT: [0,8] .D=eE-R . . . . . . pcmpgtd %xmm2, %xmm2
# CHECK-NEXT: [0,9] .D==eeeER . . . . . . pcmpgtq %xmm2, %xmm2
# CHECK-NEXT: [0,10] .D=====eER. . . . . . pcmpgtw %xmm2, %xmm2
# CHECK-NEXT: [0,11] .D==eE---R. . . . . . vpcmpgtb %xmm3, %xmm3, %xmm3
@@ -413,12 +413,12 @@ vpxor %ymm3, %ymm3, %ymm5
# CHECK-NEXT: 0. 1 1.0 1.0 0.0 subl %eax, %eax
# CHECK-NEXT: 1. 1 2.0 0.0 0.0 subq %rax, %rax
# CHECK-NEXT: 2. 1 3.0 0.0 0.0 xorl %eax, %eax
-# CHECK-NEXT: 3. 1 5.0 0.0 0.0 xorq %rax, %rax
-# CHECK-NEXT: 4. 1 1.0 1.0 5.0 pcmpgtb %mm2, %mm2
-# CHECK-NEXT: 5. 1 2.0 0.0 4.0 pcmpgtd %mm2, %mm2
-# CHECK-NEXT: 6. 1 2.0 0.0 3.0 pcmpgtw %mm2, %mm2
-# CHECK-NEXT: 7. 1 1.0 1.0 4.0 pcmpgtb %xmm2, %xmm2
-# CHECK-NEXT: 8. 1 2.0 0.0 3.0 pcmpgtd %xmm2, %xmm2
+# CHECK-NEXT: 3. 1 4.0 0.0 0.0 xorq %rax, %rax
+# CHECK-NEXT: 4. 1 1.0 1.0 3.0 pcmpgtb %mm2, %mm2
+# CHECK-NEXT: 5. 1 2.0 0.0 2.0 pcmpgtd %mm2, %mm2
+# CHECK-NEXT: 6. 1 2.0 0.0 1.0 pcmpgtw %mm2, %mm2
+# CHECK-NEXT: 7. 1 1.0 1.0 2.0 pcmpgtb %xmm2, %xmm2
+# CHECK-NEXT: 8. 1 2.0 0.0 1.0 pcmpgtd %xmm2, %xmm2
# CHECK-NEXT: 9. 1 3.0 0.0 0.0 pcmpgtq %xmm2, %xmm2
# CHECK-NEXT: 10. 1 6.0 0.0 0.0 pcmpgtw %xmm2, %xmm2
# CHECK-NEXT: 11. 1 3.0 3.0 3.0 vpcmpgtb %xmm3, %xmm3, %xmm3
@@ -493,4 +493,4 @@ vpxor %ymm3, %ymm3, %ymm5
# CHECK-NEXT: 80. 1 9.0 0.0 9.0 vxorpd %ymm1, %ymm1, %ymm3
# CHECK-NEXT: 81. 1 11.0 1.0 7.0 vpxor %xmm3, %xmm3, %xmm5
# CHECK-NEXT: 82. 1 12.0 2.0 6.0 vpxor %ymm3, %ymm3, %ymm5
-# CHECK-NEXT: 1 9.4 1.0 5.0 <total>
+# CHECK-NEXT: 1 9.4 1.0 4.9 <total>
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