[PATCH] D136862: [AArch64][SME2] Add CodeGen support for target("aarch64.svcount").

Sander de Smalen via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Feb 28 09:47:43 PST 2023


sdesmalen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:420-421
+    addRegisterClass(MVT::aarch64svcount, &AArch64::PPRRegClass);
+    setOperationAction(ISD::LOAD, MVT::aarch64svcount, Custom);
+    setOperationAction(ISD::STORE, MVT::aarch64svcount, Custom);
+    setOperationAction(ISD::SELECT, MVT::aarch64svcount, Custom);
----------------
paulwalker-arm wrote:
> I've tried and now there is isel for `ISD::BITCAST` this can be
> ```
> setOperationPromotedToType(ISD::LOAD, MVT::aarch64svcount, MVT::nxv16i1);
> setOperationPromotedToType(ISD::STORE, MVT::aarch64svcount, MVT::nxv16i1);
> ```
I'm surprised this worked, as the term 'Promote' makes me think it only works on promoted (element) types, not a bitcast. I've removed the custom lowering code now.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:422-423
+    setOperationAction(ISD::STORE, MVT::aarch64svcount, Custom);
+    setOperationAction(ISD::SELECT, MVT::aarch64svcount, Custom);
+    setOperationAction(ISD::SELECT_CC, MVT::aarch64svcount, Expand);
+  }
----------------
paulwalker-arm wrote:
> Do code generation tests for these exist?
Thanks for the reminder, I previously added them as part of D136863. I've added them to this patch now.


================
Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:2537
+
+    def : Pat<(nxv16i1 (bitconvert (aarch64svcount PNR:$src))), (nxv16i1 PPR:$src)>;
+    def : Pat<(aarch64svcount (bitconvert (nxv16i1 PPR:$src))), (aarch64svcount PNR:$src)>;
----------------
paulwalker-arm wrote:
> Does `PNR` exist? or perhaps it's a typo? When experimenting with `setOperationPromotedToType` I hit build errors and had to change these entries.
Something probably went wrong with splitting up the patches after I tried adding the predicate-as-counter register class, fixed now.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136862/new/

https://reviews.llvm.org/D136862



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