[llvm] ac67ec3 - [LV] Reland testcase in 0ec4cae

[via llvm-commits]

Author: sgokhale
Date: 2023-02-28T18:14:18+05:30
New Revision: ac67ec3a5433e2859634dae4cb2a7e94f50695f8

URL: https://github.com/llvm/llvm-project/commit/ac67ec3a5433e2859634dae4cb2a7e94f50695f8
DIFF: https://github.com/llvm/llvm-project/commit/ac67ec3a5433e2859634dae4cb2a7e94f50695f8.diff

LOG: [LV] Reland testcase in 0ec4cae

Added: 
    

Modified: 
    llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll

Removed: 
    


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diff  --git a/llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll b/llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll
index 909cf21ca3d7..8239d32445c1 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/reg-usage.ll
@@ -17,8 +17,8 @@ define void @get_invariant_reg_usage(ptr %z) {
 ; CHECK-NEXT: LV(REG): Found max usage: 1 item
 ; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 3 registers
 ; CHECK-NEXT: LV(REG): Found invariant usage: 2 item
-; CHECK-NEXT: RegisterClass: Generic::ScalarRC, 2 registers
-; CHECK-NEXT: RegisterClass: Generic::VectorRC, 8 registers 
+; CHECK-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers
+; CHECK-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 8 registers 
 
 L.entry:
   %0 = load i128, ptr %z, align 16