[PATCH] D144956: Fix VGPR + offset Scratch offset folding

[Petar Avramovic via Phabricator via llvm-commits]

Petar.Avramovic created this revision.
Petar.Avramovic added reviewers: dstuttard, foad, AMDGPU.
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Values in VGPR register are treated as unsigned by hardware.

When value in 32-bit VGPR base can be negative calculate offset using
32-bit add instruction, otherwise use vgpr base(unsigned) + offset.
Does not affect case where whole offset comes from VGPR register
(immediate offset is 0).

LoopStrengthReduce.cpp changes offsets to negative and in some
iterations value in VGPR register could be negative.


https://reviews.llvm.org/D144956

Files:
  llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
  llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll
  llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
  llvm/test/CodeGen/AMDGPU/flat-scratch.ll
  llvm/test/CodeGen/AMDGPU/memory_clause.ll

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