[PATCH] D144718: [ScalarEvolution] Enhance Predicate implication from condition

[Max Kazantsev via Phabricator via llvm-commits]

mkazantsev added inline comments.


================
Comment at: llvm/test/Transforms/HardwareLoops/ARM/simple-do.ll:151
+; CHECK: [[ROUND:%[^ ]+]] = add i32 %n, -1
+; CHECK: [[HALVE:%[^ ]+]] = lshr i32 [[ROUND]], 1
 ; CHECK: [[COUNT:%[^ ]+]] = add nuw i32 [[HALVE]], 1
----------------
This is miscompile, see https://alive2.llvm.org/ce/z/ESPqU_


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144718/new/

https://reviews.llvm.org/D144718