[PATCH] D144925: [RISCV][NFC] Expand pseudos with sew for instructions that depend on lmul

[Michael Maitland via Phabricator via llvm-commits]

michaelmaitland added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:41
+    if !eq(mx, "UpperBound") then
+      def name # "_" # mx : SchedWrite;
+    else
----------------
Why don't we make this case SEW aware?


================
Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:79
+  foreach mx = SchedMxList in {
+    if !eq(mx, "UpperBound") then
+      def name # "_" # mx : SchedRead;
----------------
Why don't we make this case SEW aware?




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Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:114
+    if !eq(mx, "UpperBound") then
+      def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>;
+    else
----------------
Why don't we make this case SEW aware?


================
Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:157
+  foreach mx = SchedMxList in {
+    if !eq(mx, "UpperBound") then
+      def : ReadAdvance<!cast<SchedRead>(name # "_" # mx), val, writes>;
----------------
Why don't we make this case SEW aware?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144925/new/

https://reviews.llvm.org/D144925