[PATCH] D144925: [RISCV][NFC] Added possible SEWs associated with a given LMUL

[Nitin John Raj via Phabricator via llvm-commits]

nitinjohnraj created this revision.
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[RISCV][NFC] Remove SEW suffix from pseudoinstructions

[RISCV] Made vcompress pseudoinstruction SEW-aware

[RISCV] Made vrgather.vv and vrgatherei16 pseudoinstructions SEW-aware

[RISCV] Made division pseudoinstructions SEW-aware

[RISCV] Made fsqrtv pseudoinstruction SEW-aware


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D144925

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/lib/Target/RISCV/RISCVScheduleV.td

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