[llvm] 31d6a57 - [AArch64][GlobalISel] Reorder stack up-adjustment and register copies
Amara Emerson via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 27 11:24:30 PST 2023
Author: Amara Emerson
Date: 2023-02-27T11:24:24-08:00
New Revision: 31d6a572579a5d1d9ae14a1a9d4ffbdb1b098e49
URL: https://github.com/llvm/llvm-project/commit/31d6a572579a5d1d9ae14a1a9d4ffbdb1b098e49
DIFF: https://github.com/llvm/llvm-project/commit/31d6a572579a5d1d9ae14a1a9d4ffbdb1b098e49.diff
LOG: [AArch64][GlobalISel] Reorder stack up-adjustment and register copies
This change reorders the stack up-adjustment and return value copying phases of
machine-ir generation on Aarch64. Doing so prevents a bug observed for fastcc
calls with >8 arguments, where the up-adjustment required from making that call
is placed in the wrong place relative to spill and reloading code.
See: https://github.com/llvm/llvm-project/issues/60972 for full issue
reproduction and context.
Patch contributed by Bruce Collie
Differential Revision: https://reviews.llvm.org/D144791
Added:
llvm/test/CodeGen/AArch64/aarch64-fastcc-stackup.ll
Modified:
llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
llvm/test/CodeGen/AArch64/GlobalISel/legalize-cos.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-exp.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-fexp2.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmaxnum.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-fminnum.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-log.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-log10.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-log2.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-sin.mir
llvm/test/CodeGen/AArch64/arm64-this-return.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
index e603414b3766..d1c1e1075fc8 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
@@ -1312,6 +1312,17 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
// Now we can add the actual call instruction to the correct basic block.
MIRBuilder.insertInstr(MIB);
+ uint64_t CalleePopBytes =
+ doesCalleeRestoreStack(Info.CallConv,
+ MF.getTarget().Options.GuaranteedTailCallOpt)
+ ? alignTo(Assigner.StackOffset, 16)
+ : 0;
+
+ CallSeqStart.addImm(Assigner.StackOffset).addImm(0);
+ MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)
+ .addImm(Assigner.StackOffset)
+ .addImm(CalleePopBytes);
+
// If Callee is a reg, since it is used by a target specific
// instruction, it must have a register class matching the
// constraint of that instruction.
@@ -1344,17 +1355,6 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21));
}
- uint64_t CalleePopBytes =
- doesCalleeRestoreStack(Info.CallConv,
- MF.getTarget().Options.GuaranteedTailCallOpt)
- ? alignTo(Assigner.StackOffset, 16)
- : 0;
-
- CallSeqStart.addImm(Assigner.StackOffset).addImm(0);
- MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)
- .addImm(Assigner.StackOffset)
- .addImm(CalleePopBytes);
-
if (!Info.CanLowerReturn) {
insertSRetLoads(MIRBuilder, Info.OrigRet.Ty, Info.OrigRet.Regs,
Info.DemoteRegister, Info.DemoteStackIndex);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
index b8b66236d7ea..b34e5ae45f7d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
@@ -90,8 +90,8 @@ define i32 @i8i16caller() nounwind readnone {
; CHECK-NEXT: $x6 = COPY [[C6]](s64)
; CHECK-NEXT: $x7 = COPY [[C7]](s64)
; CHECK-NEXT: BL @i8i16callee, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $w3, implicit $w4, implicit $x5, implicit $x6, implicit $x7, implicit-def $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: ADJCALLSTACKUP 6, 0, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
index 375b7f8134c3..048063823d1c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
@@ -219,8 +219,8 @@ define i32 @i8i16caller() nounwind readnone {
; CHECK-NEXT: $x6 = COPY [[C6]](s64)
; CHECK-NEXT: $x7 = COPY [[C7]](s64)
; CHECK-NEXT: BL @i8i16callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $w3, implicit $w4, implicit $x5, implicit $x6, implicit $x7, implicit-def $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: ADJCALLSTACKUP 32, 0, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
index 6dd1533475f8..743c41539406 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
@@ -802,8 +802,8 @@ define void @jt_multiple_jump_tables(ptr %arg, i32 %arg1, ptr %arg2) {
; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
; CHECK-NEXT: $x1 = COPY [[LOAD]](p0)
; CHECK-NEXT: BL @wibble, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; CHECK-NEXT: G_BR %bb.59
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.57.bb62:
@@ -811,8 +811,8 @@ define void @jt_multiple_jump_tables(ptr %arg, i32 %arg1, ptr %arg2) {
; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
; CHECK-NEXT: $x1 = COPY [[COPY2]](p0)
; CHECK-NEXT: BL @wibble, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1
- ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; CHECK-NEXT: G_BR %bb.59
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.58.bb64:
@@ -825,8 +825,8 @@ define void @jt_multiple_jump_tables(ptr %arg, i32 %arg1, ptr %arg2) {
; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
; CHECK-NEXT: $x1 = COPY [[FRAME_INDEX]](p0)
; CHECK-NEXT: BL @wibble, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1
- ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; CHECK-NEXT: G_BR %bb.59
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.59.bb68:
@@ -1414,8 +1414,8 @@ define ptr @test_range_phi_switch_cycle() {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $w0 = COPY [[PHI]](s32)
; CHECK-NEXT: BL @ham, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $x0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
bb:
br label %bb1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
index 51223dffe370..4224c1cad1b6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
@@ -147,8 +147,8 @@ define i32 @caller_signext_i1() {
; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[SEXT]](s8)
; CHECK-NEXT: $w0 = COPY [[SEXT1]](s32)
; CHECK-NEXT: BL @callee_signext_i1, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $w0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = call i32 @callee_signext_i1(i1 signext true)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
index e79887acf42d..e5db9c2baa88 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
@@ -56,11 +56,11 @@ define void @test_return_v3f32() {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $s0 = COPY [[DEF]](s32)
; CHECK-NEXT: BL @bar, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $q0
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](<4 x s32>)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32)
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: RET_ReallyLR
%call = call <3 x float> @bar(float undef)
ret void
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
index 1ccd2584fb11..02ab7a0772d8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
@@ -141,8 +141,8 @@ define i32 @caller_zeroext_i1() {
; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ZEXT]](s8)
; CHECK-NEXT: $w0 = COPY [[ZEXT1]](s32)
; CHECK-NEXT: BL @callee_zeroext_i1, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $w0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%r = call i32 @callee_zeroext_i1(i1 zeroext true)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
index d6a80bc81040..9828cc8572cc 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
@@ -120,8 +120,8 @@ define i32 @test_too_big_stack() {
; DARWIN-NEXT: $x6 = COPY [[DEF]](s64)
; DARWIN-NEXT: $x7 = COPY [[DEF]](s64)
; DARWIN-NEXT: BL @too_big_stack, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit-def $w0
- ; DARWIN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w0
; DARWIN-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $sp, implicit $sp
+ ; DARWIN-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w0
; DARWIN-NEXT: $w0 = COPY [[COPY1]](s32)
; DARWIN-NEXT: RET_ReallyLR implicit $w0
; WINDOWS-LABEL: name: test_too_big_stack
@@ -146,8 +146,8 @@ define i32 @test_too_big_stack() {
; WINDOWS-NEXT: $x6 = COPY [[DEF]](s64)
; WINDOWS-NEXT: $x7 = COPY [[DEF]](s64)
; WINDOWS-NEXT: BL @too_big_stack, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit-def $w0
- ; WINDOWS-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w0
; WINDOWS-NEXT: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
+ ; WINDOWS-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w0
; WINDOWS-NEXT: $w0 = COPY [[COPY1]](s32)
; WINDOWS-NEXT: RET_ReallyLR implicit $w0
entry:
@@ -420,8 +420,8 @@ define hidden swiftcc i64 @swiftself_indirect_tail(ptr swiftself %arg) {
; DARWIN-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x20
; DARWIN-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; DARWIN-NEXT: BL @pluto, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $x0
- ; DARWIN-NEXT: [[COPY1:%[0-9]+]]:tcgpr64(p0) = COPY $x0
; DARWIN-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; DARWIN-NEXT: [[COPY1:%[0-9]+]]:tcgpr64(p0) = COPY $x0
; DARWIN-NEXT: $x20 = COPY [[COPY]](p0)
; DARWIN-NEXT: TCRETURNri [[COPY1]](p0), 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $x20
; WINDOWS-LABEL: name: swiftself_indirect_tail
@@ -431,8 +431,8 @@ define hidden swiftcc i64 @swiftself_indirect_tail(ptr swiftself %arg) {
; WINDOWS-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x20
; WINDOWS-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; WINDOWS-NEXT: BL @pluto, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $x0
- ; WINDOWS-NEXT: [[COPY1:%[0-9]+]]:tcgpr64(p0) = COPY $x0
; WINDOWS-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; WINDOWS-NEXT: [[COPY1:%[0-9]+]]:tcgpr64(p0) = COPY $x0
; WINDOWS-NEXT: $x20 = COPY [[COPY]](p0)
; WINDOWS-NEXT: TCRETURNri [[COPY1]](p0), 0, csr_aarch64_aapcs, implicit $sp, implicit $x20
%tmp = call ptr @pluto()
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
index d1d6928749f2..b1bfe46f4b45 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
@@ -372,10 +372,10 @@ define i32 @test_zext_return_from_callee() {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @has_zext_return, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $w0
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_ZEXT]](s32)
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -391,10 +391,10 @@ define i32 @test_zext_return_from_callee2() {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @has_zext_return, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $w0
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_ZEXT]](s32)
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16)
; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -411,10 +411,10 @@ define i32 @test_sext_return_from_callee() {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @has_sext_return, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $w0
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT]](s32)
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s16)
; CHECK-NEXT: $w0 = COPY [[SEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -430,10 +430,10 @@ define i32 @test_sext_return_from_callee2() {
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: BL @has_sext_return, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def $w0
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT]](s32)
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s16)
; CHECK-NEXT: $w0 = COPY [[SEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
index bea2aca749cb..8d68f384db90 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
@@ -20,8 +20,8 @@ define { ptr, i32 } @bar() personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $w0 = COPY [[C]](s32)
; CHECK-NEXT: BL @foo, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit-def $w0
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: G_BR %bb.3
; CHECK-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cos.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cos.mir
index 552c7f3c7d96..798524bd880d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cos.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cos.mir
@@ -19,32 +19,32 @@ body: |
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V1_S32]](s32)
; CHECK-NEXT: BL &cosf
- ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT1_S32]](s32)
; CHECK-DAG: [[V2_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V2]](s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V2_S32]](s32)
; CHECK-NEXT: BL &cosf
- ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT2_S32]](s32)
; CHECK-DAG: [[V3_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V3]](s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V3_S32]](s32)
; CHECK-NEXT: BL &cosf
- ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT3:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT3_S32]](s32)
; CHECK-DAG: [[V4_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V4]](s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V4_S32]](s32)
; CHECK-NEXT: BL &cosf
- ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT4:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT4_S32]](s32)
; CHECK-DAG: %{{[0-9]+}}:_(<4 x s16>) = G_BUILD_VECTOR [[ELT1]](s16), [[ELT2]](s16), [[ELT3]](s16), [[ELT4]](s16)
@@ -217,8 +217,8 @@ body: |
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[REG1]](s32)
; CHECK-NEXT: BL &cosf
- ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[RES:%[0-9]+]]:_(s16) = G_FPTRUNC [[REG2]](s32)
%0:_(s16) = COPY $h0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exp.mir
index ee8ebfe868e9..6320727b3786 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-exp.mir
@@ -19,32 +19,32 @@ body: |
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V1_S32]](s32)
; CHECK-NEXT: BL &expf
- ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT1_S32]](s32)
; CHECK-DAG: [[V2_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V2]](s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V2_S32]](s32)
; CHECK-NEXT: BL &expf
- ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT2_S32]](s32)
; CHECK-DAG: [[V3_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V3]](s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V3_S32]](s32)
; CHECK-NEXT: BL &expf
- ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT3:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT3_S32]](s32)
; CHECK-DAG: [[V4_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V4]](s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V4_S32]](s32)
; CHECK-NEXT: BL &expf
- ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT4:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT4_S32]](s32)
; CHECK-DAG: %{{[0-9]+}}:_(<4 x s16>) = G_BUILD_VECTOR [[ELT1]](s16), [[ELT2]](s16), [[ELT3]](s16), [[ELT4]](s16)
@@ -217,8 +217,8 @@ body: |
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[REG1]](s32)
; CHECK-NEXT: BL &expf
- ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[RES:%[0-9]+]]:_(s16) = G_FPTRUNC [[REG2]](s32)
%0:_(s16) = COPY $h0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fexp2.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fexp2.mir
index 4e2a85472040..4f8999d8f55c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fexp2.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fexp2.mir
@@ -18,29 +18,29 @@ body: |
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[FPEXT]](s32)
; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY1]](s32)
; CHECK: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[FPEXT1]](s32)
; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY2]](s32)
; CHECK: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[FPEXT2]](s32)
; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY3]](s32)
; CHECK: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[FPEXT3]](s32)
; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY4]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16)
; CHECK: $d0 = COPY [[BUILD_VECTOR]](<4 x s16>)
@@ -66,57 +66,57 @@ body: |
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[FPEXT]](s32)
; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY1]](s32)
; CHECK: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[FPEXT1]](s32)
; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY2]](s32)
; CHECK: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[FPEXT2]](s32)
; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY3]](s32)
; CHECK: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[FPEXT3]](s32)
; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY4]](s32)
; CHECK: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[UV4]](s16)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[FPEXT4]](s32)
; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY5]](s32)
; CHECK: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[UV5]](s16)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[FPEXT5]](s32)
; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY6]](s32)
; CHECK: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[UV6]](s16)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[FPEXT6]](s32)
; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC6:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY7]](s32)
; CHECK: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[UV7]](s16)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[FPEXT7]](s32)
; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC7:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY8]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16), [[FPTRUNC4]](s16), [[FPTRUNC5]](s16), [[FPTRUNC6]](s16), [[FPTRUNC7]](s16)
; CHECK: $q0 = COPY [[BUILD_VECTOR]](<8 x s16>)
@@ -141,13 +141,13 @@ body: |
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[UV]](s32)
; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[UV1]](s32)
; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
; CHECK: $d0 = COPY [[BUILD_VECTOR]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
@@ -171,23 +171,23 @@ body: |
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[UV]](s32)
; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[UV1]](s32)
; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[UV2]](s32)
; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[UV3]](s32)
; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>)
; CHECK: RET_ReallyLR implicit $q0
@@ -211,13 +211,13 @@ body: |
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $d0 = COPY [[UV]](s64)
; CHECK: BL &exp2, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit-def $d0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $d0
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $d0 = COPY [[UV1]](s64)
; CHECK: BL &exp2, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit-def $d0
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[COPY1]](s64), [[COPY2]](s64)
; CHECK: $q0 = COPY [[BUILD_VECTOR]](<2 x s64>)
; CHECK: RET_ReallyLR implicit $q0
@@ -241,8 +241,8 @@ body: |
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[FPEXT]](s32)
; CHECK: BL &exp2f, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit-def $s0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY1]](s32)
; CHECK: $h0 = COPY [[FPTRUNC]](s16)
; CHECK: RET_ReallyLR implicit $h0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmaxnum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmaxnum.mir
index e1dabeb5e9b4..f947923e7e56 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmaxnum.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmaxnum.mir
@@ -93,8 +93,8 @@ body: |
; FP16: $q0 = COPY %a(s128)
; FP16: $q1 = COPY %b(s128)
; FP16: BL &fmaxl, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0, implicit $q1, implicit-def $q0
- ; FP16: %maxnum:_(s128) = COPY $q0
; FP16: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; FP16: %maxnum:_(s128) = COPY $q0
; FP16: $q0 = COPY %maxnum(s128)
; FP16: RET_ReallyLR implicit $q0
; NO-FP16-LABEL: name: s128_libcall
@@ -104,8 +104,8 @@ body: |
; NO-FP16: $q0 = COPY %a(s128)
; NO-FP16: $q1 = COPY %b(s128)
; NO-FP16: BL &fmaxl, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0, implicit $q1, implicit-def $q0
- ; NO-FP16: %maxnum:_(s128) = COPY $q0
; NO-FP16: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; NO-FP16: %maxnum:_(s128) = COPY $q0
; NO-FP16: $q0 = COPY %maxnum(s128)
; NO-FP16: RET_ReallyLR implicit $q0
%a:_(s128) = COPY $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fminnum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fminnum.mir
index cb6f287b857b..5b2671fcec7c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fminnum.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fminnum.mir
@@ -93,8 +93,8 @@ body: |
; FP16: $q0 = COPY %a(s128)
; FP16: $q1 = COPY %b(s128)
; FP16: BL &fminl, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0, implicit $q1, implicit-def $q0
- ; FP16: %minnum:_(s128) = COPY $q0
; FP16: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; FP16: %minnum:_(s128) = COPY $q0
; FP16: $q0 = COPY %minnum(s128)
; FP16: RET_ReallyLR implicit $q0
; NO-FP16-LABEL: name: s128_libcall
@@ -104,8 +104,8 @@ body: |
; NO-FP16: $q0 = COPY %a(s128)
; NO-FP16: $q1 = COPY %b(s128)
; NO-FP16: BL &fminl, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $q0, implicit $q1, implicit-def $q0
- ; NO-FP16: %minnum:_(s128) = COPY $q0
; NO-FP16: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; NO-FP16: %minnum:_(s128) = COPY $q0
; NO-FP16: $q0 = COPY %minnum(s128)
; NO-FP16: RET_ReallyLR implicit $q0
%a:_(s128) = COPY $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log.mir
index f8ccd852a0b3..3c27af8b5b7d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log.mir
@@ -19,32 +19,32 @@ body: |
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V1_S32]](s32)
; CHECK-NEXT: BL &logf
- ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT1_S32]](s32)
; CHECK-DAG: [[V2_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V2]](s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V2_S32]](s32)
; CHECK-NEXT: BL &logf
- ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT2_S32]](s32)
; CHECK-DAG: [[V3_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V3]](s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V3_S32]](s32)
; CHECK-NEXT: BL &logf
- ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT3:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT3_S32]](s32)
; CHECK-DAG: [[V4_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V4]](s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V4_S32]](s32)
; CHECK-NEXT: BL &logf
- ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT4:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT4_S32]](s32)
; CHECK-DAG: %{{[0-9]+}}:_(<4 x s16>) = G_BUILD_VECTOR [[ELT1]](s16), [[ELT2]](s16), [[ELT3]](s16), [[ELT4]](s16)
@@ -217,8 +217,8 @@ body: |
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[REG1]](s32)
; CHECK-NEXT: BL &logf
- ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[RES:%[0-9]+]]:_(s16) = G_FPTRUNC [[REG2]](s32)
%0:_(s16) = COPY $h0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log10.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log10.mir
index 509b0a3bd502..f0eaddc91748 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log10.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log10.mir
@@ -19,32 +19,32 @@ body: |
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V1_S32]](s32)
; CHECK-NEXT: BL &log10
- ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT1_S32]](s32)
; CHECK-DAG: [[V2_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V2]](s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V2_S32]](s32)
; CHECK-NEXT: BL &log10
- ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT2_S32]](s32)
; CHECK-DAG: [[V3_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V3]](s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V3_S32]](s32)
; CHECK-NEXT: BL &log10
- ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT3:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT3_S32]](s32)
; CHECK-DAG: [[V4_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V4]](s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V4_S32]](s32)
; CHECK-NEXT: BL &log10
- ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT4:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT4_S32]](s32)
; CHECK-DAG: %{{[0-9]+}}:_(<4 x s16>) = G_BUILD_VECTOR [[ELT1]](s16), [[ELT2]](s16), [[ELT3]](s16), [[ELT4]](s16)
@@ -217,8 +217,8 @@ body: |
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[REG1]](s32)
; CHECK-NEXT: BL &log10
- ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[RES:%[0-9]+]]:_(s16) = G_FPTRUNC [[REG2]](s32)
%0:_(s16) = COPY $h0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log2.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log2.mir
index a4b05c5498dd..1ee8ea1b6188 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log2.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-log2.mir
@@ -19,32 +19,32 @@ body: |
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V1_S32]](s32)
; CHECK-NEXT: BL &log2
- ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT1_S32]](s32)
; CHECK-DAG: [[V2_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V2]](s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V2_S32]](s32)
; CHECK-NEXT: BL &log2
- ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT2_S32]](s32)
; CHECK-DAG: [[V3_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V3]](s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V3_S32]](s32)
; CHECK-NEXT: BL &log2
- ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT3:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT3_S32]](s32)
; CHECK-DAG: [[V4_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V4]](s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V4_S32]](s32)
; CHECK-NEXT: BL &log2
- ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT4:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT4_S32]](s32)
; CHECK-DAG: %{{[0-9]+}}:_(<4 x s16>) = G_BUILD_VECTOR [[ELT1]](s16), [[ELT2]](s16), [[ELT3]](s16), [[ELT4]](s16)
@@ -217,8 +217,8 @@ body: |
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[REG1]](s32)
; CHECK-NEXT: BL &log2
- ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[RES:%[0-9]+]]:_(s16) = G_FPTRUNC [[REG2]](s32)
%0:_(s16) = COPY $h0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
index 2f147d5d34d6..10d86c663664 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
@@ -13,15 +13,15 @@ body: |
; CHECK: $d0 = COPY [[COPY]](s64)
; CHECK: $d1 = COPY [[COPY1]](s64)
; CHECK: BL &pow, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit-def $d0
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $d0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $d0
; CHECK: $x0 = COPY [[COPY4]](s64)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[COPY2]](s32)
; CHECK: $s1 = COPY [[COPY3]](s32)
; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: $w0 = COPY [[COPY5]](s32)
%0:_(s64) = COPY $d0
%1:_(s64) = COPY $d1
@@ -53,8 +53,8 @@ body: |
; CHECK: $s0 = COPY [[FPEXT]](s32)
; CHECK: $s1 = COPY [[FPEXT1]](s32)
; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY2]](s32)
; CHECK: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
; CHECK: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV5]](s16)
@@ -62,8 +62,8 @@ body: |
; CHECK: $s0 = COPY [[FPEXT2]](s32)
; CHECK: $s1 = COPY [[FPEXT3]](s32)
; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY3]](s32)
; CHECK: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
; CHECK: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[UV6]](s16)
@@ -71,8 +71,8 @@ body: |
; CHECK: $s0 = COPY [[FPEXT4]](s32)
; CHECK: $s1 = COPY [[FPEXT5]](s32)
; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY4]](s32)
; CHECK: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
; CHECK: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[UV7]](s16)
@@ -80,8 +80,8 @@ body: |
; CHECK: $s0 = COPY [[FPEXT6]](s32)
; CHECK: $s1 = COPY [[FPEXT7]](s32)
; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY5]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16)
; CHECK: $d0 = COPY [[BUILD_VECTOR]](<4 x s16>)
@@ -113,8 +113,8 @@ body: |
; CHECK: $s0 = COPY [[FPEXT]](s32)
; CHECK: $s1 = COPY [[FPEXT1]](s32)
; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY2]](s32)
; CHECK: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
; CHECK: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV9]](s16)
@@ -122,8 +122,8 @@ body: |
; CHECK: $s0 = COPY [[FPEXT2]](s32)
; CHECK: $s1 = COPY [[FPEXT3]](s32)
; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY3]](s32)
; CHECK: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
; CHECK: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[UV10]](s16)
@@ -131,8 +131,8 @@ body: |
; CHECK: $s0 = COPY [[FPEXT4]](s32)
; CHECK: $s1 = COPY [[FPEXT5]](s32)
; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY4]](s32)
; CHECK: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
; CHECK: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[UV11]](s16)
@@ -140,8 +140,8 @@ body: |
; CHECK: $s0 = COPY [[FPEXT6]](s32)
; CHECK: $s1 = COPY [[FPEXT7]](s32)
; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY5]](s32)
; CHECK: [[FPEXT8:%[0-9]+]]:_(s32) = G_FPEXT [[UV4]](s16)
; CHECK: [[FPEXT9:%[0-9]+]]:_(s32) = G_FPEXT [[UV12]](s16)
@@ -149,8 +149,8 @@ body: |
; CHECK: $s0 = COPY [[FPEXT8]](s32)
; CHECK: $s1 = COPY [[FPEXT9]](s32)
; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY6]](s32)
; CHECK: [[FPEXT10:%[0-9]+]]:_(s32) = G_FPEXT [[UV5]](s16)
; CHECK: [[FPEXT11:%[0-9]+]]:_(s32) = G_FPEXT [[UV13]](s16)
@@ -158,8 +158,8 @@ body: |
; CHECK: $s0 = COPY [[FPEXT10]](s32)
; CHECK: $s1 = COPY [[FPEXT11]](s32)
; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY7]](s32)
; CHECK: [[FPEXT12:%[0-9]+]]:_(s32) = G_FPEXT [[UV6]](s16)
; CHECK: [[FPEXT13:%[0-9]+]]:_(s32) = G_FPEXT [[UV14]](s16)
@@ -167,8 +167,8 @@ body: |
; CHECK: $s0 = COPY [[FPEXT12]](s32)
; CHECK: $s1 = COPY [[FPEXT13]](s32)
; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC6:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY8]](s32)
; CHECK: [[FPEXT14:%[0-9]+]]:_(s32) = G_FPEXT [[UV7]](s16)
; CHECK: [[FPEXT15:%[0-9]+]]:_(s32) = G_FPEXT [[UV15]](s16)
@@ -176,8 +176,8 @@ body: |
; CHECK: $s0 = COPY [[FPEXT14]](s32)
; CHECK: $s1 = COPY [[FPEXT15]](s32)
; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[FPTRUNC7:%[0-9]+]]:_(s16) = G_FPTRUNC [[COPY9]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16), [[FPTRUNC4]](s16), [[FPTRUNC5]](s16), [[FPTRUNC6]](s16), [[FPTRUNC7]](s16)
; CHECK: $q0 = COPY [[BUILD_VECTOR]](<8 x s16>)
@@ -207,14 +207,14 @@ body: |
; CHECK: $s0 = COPY [[UV]](s32)
; CHECK: $s1 = COPY [[UV2]](s32)
; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[UV1]](s32)
; CHECK: $s1 = COPY [[UV3]](s32)
; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
; CHECK: $d0 = COPY [[BUILD_VECTOR]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
@@ -243,26 +243,26 @@ body: |
; CHECK: $s0 = COPY [[UV]](s32)
; CHECK: $s1 = COPY [[UV4]](s32)
; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[UV1]](s32)
; CHECK: $s1 = COPY [[UV5]](s32)
; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[UV2]](s32)
; CHECK: $s1 = COPY [[UV6]](s32)
; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $s0 = COPY [[UV3]](s32)
; CHECK: $s1 = COPY [[UV7]](s32)
; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32)
; CHECK: $q0 = COPY [[BUILD_VECTOR]](<4 x s32>)
; CHECK: RET_ReallyLR implicit $q0
@@ -291,14 +291,14 @@ body: |
; CHECK: $d0 = COPY [[UV]](s64)
; CHECK: $d1 = COPY [[UV2]](s64)
; CHECK: BL &pow, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit-def $d0
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $d0 = COPY [[UV1]](s64)
; CHECK: $d1 = COPY [[UV3]](s64)
; CHECK: BL &pow, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit-def $d0
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $d0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $d0
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[COPY2]](s64), [[COPY3]](s64)
; CHECK: $q0 = COPY [[BUILD_VECTOR]](<2 x s64>)
; CHECK: RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
index 660b2b04fbf7..edbb776a7f4c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
@@ -126,8 +126,8 @@ body: |
; CHECK-NEXT: $d0 = COPY [[COPY]](s64)
; CHECK-NEXT: $d1 = COPY [[COPY1]](s64)
; CHECK-NEXT: BL &fmod, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit-def $d0
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $d0
; CHECK-NEXT: $x0 = COPY [[COPY2]](s64)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
@@ -135,8 +135,8 @@ body: |
; CHECK-NEXT: $s0 = COPY [[TRUNC]](s32)
; CHECK-NEXT: $s1 = COPY [[TRUNC1]](s32)
; CHECK-NEXT: BL &fmodf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
- ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: $w0 = COPY [[COPY3]](s32)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir
index 88d9680a0abf..0f0f2218c580 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir
@@ -36,10 +36,10 @@ body: |
; CHECK-NEXT: $x2 = COPY [[UV2]](s64)
; CHECK-NEXT: $x3 = COPY [[UV3]](s64)
; CHECK-NEXT: BL &__udivti3, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x1
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: G_STORE [[MV]](s128), [[COPY]](p0) :: (store (s128) into %ir.v1ptr)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
@@ -78,10 +78,10 @@ body: |
; CHECK-NEXT: $x2 = COPY [[UV2]](s64)
; CHECK-NEXT: $x3 = COPY [[UV3]](s64)
; CHECK-NEXT: BL &__divti3, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit-def $x0, implicit-def $x1
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
- ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: G_STORE [[MV]](s128), [[COPY]](p0) :: (store (s128) into %ir.v1ptr)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sin.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sin.mir
index 225bc84add74..d4da3327357c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sin.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sin.mir
@@ -19,32 +19,32 @@ body: |
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V1_S32]](s32)
; CHECK-NEXT: BL &sinf
- ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT1_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT1:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT1_S32]](s32)
; CHECK-DAG: [[V2_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V2]](s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V2_S32]](s32)
; CHECK-NEXT: BL &sinf
- ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT2_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT2:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT2_S32]](s32)
; CHECK-DAG: [[V3_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V3]](s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V3_S32]](s32)
; CHECK-NEXT: BL &sinf
- ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT3_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT3:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT3_S32]](s32)
; CHECK-DAG: [[V4_S32:%[0-9]+]]:_(s32) = G_FPEXT [[V4]](s16)
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[V4_S32]](s32)
; CHECK-NEXT: BL &sinf
- ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[ELT4_S32:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[ELT4:%[0-9]+]]:_(s16) = G_FPTRUNC [[ELT4_S32]](s32)
; CHECK-DAG: %{{[0-9]+}}:_(<4 x s16>) = G_BUILD_VECTOR [[ELT1]](s16), [[ELT2]](s16), [[ELT3]](s16), [[ELT4]](s16)
@@ -217,8 +217,8 @@ body: |
; CHECK-NEXT: ADJCALLSTACKDOWN
; CHECK-NEXT: $s0 = COPY [[REG1]](s32)
; CHECK-NEXT: BL &sinf
- ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: ADJCALLSTACKUP
+ ; CHECK-NEXT: [[REG2:%[0-9]+]]:_(s32) = COPY $s0
; CHECK-NEXT: [[RES:%[0-9]+]]:_(s16) = G_FPTRUNC [[REG2]](s32)
%0:_(s16) = COPY $h0
diff --git a/llvm/test/CodeGen/AArch64/aarch64-fastcc-stackup.ll b/llvm/test/CodeGen/AArch64/aarch64-fastcc-stackup.ll
new file mode 100644
index 000000000000..71f8a43a4385
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/aarch64-fastcc-stackup.ll
@@ -0,0 +1,49 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-none-linux -O0 -tailcallopt < %s | FileCheck %s
+
+define void @bar() {
+; CHECK-LABEL: bar:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ret
+ ret void
+}
+
+define fastcc i64 @foo(i64 %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5, i64 %6, i64 %7, i64 %8) {
+; CHECK-LABEL: foo:
+; CHECK: // %bb.0:
+; CHECK-NEXT: add sp, sp, #16
+; CHECK-NEXT: ret
+ ret i64 %0
+}
+
+; https://github.com/llvm/llvm-project/issues/60972
+define fastcc i64 @baz() {
+; CHECK-LABEL: baz:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: mov x7, xzr
+; CHECK-NEXT: str xzr, [x8]
+; CHECK-NEXT: mov x0, x7
+; CHECK-NEXT: mov x1, x7
+; CHECK-NEXT: mov x2, x7
+; CHECK-NEXT: mov x3, x7
+; CHECK-NEXT: mov x4, x7
+; CHECK-NEXT: mov x5, x7
+; CHECK-NEXT: mov x6, x7
+; CHECK-NEXT: bl foo
+; CHECK-NEXT: sub sp, sp, #16
+; CHECK-NEXT: str x0, [sp, #8] // 8-byte Folded Spill
+; CHECK-NEXT: bl bar
+; CHECK-NEXT: ldr x0, [sp, #8] // 8-byte Folded Reload
+; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call fastcc i64 @foo(i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0)
+ call void @bar()
+ ret i64 %0
+}
diff --git a/llvm/test/CodeGen/AArch64/arm64-this-return.ll b/llvm/test/CodeGen/AArch64/arm64-this-return.ll
index 93c50a38f1d1..29e086014d52 100644
--- a/llvm/test/CodeGen/AArch64/arm64-this-return.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-this-return.ll
@@ -26,8 +26,8 @@ define ptr @C_ctor_base(ptr returned %this, i32 %x) {
; GISEL-MIR: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; GISEL-MIR: $x0 = COPY [[COPY]](p0)
; GISEL-MIR: BL @A_ctor_base, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0
- ; GISEL-MIR: [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; GISEL-MIR: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; GISEL-MIR: [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; GISEL-MIR: $x0 = COPY [[COPY]](p0)
; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
; GISEL-MIR: TCRETURNdi @B_ctor_base, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $w1
@@ -51,14 +51,14 @@ define ptr @C_ctor_base_nothisret(ptr %this, i32 %x) {
; GISEL-MIR: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; GISEL-MIR: $x0 = COPY [[COPY]](p0)
; GISEL-MIR: BL @A_ctor_base_nothisret, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit-def $x0
- ; GISEL-MIR: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
; GISEL-MIR: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; GISEL-MIR: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
; GISEL-MIR: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; GISEL-MIR: $x0 = COPY [[COPY]](p0)
; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
; GISEL-MIR: BL @B_ctor_base_nothisret, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1, implicit-def $x0
- ; GISEL-MIR: [[COPY3:%[0-9]+]]:_(p0) = COPY $x0
; GISEL-MIR: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; GISEL-MIR: [[COPY3:%[0-9]+]]:_(p0) = COPY $x0
; GISEL-MIR: $x0 = COPY [[COPY]](p0)
; GISEL-MIR: RET_ReallyLR implicit $x0
entry:
@@ -98,8 +98,8 @@ define ptr @C_ctor_complete_nothisret(ptr %this, i32 %x) {
; GISEL-MIR: $x0 = COPY [[COPY]](p0)
; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
; GISEL-MIR: BL @C_ctor_base_nothisret, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1, implicit-def $x0
- ; GISEL-MIR: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
; GISEL-MIR: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; GISEL-MIR: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
; GISEL-MIR: $x0 = COPY [[COPY]](p0)
; GISEL-MIR: RET_ReallyLR implicit $x0
entry:
@@ -119,8 +119,8 @@ define ptr @D_ctor_base(ptr %this, i32 %x) {
; GISEL-MIR: $x0 = COPY [[COPY]](p0)
; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
; GISEL-MIR: BL @B_ctor_complete, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1
- ; GISEL-MIR: [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; GISEL-MIR: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; GISEL-MIR: [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; GISEL-MIR: $x0 = COPY [[COPY]](p0)
; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
; GISEL-MIR: TCRETURNdi @B_ctor_complete, 0, csr_aarch64_aapcs, implicit $sp, implicit $x0, implicit $w1
@@ -145,16 +145,16 @@ define ptr @E_ctor_base(ptr %this, i32 %x) {
; GISEL-MIR: $x0 = COPY [[COPY]](p0)
; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
; GISEL-MIR: BL @B_ctor_complete, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1
- ; GISEL-MIR: [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; GISEL-MIR: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; GISEL-MIR: [[COPY2:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; GISEL-MIR: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; GISEL-MIR: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
; GISEL-MIR: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; GISEL-MIR: $x0 = COPY [[PTR_ADD]](p0)
; GISEL-MIR: $w1 = COPY [[COPY1]](s32)
; GISEL-MIR: BL @B_ctor_complete, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1
- ; GISEL-MIR: [[COPY3:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; GISEL-MIR: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; GISEL-MIR: [[COPY3:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; GISEL-MIR: $x0 = COPY [[COPY]](p0)
; GISEL-MIR: RET_ReallyLR implicit $x0
entry:
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