[PATCH] D144900: [X86] Add DwarfRegNums for segment registers

[Alex Brachet via Phabricator via llvm-commits]

abrachet created this revision.
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https://reviews.llvm.org/D144900

Files:
  llvm/lib/Target/X86/X86RegisterInfo.td


Index: llvm/lib/Target/X86/X86RegisterInfo.td
===================================================================
--- llvm/lib/Target/X86/X86RegisterInfo.td
+++ llvm/lib/Target/X86/X86RegisterInfo.td
@@ -320,12 +320,12 @@
 
 
 // Segment registers
-def CS : X86Reg<"cs", 1>;
-def DS : X86Reg<"ds", 3>;
-def SS : X86Reg<"ss", 2>;
-def ES : X86Reg<"es", 0>;
-def FS : X86Reg<"fs", 4>;
-def GS : X86Reg<"gs", 5>;
+def CS : X86Reg<"cs", 1>, DwarfRegNum<[51, 41, -2]>;
+def DS : X86Reg<"ds", 3>, DwarfRegNum<[53, 43, -2]>;
+def SS : X86Reg<"ss", 2>, DwarfRegNum<[52, 42, -2]>;
+def ES : X86Reg<"es", 0>, DwarfRegNum<[50, 40, -2]>;
+def FS : X86Reg<"fs", 4>, DwarfRegNum<[54, 44, -2]>;
+def GS : X86Reg<"gs", 5>, DwarfRegNum<[55, 45, -2]>;
 
 def FS_BASE : X86Reg<"fs.base", 0>, DwarfRegNum<[58, -2, -2]>;
 def GS_BASE : X86Reg<"gs.base", 0>, DwarfRegNum<[59, -2, -2]>;


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