[PATCH] D144760: [InstCombine] use demanded vector elements to eliminate partially redundant instructions

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n added inline comments.


================
Comment at: llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp:1715
   BinaryOperator *BO;
   if (match(I, m_BinOp(BO)) && !BO->isIntDivRem() && !BO->isShift()) {
+    Value *X = BO->getOperand(0);
----------------
Why doesn't this work for div/rem/shift?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144760/new/

https://reviews.llvm.org/D144760