[llvm] 9e5bfa1 - [AArch64] Add some tests for multiple uses of extended vector extracts. NFC

[David Green via llvm-commits]

Author: David Green
Date: 2023-02-27T14:34:52Z
New Revision: 9e5bfa1ae30bbb8fb978f7f6e9f3d90dd1cf5a4c

URL: https://github.com/llvm/llvm-project/commit/9e5bfa1ae30bbb8fb978f7f6e9f3d90dd1cf5a4c
DIFF: https://github.com/llvm/llvm-project/commit/9e5bfa1ae30bbb8fb978f7f6e9f3d90dd1cf5a4c.diff

LOG: [AArch64] Add some tests for multiple uses of extended vector extracts. NFC

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/extract-sext-zext.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/extract-sext-zext.ll b/llvm/test/CodeGen/AArch64/extract-sext-zext.ll
index 2cbd690c3f68..278a6e3becd9 100644
--- a/llvm/test/CodeGen/AArch64/extract-sext-zext.ll
+++ b/llvm/test/CodeGen/AArch64/extract-sext-zext.ll
@@ -354,3 +354,173 @@ define i16 @zv8i8i16(<8 x i8> %x) {
   %s = zext i8 %e to i16
   ret i16 %s
 }
+
+
+define i32 @both_i16i32(<8 x i16> %x) {
+; CHECK-LABEL: both_i16i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umov w8, v0.h[2]
+; CHECK-NEXT:    smov w9, v0.h[2]
+; CHECK-NEXT:    eor w0, w8, w9
+; CHECK-NEXT:    ret
+  %e = extractelement <8 x i16> %x, i64 2
+  %s = zext i16 %e to i32
+  %t = sext i16 %e to i32
+  %u = xor i32 %s, %t
+  ret i32 %u
+}
+
+define i32 @redundant_i16i32(<8 x i16> %x) {
+; CHECK-ISEL-LABEL: redundant_i16i32:
+; CHECK-ISEL:       // %bb.0:
+; CHECK-ISEL-NEXT:    umov w8, v0.h[2]
+; CHECK-ISEL-NEXT:    smov w9, v0.h[2]
+; CHECK-ISEL-NEXT:    eor w0, w9, w8, lsl #16
+; CHECK-ISEL-NEXT:    ret
+;
+; CHECK-GLOBAL-LABEL: redundant_i16i32:
+; CHECK-GLOBAL:       // %bb.0:
+; CHECK-GLOBAL-NEXT:    smov w8, v0.h[2]
+; CHECK-GLOBAL-NEXT:    eor w0, w8, w8, lsl #16
+; CHECK-GLOBAL-NEXT:    ret
+  %e = extractelement <8 x i16> %x, i64 2
+  %s = sext i16 %e to i32
+  %t = shl i32 %s, 16
+  %u = xor i32 %s, %t
+  ret i32 %u
+}
+
+define i32 @both_i8i32(<8 x i8> %x) {
+; CHECK-LABEL: both_i8i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    umov w8, v0.b[2]
+; CHECK-NEXT:    smov w9, v0.b[2]
+; CHECK-NEXT:    eor w0, w8, w9
+; CHECK-NEXT:    ret
+  %e = extractelement <8 x i8> %x, i64 2
+  %s = zext i8 %e to i32
+  %t = sext i8 %e to i32
+  %u = xor i32 %s, %t
+  ret i32 %u
+}
+
+define i32 @redundant_i8i32(<8 x i8> %x) {
+; CHECK-ISEL-LABEL: redundant_i8i32:
+; CHECK-ISEL:       // %bb.0:
+; CHECK-ISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-ISEL-NEXT:    umov w8, v0.b[2]
+; CHECK-ISEL-NEXT:    smov w9, v0.b[2]
+; CHECK-ISEL-NEXT:    eor w0, w9, w8, lsl #24
+; CHECK-ISEL-NEXT:    ret
+;
+; CHECK-GLOBAL-LABEL: redundant_i8i32:
+; CHECK-GLOBAL:       // %bb.0:
+; CHECK-GLOBAL-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-GLOBAL-NEXT:    smov w8, v0.b[2]
+; CHECK-GLOBAL-NEXT:    eor w0, w8, w8, lsl #24
+; CHECK-GLOBAL-NEXT:    ret
+  %e = extractelement <8 x i8> %x, i64 2
+  %s = sext i8 %e to i32
+  %t = shl i32 %s, 24
+  %u = xor i32 %s, %t
+  ret i32 %u
+}
+
+define i64 @both_i32i64(<4 x i32> %x) {
+; CHECK-LABEL: both_i32i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, v0.s[2]
+; CHECK-NEXT:    smov x9, v0.s[2]
+; CHECK-NEXT:    eor x0, x8, x9
+; CHECK-NEXT:    ret
+  %e = extractelement <4 x i32> %x, i64 2
+  %s = zext i32 %e to i64
+  %t = sext i32 %e to i64
+  %u = xor i64 %s, %t
+  ret i64 %u
+}
+
+define i64 @redundant_i32i64(<4 x i32> %x) {
+; CHECK-LABEL: redundant_i32i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    smov x8, v0.s[2]
+; CHECK-NEXT:    eor x0, x8, x8, lsl #32
+; CHECK-NEXT:    ret
+  %e = extractelement <4 x i32> %x, i64 2
+  %s = sext i32 %e to i64
+  %t = shl i64 %s, 32
+  %u = xor i64 %s, %t
+  ret i64 %u
+}
+
+define i64 @both_i16i64(<8 x i16> %x) {
+; CHECK-LABEL: both_i16i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umov w8, v0.h[2]
+; CHECK-NEXT:    smov x9, v0.h[2]
+; CHECK-NEXT:    eor x0, x8, x9
+; CHECK-NEXT:    ret
+  %e = extractelement <8 x i16> %x, i64 2
+  %s = zext i16 %e to i64
+  %t = sext i16 %e to i64
+  %u = xor i64 %s, %t
+  ret i64 %u
+}
+
+define i64 @redundant_i16i64(<8 x i16> %x) {
+; CHECK-ISEL-LABEL: redundant_i16i64:
+; CHECK-ISEL:       // %bb.0:
+; CHECK-ISEL-NEXT:    umov w8, v0.h[2]
+; CHECK-ISEL-NEXT:    smov x9, v0.h[2]
+; CHECK-ISEL-NEXT:    eor x0, x9, x8, lsl #48
+; CHECK-ISEL-NEXT:    ret
+;
+; CHECK-GLOBAL-LABEL: redundant_i16i64:
+; CHECK-GLOBAL:       // %bb.0:
+; CHECK-GLOBAL-NEXT:    smov x8, v0.h[2]
+; CHECK-GLOBAL-NEXT:    eor x0, x8, x8, lsl #48
+; CHECK-GLOBAL-NEXT:    ret
+  %e = extractelement <8 x i16> %x, i64 2
+  %s = sext i16 %e to i64
+  %t = shl i64 %s, 48
+  %u = xor i64 %s, %t
+  ret i64 %u
+}
+
+define i64 @both_i8i64(<8 x i8> %x) {
+; CHECK-LABEL: both_i8i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    umov w8, v0.b[2]
+; CHECK-NEXT:    smov x9, v0.b[2]
+; CHECK-NEXT:    eor x0, x8, x9
+; CHECK-NEXT:    ret
+  %e = extractelement <8 x i8> %x, i64 2
+  %s = zext i8 %e to i64
+  %t = sext i8 %e to i64
+  %u = xor i64 %s, %t
+  ret i64 %u
+}
+
+define i64 @redundant_i8i64(<8 x i8> %x) {
+; CHECK-ISEL-LABEL: redundant_i8i64:
+; CHECK-ISEL:       // %bb.0:
+; CHECK-ISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-ISEL-NEXT:    umov w8, v0.b[2]
+; CHECK-ISEL-NEXT:    smov x9, v0.b[2]
+; CHECK-ISEL-NEXT:    eor x0, x9, x8, lsl #56
+; CHECK-ISEL-NEXT:    ret
+;
+; CHECK-GLOBAL-LABEL: redundant_i8i64:
+; CHECK-GLOBAL:       // %bb.0:
+; CHECK-GLOBAL-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-GLOBAL-NEXT:    smov x8, v0.b[2]
+; CHECK-GLOBAL-NEXT:    eor x0, x8, x8, lsl #56
+; CHECK-GLOBAL-NEXT:    ret
+  %e = extractelement <8 x i8> %x, i64 2
+  %s = sext i8 %e to i64
+  %t = shl i64 %s, 56
+  %u = xor i64 %s, %t
+  ret i64 %u
+}