[PATCH] D144550: [AArch64] Remove 64bit->128bit vector insert lowering

Mon Feb 27 04:42:43 PST 2023

dmgreen added a comment.

In D144550#4154607 <https://reviews.llvm.org/D144550#4154607>, @SjoerdMeijer wrote:

> The idea makes sense I think, but just to put things into context, do you already have a case or patch where we can see the benefit of this?

The insert-load-into-zero from D144086 <https://reviews.llvm.org/D144086> is helped by this. I wrote them in a slightly odd order due to trying to work through the regressions in this change. Otherwise some of the patterns in that patch would need to look for `insert(extractsubreg(zerovec), load, 0)`, which isn't impossible but it's cleaner without all the extracts.

Speaking of which I've put up  D144850 <https://reviews.llvm.org/D144850> to help with the regressions in combine_srem_sdiv.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144550/new/

https://reviews.llvm.org/D144550