[llvm] 7427375 - [X86][MC] Assert unexpected form in emitREXPrefix, NFCI
Shengchen Kan via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 26 17:56:01 PST 2023
Author: Shengchen Kan
Date: 2023-02-27T09:55:54+08:00
New Revision: 7427375531283c263d191a1652719936b7b7e364
URL: https://github.com/llvm/llvm-project/commit/7427375531283c263d191a1652719936b7b7e364
DIFF: https://github.com/llvm/llvm-project/commit/7427375531283c263d191a1652719936b7b7e364.diff
LOG: [X86][MC] Assert unexpected form in emitREXPrefix, NFCI
1. Add a variable `HasRegOp` to record if the instruction has a register operand
2. Enumerate all the formats with a register operand in the switch
2. Add a default (unreachable) label in the switch (suggested by @reames)
Reviewed By: pengfei
Differential Revision: https://reviews.llvm.org/D144776
Added:
Modified:
llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index 6abff8124a25d..424f81b8e903f 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -1160,20 +1160,21 @@ PrefixKind X86MCCodeEmitter::emitREXPrefix(int MemOperand, const MCInst &MI,
if (!STI.hasFeature(X86::Is64Bit))
return None;
X86OpcodePrefixHelper Prefix(*Ctx.getRegisterInfo());
- bool UsesHighByteReg = false;
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
uint64_t TSFlags = Desc.TSFlags;
Prefix.setW(TSFlags & X86II::REX_W);
unsigned NumOps = MI.getNumOperands();
- if (!NumOps) {
- PrefixKind Kind = Prefix.determineOptimalKind();
- Prefix.emit(OS);
- return Kind;
- }
- unsigned CurOp = X86II::getOperandBias(Desc);
+ bool UsesHighByteReg = false;
+#ifndef NDEBUG
+ bool HasRegOp = false;
+#endif
+ unsigned CurOp = NumOps ? X86II::getOperandBias(Desc) : 0;
for (unsigned i = CurOp; i != NumOps; ++i) {
const MCOperand &MO = MI.getOperand(i);
if (MO.isReg()) {
+#ifndef NDEBUG
+ HasRegOp = true;
+#endif
unsigned Reg = MO.getReg();
if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)
UsesHighByteReg = true;
@@ -1194,6 +1195,14 @@ PrefixKind X86MCCodeEmitter::emitREXPrefix(int MemOperand, const MCInst &MI,
}
}
switch (TSFlags & X86II::FormMask) {
+ default:
+ assert(!HasRegOp && "Unexpected form in emitREXPrefix!");
+ case X86II::RawFrm:
+ case X86II::RawFrmMemOffs:
+ case X86II::RawFrmSrc:
+ case X86II::RawFrmDst:
+ case X86II::RawFrmDstSrc:
+ break;
case X86II::AddRegFrm:
Prefix.setB(MI, CurOp++);
break;
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