[PATCH] D144776: [X86][MC] Assert unexpected form in emitREXPrefix, NFCI

[Kan Shengchen via Phabricator via llvm-commits]

skan updated this revision to Diff 500488.
skan added a comment.

Fix the compiler-rt test fail by adding format RawFrm


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144776/new/

https://reviews.llvm.org/D144776

Files:
  llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp


Index: llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
===================================================================
--- llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -1160,20 +1160,17 @@
   if (!STI.hasFeature(X86::Is64Bit))
     return None;
   X86OpcodePrefixHelper Prefix(*Ctx.getRegisterInfo());
-  bool UsesHighByteReg = false;
   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
   uint64_t TSFlags = Desc.TSFlags;
   Prefix.setW(TSFlags & X86II::REX_W);
   unsigned NumOps = MI.getNumOperands();
-  if (!NumOps) {
-    PrefixKind Kind = Prefix.determineOptimalKind();
-    Prefix.emit(OS);
-    return Kind;
-  }
-  unsigned CurOp = X86II::getOperandBias(Desc);
+  bool UsesHighByteReg = false;
+  bool HasRegOp = false;
+  unsigned CurOp = NumOps ? X86II::getOperandBias(Desc) : 0;
   for (unsigned i = CurOp; i != NumOps; ++i) {
     const MCOperand &MO = MI.getOperand(i);
     if (MO.isReg()) {
+      HasRegOp = true;
       unsigned Reg = MO.getReg();
       if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)
         UsesHighByteReg = true;
@@ -1194,6 +1191,16 @@
     }
   }
   switch (TSFlags & X86II::FormMask) {
+  default:
+    if (HasRegOp)
+      llvm_unreachable("Unexpected form in emitREXPrefix!");
+    [[fallthrough]];
+  case X86II::RawFrm:
+  case X86II::RawFrmMemOffs:
+  case X86II::RawFrmSrc:
+  case X86II::RawFrmDst:
+  case X86II::RawFrmDstSrc:
+    break;
   case X86II::AddRegFrm:
     Prefix.setB(MI, CurOp++);
     break;


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