[PATCH] D144791: Reorder stack up-adjustment and register copies

[Bruce Collie via Phabricator via llvm-commits]

Baltoli created this revision.
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This diff reorders the stack up-adjustment and return value copying phases of
machine-ir generation on Aarch64. Doing so prevents a bug observed for fastcc
calls with >8 arguments, where the up-adjustment required from making that call
is placed in the wrong place relative to spill and reloading code.

See: https://github.com/llvm/llvm-project/issues/60972


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D144791

Files:
  llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv-ios.ll
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
  llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-signext.ll
  llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-vectors.ll
  llvm/test/CodeGen/AArch64/GlobalISel/call-lowering-zeroext.ll
  llvm/test/CodeGen/AArch64/GlobalISel/call-translator-tail-call.ll
  llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
  llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-cos.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-exp.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-fexp2.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmaxnum.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-fminnum.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-log.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-log10.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-log2.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-sin.mir
  llvm/test/CodeGen/AArch64/arm64-this-return.ll

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