[llvm] 7910ed1 - [RISCV] Add explicit types to some XTHead isel patterns to reduce RISCVGenDAGISel.inc size.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-02-25T00:40:13-08:00
New Revision: 7910ed1d56c349b76c82d5ebe2f2590770955ff5

URL: https://github.com/llvm/llvm-project/commit/7910ed1d56c349b76c82d5ebe2f2590770955ff5
DIFF: https://github.com/llvm/llvm-project/commit/7910ed1d56c349b76c82d5ebe2f2590770955ff5.diff

LOG: [RISCV] Add explicit types to some XTHead isel patterns to reduce RISCVGenDAGISel.inc size.

HWMode expansion of GPR can create patterns with i32 types with
Subtarget->is64Bit() or i64 types with !Subtarget->is64Bit().
These patterns will never match. They just waste space in the table.

By adding explicit i32 or i64 to patterns that only apply to RV32
or RV64 we can filter these patterns.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
index 275903211762..2153944b32bc 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
@@ -770,7 +770,7 @@ def : Pat<(vt (LoadOp (AddrRegRegScale GPR:$rs1, GPR:$rs2, uimm2:$uimm2))),
 }
 
 multiclass LdZextIdxPat<PatFrag LoadOp, RVInst Inst, ValueType vt = i64> {
-def : Pat<(vt (LoadOp (AddrRegZextRegScale GPR:$rs1, GPR:$rs2, uimm2:$uimm2))),
+def : Pat<(vt (LoadOp (AddrRegZextRegScale (i64 GPR:$rs1), GPR:$rs2, uimm2:$uimm2))),
           (Inst GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;
 }
 
@@ -784,7 +784,7 @@ def : Pat<(StoreOp (vt StTy:$rd),
 multiclass StZextIdxPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy,
                         ValueType vt = i64> {
 def : Pat<(StoreOp (vt StTy:$rd),
-            (AddrRegZextRegScale GPR:$rs1, GPR:$rs2, uimm2:$uimm2)),
+            (AddrRegZextRegScale (i64 GPR:$rs1), GPR:$rs2, uimm2:$uimm2)),
           (Inst StTy:$rd, GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;
 }
 
@@ -869,13 +869,13 @@ defm : StoreUpdatePat<pre_truncsti16, TH_SHIB>;
 }
 
 let Predicates = [HasVendorXTHeadMemIdx, IsRV32] in {
-defm : StoreUpdatePat<post_store, TH_SWIA>;
-defm : StoreUpdatePat<pre_store, TH_SWIB>;
+defm : StoreUpdatePat<post_store, TH_SWIA, i32>;
+defm : StoreUpdatePat<pre_store, TH_SWIB, i32>;
 }
 
 let Predicates = [HasVendorXTHeadMemIdx, IsRV64] in {
-defm : StoreUpdatePat<post_truncsti32, TH_SWIA>;
-defm : StoreUpdatePat<pre_truncsti32, TH_SWIB>;
-defm : StoreUpdatePat<post_store, TH_SDIA>;
-defm : StoreUpdatePat<pre_store, TH_SDIB>;
+defm : StoreUpdatePat<post_truncsti32, TH_SWIA, i64>;
+defm : StoreUpdatePat<pre_truncsti32, TH_SWIB, i64>;
+defm : StoreUpdatePat<post_store, TH_SDIA, i64>;
+defm : StoreUpdatePat<pre_store, TH_SDIB, i64>;
 }