[PATCH] D144442: [X86] Add tests for replacing `{v}unpck{l|h}pd` -> `{v}shufps`; NFC

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n updated this revision to Diff 500305.
goldstein.w.n added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144442/new/

https://reviews.llvm.org/D144442

Files:
  llvm/test/CodeGen/X86/tuning-shuffle-unpckpd.ll


Index: llvm/test/CodeGen/X86/tuning-shuffle-unpckpd.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/tuning-shuffle-unpckpd.ll
@@ -0,0 +1,77 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skylake-avx512  | FileCheck %s --check-prefixes=CHECK,CHECK-512,CHECK-SKX
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skylake  | FileCheck %s --check-prefixes=CHECK,CHECK-SKL
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=icelake-server  | FileCheck %s --check-prefixes=CHECK,CHECK-512,CHECK-ICX
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4  | FileCheck %s --check-prefixes=CHECK,CHECK-512,CHECK-V4
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver4  | FileCheck %s --check-prefixes=CHECK,CHECK-512,CHECK-ZNVER4
+
+define <16 x float> @transform_VUNPCKLPDZrr(<16 x float> %a, <16 x float> %b) nounwind {
+; CHECK-512-LABEL: transform_VUNPCKLPDZrr:
+; CHECK-512:       # %bb.0:
+; CHECK-512-NEXT:    vunpcklpd {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]
+; CHECK-512-NEXT:    retq
+;
+; CHECK-SKL-LABEL: transform_VUNPCKLPDZrr:
+; CHECK-SKL:       # %bb.0:
+; CHECK-SKL-NEXT:    vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm2[0],ymm0[2],ymm2[2]
+; CHECK-SKL-NEXT:    vunpcklpd {{.*#+}} ymm1 = ymm1[0],ymm3[0],ymm1[2],ymm3[2]
+; CHECK-SKL-NEXT:    retq
+  %shufp = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 4, i32 5, i32 20, i32 21, i32 8, i32 9, i32 24, i32 25, i32 12, i32 13, i32 28, i32 29>
+  ret <16 x float> %shufp
+}
+
+define <16 x float> @transform_VUNPCKHPDZrr(<16 x float> %a, <16 x float> %b) nounwind {
+; CHECK-512-LABEL: transform_VUNPCKHPDZrr:
+; CHECK-512:       # %bb.0:
+; CHECK-512-NEXT:    vunpckhpd {{.*#+}} zmm0 = zmm0[1],zmm1[1],zmm0[3],zmm1[3],zmm0[5],zmm1[5],zmm0[7],zmm1[7]
+; CHECK-512-NEXT:    retq
+;
+; CHECK-SKL-LABEL: transform_VUNPCKHPDZrr:
+; CHECK-SKL:       # %bb.0:
+; CHECK-SKL-NEXT:    vunpckhpd {{.*#+}} ymm0 = ymm0[1],ymm2[1],ymm0[3],ymm2[3]
+; CHECK-SKL-NEXT:    vunpckhpd {{.*#+}} ymm1 = ymm1[1],ymm3[1],ymm1[3],ymm3[3]
+; CHECK-SKL-NEXT:    retq
+  %shufp = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> <i32 2, i32 3, i32 18, i32 19, i32 6, i32 7, i32 22, i32 23, i32 10, i32 11, i32 26, i32 27, i32 14, i32 15, i32 30, i32 31>
+  ret <16 x float> %shufp
+}
+
+define <8 x float> @transform_VUNPCKLPDYrr(<8 x float> %a, <8 x float> %b) nounwind {
+; CHECK-LABEL: transform_VUNPCKLPDYrr:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
+; CHECK-NEXT:    retq
+  %shufp = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 4, i32 5, i32 12, i32 13>
+  ret <8 x float> %shufp
+}
+
+define <8 x float> @transform_VUNPCKHPDYrr(<8 x float> %a, <8 x float> %b) nounwind {
+; CHECK-LABEL: transform_VUNPCKHPDYrr:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vunpckhpd {{.*#+}} ymm0 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
+; CHECK-NEXT:    retq
+  %shufp = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 2, i32 3, i32 10, i32 11, i32 6, i32 7, i32 14, i32 15>
+  ret <8 x float> %shufp
+}
+
+define <4 x float> @transform_VUNPCKLPDrr(<4 x float> %a, <4 x float> %b) nounwind {
+; CHECK-LABEL: transform_VUNPCKLPDrr:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; CHECK-NEXT:    retq
+  %shufp = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
+  ret <4 x float> %shufp
+}
+
+define <4 x float> @transform_VUNPCKHPDrr(<4 x float> %a, <4 x float> %b) nounwind {
+; CHECK-LABEL: transform_VUNPCKHPDrr:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
+; CHECK-NEXT:    retq
+  %shufp = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 3, i32 6, i32 7>
+  ret <4 x float> %shufp
+}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-ICX: {{.*}}
+; CHECK-SKX: {{.*}}
+; CHECK-V4: {{.*}}
+; CHECK-ZNVER4: {{.*}}


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