[llvm] b474739 - [PowerPC] Add Binary Coded Decimal Assist Instructions
Stefan Pintilie via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 24 13:00:00 PST 2023
Author: Stefan Pintilie
Date: 2023-02-24T15:59:49-05:00
New Revision: b47473908b32ae6de0c92a0831f85acbd7ef3dea
URL: https://github.com/llvm/llvm-project/commit/b47473908b32ae6de0c92a0831f85acbd7ef3dea
DIFF: https://github.com/llvm/llvm-project/commit/b47473908b32ae6de0c92a0831f85acbd7ef3dea.diff
LOG: [PowerPC] Add Binary Coded Decimal Assist Instructions
This patch adds three instructions for Binary Coded Decimal (BCD).
They are: cdtbcd, cbcdtd, addg6s.
Reviewed By: amyk
Differential Revision: https://reviews.llvm.org/D144068
Added:
Modified:
llvm/lib/Target/PowerPC/P10InstrResources.td
llvm/lib/Target/PowerPC/P9InstrResources.td
llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
llvm/test/MC/PowerPC/ppc64-encoding.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/P10InstrResources.td b/llvm/lib/Target/PowerPC/P10InstrResources.td
index f7d07a06c33eb..b96fdb00306d1 100644
--- a/llvm/lib/Target/PowerPC/P10InstrResources.td
+++ b/llvm/lib/Target/PowerPC/P10InstrResources.td
@@ -650,6 +650,8 @@ def : InstRW<[P10W_F2_4C, P10W_DISP_ANY],
// 4 Cycles ALU2 operations, 1 input operands
def : InstRW<[P10W_F2_4C, P10W_DISP_ANY, P10F2_Read],
(instrs
+ CBCDTD, CBCDTD8,
+ CDTBCD, CDTBCD8,
CNTLZD,
CNTLZD_rec,
CNTLZW, CNTLZW8,
@@ -1203,6 +1205,13 @@ def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_DISP_ANY, P10FX_Read, P10FX_Read]
SUBF8O_rec, SUBFO_rec
)>;
+// 2-way crack instructions
+// 3 Cycles ALU operations, and 4 Cycles ALU2 operations, 2 input operands
+def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_F2_4C, P10W_DISP_ANY],
+ (instrs
+ ADDG6S, ADDG6S8
+)>;
+
// 2-way crack instructions
// 3 Cycles ALU operations, and 3 Cycles ALU operations, 0 input operands
def : InstRW<[P10W_FX_3C, P10W_DISP_EVEN, P10W_FX_3C, P10W_DISP_ANY],
diff --git a/llvm/lib/Target/PowerPC/P9InstrResources.td b/llvm/lib/Target/PowerPC/P9InstrResources.td
index ac20dd353c849..62275722a9635 100644
--- a/llvm/lib/Target/PowerPC/P9InstrResources.td
+++ b/llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -1430,5 +1430,8 @@ def : InstRW<[],
DCCCI,
ICCCI,
ADDEX,
- ADDEX8
+ ADDEX8,
+ CDTBCD, CDTBCD8,
+ CBCDTD, CBCDTD8,
+ ADDG6S, ADDG6S8
)> { let Unsupported = 1; }
diff --git a/llvm/lib/Target/PowerPC/PPCBack2BackFusion.def b/llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
index 1fbe94eb310f7..5d97d187b2969 100644
--- a/llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
+++ b/llvm/lib/Target/PowerPC/PPCBack2BackFusion.def
@@ -50,6 +50,10 @@ FUSION_FEATURE(GeneralBack2Back, hasBack2BackFusion, -1,
ANDIS_rec,
ANDI_rec,
AND_rec,
+ CBCDTD,
+ CBCDTD8,
+ CDTBCD,
+ CDTBCD8,
CMPB,
CMPB8,
CNTLZD,
@@ -535,6 +539,10 @@ FUSION_FEATURE(GeneralBack2Back, hasBack2BackFusion, -1,
ANDIS_rec,
ANDI_rec,
AND_rec,
+ CBCDTD,
+ CBCDTD8,
+ CDTBCD,
+ CDTBCD8,
CMPB,
CMPB8,
CMPD,
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index 0c38aba30d9bb..3ce7c04fea63e 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -993,11 +993,20 @@ def POPCNTW : XForm_11<31, 378, (outs gprc:$RA), (ins gprc:$RST),
"popcntw $RA, $RST", IIC_IntGeneral,
[(set i32:$RA, (ctpop i32:$RST))]>;
-let isCodeGenOnly = 1 in
+let isCodeGenOnly = 1 in {
def POPCNTB8 : XForm_11<31, 122, (outs g8rc:$RA), (ins g8rc:$RST),
"popcntb $RA, $RST", IIC_IntGeneral,
[(set i64:$RA, (int_ppc_popcntb i64:$RST))]>;
+def CDTBCD8 : XForm_11<31, 282, (outs g8rc:$RA), (ins g8rc:$RST),
+ "cdtbcd $RA, $RST", IIC_IntGeneral, []>;
+def CBCDTD8 : XForm_11<31, 314, (outs g8rc:$RA), (ins g8rc:$RST),
+ "cbcdtd $RA, $RST", IIC_IntGeneral, []>;
+
+def ADDG6S8 : XOForm_1<31, 74, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
+ "addg6s $RT, $RA, $RB", IIC_IntGeneral, []>;
+}
+
defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
"divd", "$RT, $RA, $RB", IIC_IntDivD,
[(set i64:$RT, (sdiv i64:$RA, i64:$RB))]>, isPPC64;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index af8533e1f9f64..d18dbd86d94a0 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1822,6 +1822,14 @@ def POPCNTB : XForm_11<31, 122, (outs gprc:$RA), (ins gprc:$RST),
"popcntb $RA, $RST", IIC_IntGeneral,
[(set i32:$RA, (int_ppc_popcntb i32:$RST))]>;
+def CDTBCD : XForm_11<31, 282, (outs gprc:$RA), (ins gprc:$RST),
+ "cdtbcd $RA, $RST", IIC_IntGeneral, []>;
+def CBCDTD : XForm_11<31, 314, (outs gprc:$RA), (ins gprc:$RST),
+ "cbcdtd $RA, $RST", IIC_IntGeneral, []>;
+
+def ADDG6S : XOForm_1<31, 74, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
+ "addg6s $RT, $RA, $RB", IIC_IntGeneral, []>;
+
//===----------------------------------------------------------------------===//
// PPC32 Load Instructions.
//
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
index c79e20b31f948..1050a324767e0 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt
@@ -841,6 +841,15 @@
# CHECK: extswsli. 2, 3, 4
0x7c 0x62 0x26 0xf5
+# CHECK: cdtbcd 2, 7
+0x7c 0xe2 0x02 0x34
+
+# CHECK: cbcdtd 2, 7
+0x7c 0xe2 0x02 0x74
+
+# CHECK: addg6s 2, 3, 4
+0x7c 0x43 0x20 0x94
+
# CHECK: mtspr 600, 2
0x7c 0x58 0x93 0xa6
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
index f005b252c1dc8..bdade9867ed6f 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt
@@ -781,6 +781,15 @@
# CHECK: srad. 2, 3, 4
0x35 0x26 0x62 0x7c
+# CHECK: cdtbcd 2, 7
+0x34 0x02 0xe2 0x7c
+
+# CHECK: cbcdtd 2, 7
+0x74 0x02 0xe2 0x7c
+
+# CHECK: addg6s 2, 3, 4
+0x94 0x20 0x43 0x7c
+
# CHECK: mtspr 600, 2
0xa6 0x93 0x58 0x7c
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding.s b/llvm/test/MC/PowerPC/ppc64-encoding.s
index ddc9e72ad3eba..149ee005b4c30 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding.s
@@ -1023,7 +1023,17 @@
extswsli. 2, 3, 4
-# FIXME: BCD assist instructions
+# BCD assist instructions
+
+# CHECK-BE: cdtbcd 2, 7 # encoding: [0x7c,0xe2,0x02,0x34]
+# CHECK-LE: cdtbcd 2, 7 # encoding: [0x34,0x02,0xe2,0x7c]
+ cdtbcd 2, 7
+# CHECK-BE: cbcdtd 2, 7 # encoding: [0x7c,0xe2,0x02,0x74]
+# CHECK-LE: cbcdtd 2, 7 # encoding: [0x74,0x02,0xe2,0x7c]
+ cbcdtd 2, 7
+# CHECK-BE: addg6s 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x94]
+# CHECK-LE: addg6s 2, 3, 4 # encoding: [0x94,0x20,0x43,0x7c]
+ addg6s 2, 3, 4
# Move to/from system register instructions
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