[PATCH] D143361: [RISCV] Support __builtin_nontemporal_load/store by MachineMemOperand

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D143361#4150627 <https://reviews.llvm.org/D143361#4150627>, @reames wrote:

> The way other targets appear to be approach this is to modify ISEL.  Can you explain why you believe the late hint insertion pass is the right approach here?  The alternative would be to have a family of non-temporal pseudos which expanded into a hint + a memory op.  I don't have a strong opinion, just curious for the justification.

I think this was to reduce the number of vector pseudos required. There 2088 vector pseudos today if you considered unit stride, strided, indexed(with different eews for index). Then there are segment versions of those with different seqment sizes. Then there are masked, unmasked, and tail undisturbed versions. For full generality we would need to apply non-temporal hint to all of them. Though __builtin_nontemporal_load doesn't need all of those variations we could have target specific intrinsics that do.


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https://reviews.llvm.org/D143361