[PATCH] D142231: [AMDGPU][AsmParser] Forbid optional SMRD offsets on GFX6/GFX7.
Ivan Kosarev via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 24 09:25:30 PST 2023
kosarev updated this revision to Diff 500237.
kosarev added a comment.
Reworked to keep optional offsets.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D142231/new/
https://reviews.llvm.org/D142231
Files:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/SMInstructions.td
llvm/test/MC/AMDGPU/smrd.s
Index: llvm/test/MC/AMDGPU/smrd.s
===================================================================
--- llvm/test/MC/AMDGPU/smrd.s
+++ llvm/test/MC/AMDGPU/smrd.s
@@ -11,6 +11,12 @@
// Offset Handling
//===----------------------------------------------------------------------===//
+// SP3 requires the immediate offset, but we allow to drop it for
+// compatibility reasons.
+s_load_dword s1, s[2:3]
+// GCN: s_load_dword s1, s[2:3], 0x0 ; encoding: [0x00,0x83,0x00,0xc0]
+// VI: s_load_dword s1, s[2:3], 0x0 ; encoding: [0x41,0x00,0x02,0xc0,0x00,0x00,0x00,0x00]
+
s_load_dword s1, s[2:3], 0xfc
// GCN: s_load_dword s1, s[2:3], 0xfc ; encoding: [0xfc,0x83,0x00,0xc0]
// VI: s_load_dword s1, s[2:3], 0xfc ; encoding: [0x41,0x00,0x02,0xc0,0xfc,0x00,0x00,0x00]
Index: llvm/lib/Target/AMDGPU/SMInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/SMInstructions.td
+++ llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -756,8 +756,12 @@
// CI
//===----------------------------------------------------------------------===//
+def SMRDLiteralOffsetClass : NamedMatchClass<"SMRDLiteralOffset", 0> {
+ let ParserMethod = "";
+}
+
def smrd_literal_offset : NamedOperandU32<"SMRDLiteralOffset",
- NamedMatchClass<"SMRDLiteralOffset">> {
+ SMRDLiteralOffsetClass> {
let OperandType = "OPERAND_IMMEDIATE";
}
Index: llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1755,7 +1755,6 @@
AMDGPUOperand::Ptr defaultSMRDOffset8() const;
AMDGPUOperand::Ptr defaultSMEMOffset() const;
- AMDGPUOperand::Ptr defaultSMRDLiteralOffset() const;
AMDGPUOperand::Ptr defaultFlatOffset() const;
OperandMatchResultTy parseOModOperand(OperandVector &Operands);
@@ -7973,17 +7972,13 @@
}
AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSMRDOffset8() const {
- return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
+ return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyNone);
}
AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSMEMOffset() const {
return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
}
-AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSMRDLiteralOffset() const {
- return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
-}
-
AMDGPUOperand::Ptr AMDGPUAsmParser::defaultFlatOffset() const {
return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
}
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