[PATCH] D144715: [AMDGPU] Use `S_BFE_U64` for uniform i1-i64 ext

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/saddo.ll:32
 ; SI-NEXT:    s_xor_b64 s[4:5], s[6:7], vcc
-; SI-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
-; SI-NEXT:    v_mov_b32_e32 v1, s11
-; SI-NEXT:    v_add_i32_e32 v0, vcc, s10, v0
-; SI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; SI-NEXT:    s_bfe_u64 s[4:5], s[4:5], 0x10000
+; SI-NEXT:    s_add_u32 s4, s10, s4
----------------
Pierre-vh wrote:
> foad wrote:
> > I'm not sure this is correct. The old code treated s[4:5] like a divergent boolean, with a bit for each *active* lane. The new code assumes the boolean value is in bit 0 - but will that work if lane 0 is not active?
> Very good question; I have a bit of trouble following what V_CNDMASK does exactly in this case.
> v0 is the destination, but what do the 0/1/s[4:5] correspond to?
> 
> This function doesn't seem to select with global isel so I can't compare with that
For each active lane, v0 get 0 if the corresponding bit of s[4:5] if 0, 1 if the corresponding bit is 1.

`v_cndmask v0, v1, v2, s0` is a bit like `v0 = s0 ? v2 : v1` (NB v1/v2 are swapped!) where s0 holds the condition as a divergent boolean, 1 bit per lane.


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  https://reviews.llvm.org/D144715/new/

https://reviews.llvm.org/D144715