[PATCH] D144681: [RISCV] Add vendor-defined XTheadCondMov (conditional move) extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td:661
+          (MVEQZ $rd, X0, $x)>;
+def : Pat<(select (XLenVT (setne GPR:$x, (XLenVT 0))), GPR:$rd, GPR:$rs1),
+          (MVEQZ $rd, $rs1, $x)>;
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philipp.tomsich wrote:
> craig.topper wrote:
> > This pattern is identical to line 653.
> Due to the register constraints ($rd being in/out) it should help to minimize unneeded register moves (my testing may have been biased, though).
> 
> Will the pattern at 653 always trigger, even if the register constraint on $rd make this one preferable?
Yes the pattern at 653 will always trigger. The isel pattern matching doesn't know anything about the register constraint.  Adding support to `commuteInstruction` will allow the TwoAddressInstruction pass to commute it if the tied operand is needed after the instruction, but the untied operand isn't needed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144681/new/

https://reviews.llvm.org/D144681