[PATCH] D144681: [RISCV] Add vendor-defined XTheadCondMov (conditional move) extension

[Philipp Tomsich via Phabricator via llvm-commits]

philipp.tomsich added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td:661
+          (MVEQZ $rd, X0, $x)>;
+def : Pat<(select (XLenVT (setne GPR:$x, (XLenVT 0))), GPR:$rd, GPR:$rs1),
+          (MVEQZ $rd, $rs1, $x)>;
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craig.topper wrote:
> This pattern is identical to line 653.
Due to the register constraints ($rd being in/out) it should help to minimize unneeded register moves (my testing may have been biased, though).

Will the pattern at 653 always trigger, even if the register constraint on $rd make this one preferable?


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  https://reviews.llvm.org/D144681/new/

https://reviews.llvm.org/D144681