[PATCH] D144700: [RISCV] Use ComplexPattern to reduce the number of patterns for XVentanaCondOps.

[Craig Topper via Phabricator via llvm-commits]

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XVentanaCondOps check the condition operand for zero or non-zero.
We use this to optimize seteq/setne that would otherwise becomes
xor/xori/addi+snez/seqz. These patterns avoid the snez/seqz.

This patch adds two ComplexPatterns to match the varous cases and
emit the xor/xori/addi instruction.

These patterns can also be used by D144681 <https://reviews.llvm.org/D144681>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D144700

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td

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