[PATCH] D144681: [RISCV] Add vendor-defined XTheadCondMov (conditional move) extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/docs/RISCVUsage.rst:190
+``XTHeadCondmov``
+  LLVM implements `the THeadCondmov (conditional move) vendor-defined instructions specified in <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf>`_  by T-HEAD of Alibaba.  Instructions are prefixed with `th.` as described in the specification.
+
----------------
mov -> Mov


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td:649
+          (MVNEZ $rd, X0, $rs2)>;
+def : Pat<(select GPR:$rs2, GPR:$rs1, GPR:$rd),
+          (MVNEZ $rd, $rs1, $rs2)>;
----------------
As far as tablegen is concerned this pattern is the same as the pattern on line 643.

I think you need to make these instruction commutable and teach the commuting hooks in RISCVInstrInfo about it.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td:661
+          (MVEQZ $rd, X0, $x)>;
+def : Pat<(select (XLenVT (setne GPR:$x, (XLenVT 0))), GPR:$rd, GPR:$rs1),
+          (MVEQZ $rd, $rs1, $x)>;
----------------
This pattern is identical to line 653.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td:663
+          (MVEQZ $rd, $rs1, $x)>;
+def : Pat<(select (XLenVT (seteq GPR:$x, (XLenVT 0))), GPR:$rd, GPR:$rs1),
+          (MVNEZ $rd, $rs1, $x)>;
----------------
This pattern is identical to line 655


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td:679
+          (MVEQZ $rd, X0, (XOR $x, $y))>;
+def : Pat<(select (XLenVT (setne GPR:$x, GPR:$y)), GPR:$rd, GPR:$rs1),
+          (MVEQZ $rd, $rs1, (XOR $x, $y))>;
----------------
Redundant


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td:681
+          (MVEQZ $rd, $rs1, (XOR $x, $y))>;
+def : Pat<(select (XLenVT (seteq GPR:$x, GPR:$y)), GPR:$rd, GPR:$rs1),
+          (MVNEZ $rd, $rs1, (XOR $x, $y))>;
----------------
Redundant


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td:697
+          (MVEQZ $rd, X0, (XORI $x, simm12:$i))>;
+def : Pat<(select (XLenVT (setne GPR:$x, simm12:$i)), GPR:$rd, GPR:$rs1),
+          (MVEQZ $rd, $rs1, (XORI $x, simm12:$i))>;
----------------
Redundant


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td:699
+          (MVEQZ $rd, $rs1, (XORI $x, simm12:$i))>;
+def : Pat<(select (XLenVT (seteq GPR:$x, simm12:$i)), GPR:$rd, GPR:$rs1),
+          (MVNEZ $rd, $rs1, (XORI $x, simm12:$i))>;
----------------
Redundant


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td:719
+          (MVEQZ $rd, X0, (ADDI $x, -2048))>;
+def : Pat<(select (XLenVT (setne GPR:$x, 2048)), GPR:$rd, GPR:$rs1),
+          (MVEQZ $rd, $rs1, (ADDI $x, -2048))>;
----------------
Redundant


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td:721
+          (MVEQZ $rd, $rs1, (ADDI $x, -2048))>;
+def : Pat<(select (XLenVT (seteq GPR:$x, 2048)), GPR:$rd, GPR:$rs1),
+          (MVNEZ $rd, $rs1, (ADDI $x, -2048))>;
----------------
Redundant


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144681/new/

https://reviews.llvm.org/D144681