[PATCH] D144681: [RISCV] Add vendor-defined XTheadCondMov (conditional move) extension

[Philipp Tomsich via Phabricator via llvm-commits]

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The vendor-defined XTheadCondMov (somewhat related to the upcoming
Zicond and XVentanaCondOps) extension add conditional move
instructions with $rd being an input and an ouput instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1 <https://reviews.llvm.org/D1>) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:

  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:

  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=73442230966a22b3238b2074691a71d7b4ed914a


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D144681

Files:
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/condops.ll
  llvm/test/CodeGen/RISCV/xventanacondops.ll
  llvm/test/MC/RISCV/xtheadcondmov-invalid.s
  llvm/test/MC/RISCV/xtheadcondmov-valid.s

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