[llvm] 230e616 - [LegalizeTypes] Add a special case for (add X, 1) to ExpandIntRes_ADDSUB.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 23 09:48:45 PST 2023
Author: Craig Topper
Date: 2023-02-23T09:47:42-08:00
New Revision: 230e61658b5e5c91f631459511f0efb4b15f8c77
URL: https://github.com/llvm/llvm-project/commit/230e61658b5e5c91f631459511f0efb4b15f8c77
DIFF: https://github.com/llvm/llvm-project/commit/230e61658b5e5c91f631459511f0efb4b15f8c77.diff
LOG: [LegalizeTypes] Add a special case for (add X, 1) to ExpandIntRes_ADDSUB.
On targets without ADDCARRY or ADDE, we need to emit a separate
SETCC to determine carry from the low half to the high half. Usually
we do (setult Lo, LHSLo). If RHSLo is 1 we can instead do (seteq Lo, 0).
This can reduce the live range of LHSLo.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/test/CodeGen/RISCV/alu64.ll
llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
llvm/test/CodeGen/RISCV/branch-on-zero.ll
llvm/test/CodeGen/RISCV/forced-atomics.ll
llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
llvm/test/CodeGen/RISCV/xaluo.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 22d997bce18b..f2e728e8b1cc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -3014,8 +3014,15 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
if (N->getOpcode() == ISD::ADD) {
Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
Hi = DAG.getNode(ISD::ADD, dl, NVT, ArrayRef(HiOps, 2));
- SDValue Cmp = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
- ISD::SETULT);
+ SDValue Cmp;
+ // Special case: X+1 has a carry out if X+1==0. This may reduce the live
+ // range of X. We assume comparing with 0 is cheap.
+ if (isOneConstant(LoOps[1]))
+ Cmp = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
+ DAG.getConstant(0, dl, NVT), ISD::SETEQ);
+ else
+ Cmp = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
+ ISD::SETULT);
SDValue Carry;
if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
diff --git a/llvm/test/CodeGen/RISCV/alu64.ll b/llvm/test/CodeGen/RISCV/alu64.ll
index 9743c49f82d7..5349c82ef0f0 100644
--- a/llvm/test/CodeGen/RISCV/alu64.ll
+++ b/llvm/test/CodeGen/RISCV/alu64.ll
@@ -19,10 +19,9 @@ define i64 @addi(i64 %a) nounwind {
;
; RV32I-LABEL: addi:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi a2, a0, 1
-; RV32I-NEXT: sltu a0, a2, a0
-; RV32I-NEXT: add a1, a1, a0
-; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: addi a0, a0, 1
+; RV32I-NEXT: seqz a2, a0
+; RV32I-NEXT: add a1, a1, a2
; RV32I-NEXT: ret
%1 = add i64 %a, 1
ret i64 %1
diff --git a/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll b/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
index a12985c701b9..7c871089bca0 100644
--- a/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
+++ b/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
@@ -492,7 +492,7 @@ define i64 @atomicrmw_uinc_wrap_i64(ptr %ptr, i64 %val) {
; RV32I-NEXT: # in Loop: Header=BB3_3 Depth=1
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: addi a1, a4, 1
-; RV32I-NEXT: sltu a2, a1, a4
+; RV32I-NEXT: seqz a2, a1
; RV32I-NEXT: add a3, a5, a2
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and a2, a0, a1
@@ -548,7 +548,7 @@ define i64 @atomicrmw_uinc_wrap_i64(ptr %ptr, i64 %val) {
; RV32IA-NEXT: # in Loop: Header=BB3_3 Depth=1
; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: addi a1, a4, 1
-; RV32IA-NEXT: sltu a2, a1, a4
+; RV32IA-NEXT: seqz a2, a1
; RV32IA-NEXT: add a3, a5, a2
; RV32IA-NEXT: addi a0, a0, -1
; RV32IA-NEXT: and a2, a0, a1
diff --git a/llvm/test/CodeGen/RISCV/branch-on-zero.ll b/llvm/test/CodeGen/RISCV/branch-on-zero.ll
index a08388a48ee1..7a9cd5ced955 100644
--- a/llvm/test/CodeGen/RISCV/branch-on-zero.ll
+++ b/llvm/test/CodeGen/RISCV/branch-on-zero.ll
@@ -46,10 +46,9 @@ define i64 @optbranch_64(i64 %Arg) {
; RV32-NEXT: li a3, -1
; RV32-NEXT: beq a2, a3, .LBB1_2
; RV32-NEXT: # %bb.1: # %bb3
-; RV32-NEXT: addi a2, a0, 1
-; RV32-NEXT: sltu a0, a2, a0
-; RV32-NEXT: add a1, a1, a0
-; RV32-NEXT: mv a0, a2
+; RV32-NEXT: addi a0, a0, 1
+; RV32-NEXT: seqz a2, a0
+; RV32-NEXT: add a1, a1, a2
; RV32-NEXT: ret
; RV32-NEXT: .LBB1_2: # %bb2
; RV32-NEXT: li a0, -1
diff --git a/llvm/test/CodeGen/RISCV/forced-atomics.ll b/llvm/test/CodeGen/RISCV/forced-atomics.ll
index 566b54054790..1bc88567d9ec 100644
--- a/llvm/test/CodeGen/RISCV/forced-atomics.ll
+++ b/llvm/test/CodeGen/RISCV/forced-atomics.ll
@@ -3512,9 +3512,13 @@ define i128 @rmw128(ptr %p) nounwind {
; RV32-NEXT: lw a3, 4(s0)
; RV32-NEXT: lw a4, 0(s0)
; RV32-NEXT: mv s1, a0
-; RV32-NEXT: j .LBB62_2
; RV32-NEXT: .LBB62_1: # %atomicrmw.start
-; RV32-NEXT: # in Loop: Header=BB62_2 Depth=1
+; RV32-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32-NEXT: addi a0, a4, 1
+; RV32-NEXT: seqz a5, a0
+; RV32-NEXT: add a5, a3, a5
+; RV32-NEXT: or a6, a0, a5
+; RV32-NEXT: seqz a6, a6
; RV32-NEXT: add a6, a2, a6
; RV32-NEXT: sltu a7, a6, a2
; RV32-NEXT: add a7, a1, a7
@@ -3537,18 +3541,8 @@ define i128 @rmw128(ptr %p) nounwind {
; RV32-NEXT: lw a2, 24(sp)
; RV32-NEXT: lw a3, 20(sp)
; RV32-NEXT: lw a4, 16(sp)
-; RV32-NEXT: bnez a0, .LBB62_4
-; RV32-NEXT: .LBB62_2: # %atomicrmw.start
-; RV32-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32-NEXT: addi a0, a4, 1
-; RV32-NEXT: sltu a6, a0, a4
-; RV32-NEXT: add a5, a3, a6
-; RV32-NEXT: bgeu a0, a4, .LBB62_1
-; RV32-NEXT: # %bb.3: # %atomicrmw.start
-; RV32-NEXT: # in Loop: Header=BB62_2 Depth=1
-; RV32-NEXT: sltu a6, a5, a3
-; RV32-NEXT: j .LBB62_1
-; RV32-NEXT: .LBB62_4: # %atomicrmw.end
+; RV32-NEXT: beqz a0, .LBB62_1
+; RV32-NEXT: # %bb.2: # %atomicrmw.end
; RV32-NEXT: sw a4, 0(s1)
; RV32-NEXT: sw a3, 4(s1)
; RV32-NEXT: sw a2, 8(s1)
diff --git a/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll b/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
index c7fab1767ea1..fea0199c8cfe 100644
--- a/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
+++ b/llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
@@ -520,7 +520,7 @@ define i1 @uaddo_i64_increment(i64 %x, ptr %p) {
; RV32-LABEL: uaddo_i64_increment:
; RV32: # %bb.0:
; RV32-NEXT: addi a3, a0, 1
-; RV32-NEXT: sltu a0, a3, a0
+; RV32-NEXT: seqz a0, a3
; RV32-NEXT: add a1, a1, a0
; RV32-NEXT: or a0, a3, a1
; RV32-NEXT: seqz a0, a0
@@ -622,7 +622,7 @@ define i1 @uaddo_i64_increment_alt(i64 %x, ptr %p) {
; RV32-LABEL: uaddo_i64_increment_alt:
; RV32: # %bb.0:
; RV32-NEXT: addi a3, a0, 1
-; RV32-NEXT: sltu a4, a3, a0
+; RV32-NEXT: seqz a4, a3
; RV32-NEXT: add a4, a1, a4
; RV32-NEXT: sw a3, 0(a2)
; RV32-NEXT: and a0, a0, a1
@@ -651,11 +651,11 @@ define i1 @uaddo_i64_increment_alt_dom(i64 %x, ptr %p) {
; RV32-NEXT: and a3, a0, a1
; RV32-NEXT: addi a3, a3, 1
; RV32-NEXT: seqz a3, a3
-; RV32-NEXT: addi a4, a0, 1
-; RV32-NEXT: sltu a0, a4, a0
-; RV32-NEXT: add a0, a1, a0
-; RV32-NEXT: sw a4, 0(a2)
-; RV32-NEXT: sw a0, 4(a2)
+; RV32-NEXT: addi a0, a0, 1
+; RV32-NEXT: seqz a4, a0
+; RV32-NEXT: add a1, a1, a4
+; RV32-NEXT: sw a0, 0(a2)
+; RV32-NEXT: sw a1, 4(a2)
; RV32-NEXT: mv a0, a3
; RV32-NEXT: ret
;
@@ -733,7 +733,7 @@ define i1 @uaddo_i42_increment_illegal_type(i42 %x, ptr %p) {
; RV32-LABEL: uaddo_i42_increment_illegal_type:
; RV32: # %bb.0:
; RV32-NEXT: addi a3, a0, 1
-; RV32-NEXT: sltu a0, a3, a0
+; RV32-NEXT: seqz a0, a3
; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: andi a1, a0, 1023
; RV32-NEXT: or a0, a3, a1
diff --git a/llvm/test/CodeGen/RISCV/xaluo.ll b/llvm/test/CodeGen/RISCV/xaluo.ll
index 4e26ab228352..e0da75877e31 100644
--- a/llvm/test/CodeGen/RISCV/xaluo.ll
+++ b/llvm/test/CodeGen/RISCV/xaluo.ll
@@ -500,7 +500,7 @@ define zeroext i1 @uaddo.i64.constant_one(i64 %v1, ptr %res) {
; RV32-LABEL: uaddo.i64.constant_one:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi a3, a0, 1
-; RV32-NEXT: sltu a0, a3, a0
+; RV32-NEXT: seqz a0, a3
; RV32-NEXT: add a1, a1, a0
; RV32-NEXT: or a0, a3, a1
; RV32-NEXT: seqz a0, a0
@@ -518,7 +518,7 @@ define zeroext i1 @uaddo.i64.constant_one(i64 %v1, ptr %res) {
; RV32ZBA-LABEL: uaddo.i64.constant_one:
; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: addi a3, a0, 1
-; RV32ZBA-NEXT: sltu a0, a3, a0
+; RV32ZBA-NEXT: seqz a0, a3
; RV32ZBA-NEXT: add a1, a1, a0
; RV32ZBA-NEXT: or a0, a3, a1
; RV32ZBA-NEXT: seqz a0, a0
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