[PATCH] D144249: [RISCV] Add vendor-defined XTheadMemIdx (Indexed Memory Operations) extension

[Manolis Tsamis via Phabricator via llvm-commits]

mtsamis marked 3 inline comments as done.
mtsamis added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:769
+  unsigned Opcode;
+  if (LoadedVT == MVT::i8 && AM == ISD::PRE_INC)
+    Opcode = (Ext == ISD::ZEXTLOAD) ? RISCV::TH_LBUIB : RISCV::TH_LBIB;
----------------
craig.topper wrote:
> Can we put `AM == ISD::PRE_INC` and `Ext == ISD::ZEXTLOAD` into a variables `IsPre` and `IsZExt`. That should reduce the amount of text here.
Thanks for the suggestion, done.

I set `IsPre = (AM == ISD::PRE_INC || AM == ISD::PRE_DEC);` which allowed to remove these statements entirely
```
    if (AM == ISD::PRE_DEC)
      AM = ISD::PRE_INC;
    else if (AM == ISD::POST_DEC)
      AM = ISD::POST_INC;
```


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D144249/new/

https://reviews.llvm.org/D144249