[llvm] 1b9b4f3 - [AMDGPU][NFC] Convert llvm.amdgcn tests to autogen
Piotr Sobczak via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 22 23:21:36 PST 2023
Author: Piotr Sobczak
Date: 2023-02-23T08:21:12+01:00
New Revision: 1b9b4f3bfa8bc7ed7dddd30dd30a07676891bedb
URL: https://github.com/llvm/llvm-project/commit/1b9b4f3bfa8bc7ed7dddd30dd30a07676891bedb
DIFF: https://github.com/llvm/llvm-project/commit/1b9b4f3bfa8bc7ed7dddd30dd30a07676891bedb.diff
LOG: [AMDGPU][NFC] Convert llvm.amdgcn tests to autogen
Added:
Modified:
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
index 50b894ced5261..e6aa6a44bf39c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
@@ -1,14 +1,35 @@
-;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,PREGFX10
-;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,VI,PREGFX10
-;RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,GFX10
-;RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,GFX10
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s --check-prefixes=PREGFX10
+;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefixes=PREGFX10
+;RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck %s --check-prefixes=GFX10
+;RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck %s --check-prefixes=GFX11
-;CHECK-LABEL: {{^}}buffer_load:
-;CHECK: buffer_load_{{dwordx4|b128}} v[0:3], off, s[0:3], 0{{$}}
-;CHECK: buffer_load_{{dwordx4|b128}} v[4:7], off, s[0:3], 0 glc{{$}}
-;CHECK: buffer_load_{{dwordx4|b128}} v[8:11], off, s[0:3], 0 slc{{$}}
-;CHECK: s_waitcnt
define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) {
+; PREGFX10-LABEL: buffer_load:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
+; PREGFX10-NEXT: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc
+; PREGFX10-NEXT: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: buffer_load:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: s_clause 0x2
+; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
+; GFX10-NEXT: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc
+; GFX10-NEXT: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: s_clause 0x2
+; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0
+; GFX11-NEXT: buffer_load_b128 v[4:7], off, s[0:3], 0 glc
+; GFX11-NEXT: buffer_load_b128 v[8:11], off, s[0:3], 0 slc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0)
%data_glc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 1)
@@ -19,15 +40,32 @@ main_body:
ret {<4 x float>, <4 x float>, <4 x float>} %r2
}
-;CHECK-LABEL: {{^}}buffer_load_dlc:
-;PREGFX10: buffer_load_dwordx4 v[0:3], off, s[0:3], 0{{$}}
-;PREGFX10: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc{{$}}
-;PREGFX10: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc{{$}}
-;GFX10: buffer_load_{{dwordx4|b128}} v[0:3], off, s[0:3], 0 dlc{{$}}
-;GFX10: buffer_load_{{dwordx4|b128}} v[4:7], off, s[0:3], 0 glc dlc{{$}}
-;GFX10: buffer_load_{{dwordx4|b128}} v[8:11], off, s[0:3], 0 slc dlc{{$}}
-;CHECK: s_waitcnt
define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load_dlc(<4 x i32> inreg) {
+; PREGFX10-LABEL: buffer_load_dlc:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
+; PREGFX10-NEXT: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc
+; PREGFX10-NEXT: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: buffer_load_dlc:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: s_clause 0x2
+; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 dlc
+; GFX10-NEXT: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc dlc
+; GFX10-NEXT: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc dlc
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_dlc:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: s_clause 0x2
+; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0 dlc
+; GFX11-NEXT: buffer_load_b128 v[4:7], off, s[0:3], 0 glc dlc
+; GFX11-NEXT: buffer_load_b128 v[8:11], off, s[0:3], 0 slc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 4)
%data_glc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 5)
@@ -38,79 +76,189 @@ main_body:
ret {<4 x float>, <4 x float>, <4 x float>} %r2
}
-;CHECK-LABEL: {{^}}buffer_load_immoffs:
-;CHECK: buffer_load_{{dwordx4|b128}} v[0:3], off, s[0:3], 0 offset:40
-;CHECK: s_waitcnt
define amdgpu_ps <4 x float> @buffer_load_immoffs(<4 x i32> inreg) {
+; PREGFX10-LABEL: buffer_load_immoffs:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:40
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: buffer_load_immoffs:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:40
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_immoffs:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0 offset:40
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 40, i32 0, i32 0)
ret <4 x float> %data
}
-;CHECK-LABEL: {{^}}buffer_load_immoffs_large:
-;CHECK: s_movk_i32 [[OFFSET:s[0-9]+]], 0x1ffc
-;CHECK: buffer_load_{{dwordx4|b128}} v[0:3], off, s[0:3], [[OFFSET]] offset:4
-;CHECK: s_waitcnt
define amdgpu_ps <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) {
+; PREGFX10-LABEL: buffer_load_immoffs_large:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: s_movk_i32 s4, 0x1ffc
+; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], s4 offset:4
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: buffer_load_immoffs_large:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: s_movk_i32 s4, 0x1ffc
+; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], s4 offset:4
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_immoffs_large:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: s_movk_i32 s4, 0x1ffc
+; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], s4 offset:4
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 4, i32 8188, i32 0)
ret <4 x float> %data
}
-;CHECK-LABEL: {{^}}buffer_load_ofs:
-;CHECK: buffer_load_{{dwordx4|b128}} v[0:3], v0, s[0:3], 0 offen
-;CHECK: s_waitcnt
define amdgpu_ps <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) {
+; PREGFX10-LABEL: buffer_load_ofs:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: buffer_load_ofs:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_ofs:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 0, i32 0)
ret <4 x float> %data
}
-;CHECK-LABEL: {{^}}buffer_load_ofs_imm:
-;CHECK: buffer_load_{{dwordx4|b128}} v[0:3], v0, s[0:3], 0 offen offset:60
-;CHECK: s_waitcnt
define amdgpu_ps <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) {
+; PREGFX10-LABEL: buffer_load_ofs_imm:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:60
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: buffer_load_ofs_imm:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:60
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_ofs_imm:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen offset:60
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%ofs = add i32 %1, 60
%data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 %ofs, i32 0, i32 0)
ret <4 x float> %data
}
-;CHECK-LABEL: {{^}}buffer_load_x1:
-;CHECK: buffer_load_{{dword|b32}} v0, v0, s[0:3], 0 offen
-;CHECK: s_waitcnt
define amdgpu_ps float @buffer_load_x1(<4 x i32> inreg %rsrc, i32 %ofs) {
+; PREGFX10-LABEL: buffer_load_x1:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: buffer_load_x1:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_x1:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: buffer_load_b32 v0, v0, s[0:3], 0 offen
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 0, i32 0)
ret float %data
}
-;CHECK-LABEL: {{^}}buffer_load_x2:
-;CHECK: buffer_load_{{dwordx2|b64}} v[0:1], v0, s[0:3], 0 offen
-;CHECK: s_waitcnt
define amdgpu_ps <2 x float> @buffer_load_x2(<4 x i32> inreg %rsrc, i32 %ofs) {
+; PREGFX10-LABEL: buffer_load_x2:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_dwordx2 v[0:1], v0, s[0:3], 0 offen
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: buffer_load_x2:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: buffer_load_dwordx2 v[0:1], v0, s[0:3], 0 offen
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_x2:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: buffer_load_b64 v[0:1], v0, s[0:3], 0 offen
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%data = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 0, i32 0)
ret <2 x float> %data
}
-;CHECK-LABEL: {{^}}buffer_load_negative_offset:
-;PREGFX10: v_add_{{[iu]}}32_e32 [[VOFS:v[0-9]+]], vcc, -16, v0
-;GFX10: v_add_nc_{{[iu]}}32_e32 [[VOFS:v[0-9]+]], -16, v0
-;CHECK: buffer_load_{{dwordx4|b128}} v[0:3], [[VOFS]], s[0:3], 0 offen
define amdgpu_ps <4 x float> @buffer_load_negative_offset(<4 x i32> inreg, i32 %ofs) {
+; GFX10-LABEL: buffer_load_negative_offset:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: v_add_nc_u32_e32 v0, -16, v0
+; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_negative_offset:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: v_add_nc_u32_e32 v0, -16, v0
+; GFX11-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%ofs.1 = add i32 %ofs, -16
%data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 %ofs.1, i32 0, i32 0)
ret <4 x float> %data
}
-; SI won't merge ds memory operations, because of the signed offset bug, so
-; we only have check lines for VI.
-; CHECK-LABEL: buffer_load_mmo:
-; VI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0
-; VI: ds_write2_b32 v{{[0-9]+}}, [[ZERO]], [[ZERO]] offset1:4
+
define amdgpu_ps float @buffer_load_mmo(<4 x i32> inreg %rsrc, ptr addrspace(3) %lds) {
+; GFX10-LABEL: buffer_load_mmo:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], 0
+; GFX10-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-NEXT: ds_write2_b32 v0, v2, v2 offset1:4
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: v_mov_b32_e32 v0, v1
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_mmo:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: buffer_load_b32 v1, off, s[0:3], 0
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: ds_store_2addr_b32 v0, v2, v2 offset1:4
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v0, v1
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
entry:
store float 0.0, ptr addrspace(3) %lds
%val = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
@@ -119,13 +267,38 @@ entry:
ret float %val
}
-;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged_and:
-;CHECK-NEXT: %bb.
-;GFX10-NEXT: s_clause
-;CHECK-NEXT: buffer_load_{{dwordx4|b128}} v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4
-;CHECK-NEXT: buffer_load_{{dwordx2|b64}} v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28
-;CHECK: s_waitcnt
define amdgpu_ps void @buffer_load_x1_offen_merged_and(<4 x i32> inreg %rsrc, i32 %a) {
+; PREGFX10-LABEL: buffer_load_x1_offen_merged_and:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:4
+; PREGFX10-NEXT: buffer_load_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28
+; PREGFX10-NEXT: s_waitcnt vmcnt(1)
+; PREGFX10-NEXT: exp mrt0 v1, v2, v3, v4 done vm
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: exp mrt0 v5, v6, v0, v0 done vm
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: buffer_load_x1_offen_merged_and:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: s_clause 0x1
+; GFX10-NEXT: buffer_load_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:4
+; GFX10-NEXT: buffer_load_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28
+; GFX10-NEXT: s_waitcnt vmcnt(1)
+; GFX10-NEXT: exp mrt0 v1, v2, v3, v4 done vm
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: exp mrt0 v5, v6, v0, v0 done vm
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: buffer_load_x1_offen_merged_and:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: buffer_load_b128 v[1:4], v0, s[0:3], 0 offen offset:4
+; GFX11-NEXT: buffer_load_b64 v[5:6], v0, s[0:3], 0 offen offset:28
+; GFX11-NEXT: s_waitcnt vmcnt(1)
+; GFX11-NEXT: exp mrt0 v1, v2, v3, v4 done
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: exp mrt0 v5, v6, v0, v0 done
+; GFX11-NEXT: s_endpgm
main_body:
%a1 = add i32 %a, 4
%a2 = add i32 %a, 8
@@ -144,14 +317,41 @@ main_body:
ret void
}
-;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged_or:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: v_lshlrev_b32_e32 v{{[0-9]}}, 6, v0
-;GFX10-NEXT: s_clause
-;CHECK-NEXT: buffer_load_{{dwordx4|b128}} v[{{[0-9]}}:{{[0-9]}}], v{{[0-9]}}, s[0:3], 0 offen offset:4
-;CHECK-NEXT: buffer_load_{{dwordx2|b64}} v[{{[0-9]}}:{{[0-9]}}], v{{[0-9]}}, s[0:3], 0 offen offset:28
-;CHECK: s_waitcnt
define amdgpu_ps void @buffer_load_x1_offen_merged_or(<4 x i32> inreg %rsrc, i32 %inp) {
+; PREGFX10-LABEL: buffer_load_x1_offen_merged_or:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: v_lshlrev_b32_e32 v4, 6, v0
+; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], v4, s[0:3], 0 offen offset:4
+; PREGFX10-NEXT: buffer_load_dwordx2 v[4:5], v4, s[0:3], 0 offen offset:28
+; PREGFX10-NEXT: s_waitcnt vmcnt(1)
+; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: buffer_load_x1_offen_merged_or:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 6, v0
+; GFX10-NEXT: s_clause 0x1
+; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v6, s[0:3], 0 offen offset:4
+; GFX10-NEXT: buffer_load_dwordx2 v[4:5], v6, s[0:3], 0 offen offset:28
+; GFX10-NEXT: s_waitcnt vmcnt(1)
+; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: buffer_load_x1_offen_merged_or:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 6, v0
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: buffer_load_b128 v[0:3], v4, s[0:3], 0 offen offset:4
+; GFX11-NEXT: buffer_load_b64 v[4:5], v4, s[0:3], 0 offen offset:28
+; GFX11-NEXT: s_waitcnt vmcnt(1)
+; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: exp mrt0 v4, v5, v0, v0 done
+; GFX11-NEXT: s_endpgm
main_body:
%a = shl i32 %inp, 6
%a1 = or i32 %a, 4
@@ -171,14 +371,41 @@ main_body:
ret void
}
-;CHECK-LABEL: {{^}}buffer_load_x1_offen_merged_glc_slc:
-;CHECK-NEXT: %bb.
-;GFX10-NEXT: s_clause
-;CHECK-NEXT: buffer_load_{{dwordx2|b64}} v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4{{$}}
-;CHECK-NEXT: buffer_load_{{dwordx2|b64}} v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:12 glc{{$}}
-;CHECK-NEXT: buffer_load_{{dwordx2|b64}} v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:28 glc slc{{$}}
-;CHECK: s_waitcnt
define amdgpu_ps void @buffer_load_x1_offen_merged_glc_slc(<4 x i32> inreg %rsrc, i32 %a) {
+; PREGFX10-LABEL: buffer_load_x1_offen_merged_glc_slc:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_dwordx2 v[1:2], v0, s[0:3], 0 offen offset:4
+; PREGFX10-NEXT: buffer_load_dwordx2 v[3:4], v0, s[0:3], 0 offen offset:12 glc
+; PREGFX10-NEXT: buffer_load_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28 glc slc
+; PREGFX10-NEXT: s_waitcnt vmcnt(1)
+; PREGFX10-NEXT: exp mrt0 v1, v2, v3, v4 done vm
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: exp mrt0 v5, v6, v0, v0 done vm
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: buffer_load_x1_offen_merged_glc_slc:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: s_clause 0x2
+; GFX10-NEXT: buffer_load_dwordx2 v[1:2], v0, s[0:3], 0 offen offset:4
+; GFX10-NEXT: buffer_load_dwordx2 v[3:4], v0, s[0:3], 0 offen offset:12 glc
+; GFX10-NEXT: buffer_load_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28 glc slc
+; GFX10-NEXT: s_waitcnt vmcnt(1)
+; GFX10-NEXT: exp mrt0 v1, v2, v3, v4 done vm
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: exp mrt0 v5, v6, v0, v0 done vm
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: buffer_load_x1_offen_merged_glc_slc:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: s_clause 0x2
+; GFX11-NEXT: buffer_load_b64 v[1:2], v0, s[0:3], 0 offen offset:4
+; GFX11-NEXT: buffer_load_b64 v[3:4], v0, s[0:3], 0 offen offset:12 glc
+; GFX11-NEXT: buffer_load_b64 v[5:6], v0, s[0:3], 0 offen offset:28 glc slc
+; GFX11-NEXT: s_waitcnt vmcnt(1)
+; GFX11-NEXT: exp mrt0 v1, v2, v3, v4 done
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: exp mrt0 v5, v6, v0, v0 done
+; GFX11-NEXT: s_endpgm
main_body:
%a1 = add i32 %a, 4
%a2 = add i32 %a, 8
@@ -197,11 +424,27 @@ main_body:
ret void
}
-;CHECK-LABEL: {{^}}buffer_load_x2_offen_merged_and:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: buffer_load_{{dwordx4|b128}} v[{{[0-9]}}:{{[0-9]}}], v0, s[0:3], 0 offen offset:4
-;CHECK: s_waitcnt
define amdgpu_ps void @buffer_load_x2_offen_merged_and(<4 x i32> inreg %rsrc, i32 %a) {
+; PREGFX10-LABEL: buffer_load_x2_offen_merged_and:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: buffer_load_x2_offen_merged_and:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: buffer_load_x2_offen_merged_and:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen offset:4
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done
+; GFX11-NEXT: s_endpgm
main_body:
%a1 = add i32 %a, 4
%a2 = add i32 %a, 12
@@ -215,12 +458,30 @@ main_body:
ret void
}
-;CHECK-LABEL: {{^}}buffer_load_x2_offen_merged_or:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: v_lshlrev_b32_e32 v{{[0-9]}}, 4, v0
-;CHECK-NEXT: buffer_load_{{dwordx4|b128}} v[{{[0-9]}}:{{[0-9]}}], v{{[0-9]}}, s[0:3], 0 offen offset:4
-;CHECK: s_waitcnt
define amdgpu_ps void @buffer_load_x2_offen_merged_or(<4 x i32> inreg %rsrc, i32 %inp) {
+; PREGFX10-LABEL: buffer_load_x2_offen_merged_or:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: buffer_load_x2_offen_merged_or:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: buffer_load_x2_offen_merged_or:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; GFX11-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen offset:4
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done
+; GFX11-NEXT: s_endpgm
main_body:
%a = shl i32 %inp, 4
%a1 = add i32 %a, 4
@@ -235,13 +496,38 @@ main_body:
ret void
}
-;CHECK-LABEL: {{^}}buffer_load_x1_offset_merged:
-;CHECK-NEXT: %bb.
-;GFX10-NEXT: s_clause
-;CHECK-NEXT: buffer_load_{{dwordx4|b128}} v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4
-;CHECK-NEXT: buffer_load_{{dwordx2|b64}} v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:28
-;CHECK: s_waitcnt
define amdgpu_ps void @buffer_load_x1_offset_merged(<4 x i32> inreg %rsrc) {
+; PREGFX10-LABEL: buffer_load_x1_offset_merged:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4
+; PREGFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28
+; PREGFX10-NEXT: s_waitcnt vmcnt(1)
+; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: buffer_load_x1_offset_merged:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: s_clause 0x1
+; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4
+; GFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28
+; GFX10-NEXT: s_waitcnt vmcnt(1)
+; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: buffer_load_x1_offset_merged:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0 offset:4
+; GFX11-NEXT: buffer_load_b64 v[4:5], off, s[0:3], 0 offset:28
+; GFX11-NEXT: s_waitcnt vmcnt(1)
+; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: exp mrt0 v4, v5, v0, v0 done
+; GFX11-NEXT: s_endpgm
main_body:
%r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4, i32 0, i32 0)
%r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 8, i32 0, i32 0)
@@ -254,11 +540,27 @@ main_body:
ret void
}
-;CHECK-LABEL: {{^}}buffer_load_x2_offset_merged:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: buffer_load_{{dwordx4|b128}} v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4
-;CHECK: s_waitcnt
define amdgpu_ps void @buffer_load_x2_offset_merged(<4 x i32> inreg %rsrc) {
+; PREGFX10-LABEL: buffer_load_x2_offset_merged:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: buffer_load_x2_offset_merged:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: buffer_load_x2_offset_merged:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0 offset:4
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done
+; GFX11-NEXT: s_endpgm
main_body:
%vr1 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 4, i32 0, i32 0)
%vr2 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 12, i32 0, i32 0)
@@ -270,12 +572,32 @@ main_body:
ret void
}
-;CHECK-LABEL: {{^}}buffer_load_int:
-;CHECK: buffer_load_{{dwordx4|b128}} v[0:3], off, s[0:3], 0
-;CHECK: buffer_load_{{dwordx2|b64}} v[4:5], off, s[0:3], 0 glc
-;CHECK: buffer_load_{{dword|b32}} v6, off, s[0:3], 0 slc
-;CHECK: s_waitcnt
define amdgpu_ps {<4 x float>, <2 x float>, float} @buffer_load_int(<4 x i32> inreg) {
+; PREGFX10-LABEL: buffer_load_int:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
+; PREGFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 glc
+; PREGFX10-NEXT: buffer_load_dword v6, off, s[0:3], 0 slc
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: buffer_load_int:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: s_clause 0x2
+; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0
+; GFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 glc
+; GFX10-NEXT: buffer_load_dword v6, off, s[0:3], 0 slc
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_int:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: s_clause 0x2
+; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0
+; GFX11-NEXT: buffer_load_b64 v[4:5], off, s[0:3], 0 glc
+; GFX11-NEXT: buffer_load_b32 v6, off, s[0:3], 0 slc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x i32> @llvm.amdgcn.raw.buffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 0)
%data_glc = call <2 x i32> @llvm.amdgcn.raw.buffer.load.v2i32(<4 x i32> %0, i32 0, i32 0, i32 1)
@@ -289,13 +611,27 @@ main_body:
ret {<4 x float>, <2 x float>, float} %r2
}
-;CHECK-LABEL: {{^}}raw_buffer_load_ubyte:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: buffer_load_{{ubyte|u8}} v{{[0-9]}}, off, s[0:3], 0
-;CHECK: s_waitcnt vmcnt(0)
-;CHECK-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
-;CHECK-NEXT: ; return to shader part epilog
define amdgpu_ps float @raw_buffer_load_ubyte(<4 x i32> inreg %rsrc) {
+; PREGFX10-LABEL: raw_buffer_load_ubyte:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: raw_buffer_load_ubyte:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: raw_buffer_load_ubyte:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: buffer_load_u8 v0, off, s[0:3], 0
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%tmp = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
%tmp2 = zext i8 %tmp to i32
@@ -303,13 +639,27 @@ main_body:
ret float %val
}
-;CHECK-LABEL: {{^}}raw_buffer_load_i16:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: buffer_load_{{ushort|u16}} v{{[0-9]}}, off, s[0:3], 0
-;CHECK: s_waitcnt vmcnt(0)
-;CHECK-NEXT: v_cvt_f32_u32_e32 v0, v0
-;CHECK-NEXT: ; return to shader part epilog
define amdgpu_ps float @raw_buffer_load_i16(<4 x i32> inreg %rsrc) {
+; PREGFX10-LABEL: raw_buffer_load_i16:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_ushort v0, off, s[0:3], 0
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: v_cvt_f32_u32_e32 v0, v0
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: raw_buffer_load_i16:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: buffer_load_ushort v0, off, s[0:3], 0
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: raw_buffer_load_i16:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: buffer_load_u16 v0, off, s[0:3], 0
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%tmp = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
%tmp2 = zext i16 %tmp to i32
@@ -317,13 +667,27 @@ main_body:
ret float %val
}
-;CHECK-LABEL: {{^}}raw_buffer_load_sbyte:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: buffer_load_{{sbyte|i8}} v{{[0-9]}}, off, s[0:3], 0
-;CHECK: s_waitcnt vmcnt(0)
-;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
-;CHECK-NEXT: ; return to shader part epilog
define amdgpu_ps float @raw_buffer_load_sbyte(<4 x i32> inreg %rsrc) {
+; PREGFX10-LABEL: raw_buffer_load_sbyte:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_sbyte v0, off, s[0:3], 0
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: v_cvt_f32_i32_e32 v0, v0
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: raw_buffer_load_sbyte:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: buffer_load_sbyte v0, off, s[0:3], 0
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: raw_buffer_load_sbyte:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: buffer_load_i8 v0, off, s[0:3], 0
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%tmp = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
%tmp2 = sext i8 %tmp to i32
@@ -331,13 +695,27 @@ main_body:
ret float %val
}
-;CHECK-LABEL: {{^}}raw_buffer_load_sshort:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: buffer_load_{{sshort|i16}} v{{[0-9]}}, off, s[0:3], 0
-;CHECK: s_waitcnt vmcnt(0)
-;CHECK-NEXT: v_cvt_f32_i32_e32 v0, v0
-;CHECK-NEXT: ; return to shader part epilog
define amdgpu_ps float @raw_buffer_load_sshort(<4 x i32> inreg %rsrc) {
+; PREGFX10-LABEL: raw_buffer_load_sshort:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_sshort v0, off, s[0:3], 0
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: v_cvt_f32_i32_e32 v0, v0
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: raw_buffer_load_sshort:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: buffer_load_sshort v0, off, s[0:3], 0
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: raw_buffer_load_sshort:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: buffer_load_i16 v0, off, s[0:3], 0
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%tmp = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
%tmp2 = sext i16 %tmp to i32
@@ -345,73 +723,178 @@ main_body:
ret float %val
}
-;CHECK-LABEL: {{^}}raw_buffer_load_f16:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: buffer_load_{{ushort|u16}} [[VAL:v[0-9]+]], off, s[0:3], 0
-;CHECK: s_waitcnt vmcnt(0)
-;CHECK: ds_{{write|store}}_b16 v0, [[VAL]]
define amdgpu_ps void @raw_buffer_load_f16(<4 x i32> inreg %rsrc, ptr addrspace(3) %ptr) {
+; PREGFX10-LABEL: raw_buffer_load_f16:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_ushort v1, off, s[0:3], 0
+; PREGFX10-NEXT: s_mov_b32 m0, -1
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ds_write_b16 v0, v1
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: raw_buffer_load_f16:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: buffer_load_ushort v1, off, s[0:3], 0
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ds_write_b16 v0, v1
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: raw_buffer_load_f16:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: buffer_load_u16 v1, off, s[0:3], 0
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ds_store_b16 v0, v1
+; GFX11-NEXT: s_endpgm
main_body:
%val = call half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
store half %val, ptr addrspace(3) %ptr
ret void
}
-;CHECK-LABEL: {{^}}raw_buffer_load_v2f16:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: buffer_load_{{dword|b32}} [[VAL:v[0-9]+]], off, s[0:3], 0
-;CHECK: s_waitcnt vmcnt(0)
-;CHECK: ds_{{write|store}}_b32 v0, [[VAL]]
define amdgpu_ps void @raw_buffer_load_v2f16(<4 x i32> inreg %rsrc, ptr addrspace(3) %ptr) {
+; PREGFX10-LABEL: raw_buffer_load_v2f16:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_dword v1, off, s[0:3], 0
+; PREGFX10-NEXT: s_mov_b32 m0, -1
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ds_write_b32 v0, v1
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: raw_buffer_load_v2f16:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], 0
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ds_write_b32 v0, v1
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: raw_buffer_load_v2f16:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: buffer_load_b32 v1, off, s[0:3], 0
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ds_store_b32 v0, v1
+; GFX11-NEXT: s_endpgm
main_body:
%val = call <2 x half> @llvm.amdgcn.raw.buffer.load.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
store <2 x half> %val, ptr addrspace(3) %ptr
ret void
}
-;CHECK-LABEL: {{^}}raw_buffer_load_v4f16:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: buffer_load_{{dwordx2|b64}} [[VAL:v\[[0-9]+:[0-9]+\]]], off, s[0:3], 0
-;CHECK: s_waitcnt vmcnt(0)
-;CHECK: ds_{{write|store}}_b64 v0, [[VAL]]
define amdgpu_ps void @raw_buffer_load_v4f16(<4 x i32> inreg %rsrc, ptr addrspace(3) %ptr) {
+; PREGFX10-LABEL: raw_buffer_load_v4f16:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_dwordx2 v[1:2], off, s[0:3], 0
+; PREGFX10-NEXT: s_mov_b32 m0, -1
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ds_write_b64 v0, v[1:2]
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: raw_buffer_load_v4f16:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: buffer_load_dwordx2 v[1:2], off, s[0:3], 0
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ds_write_b64 v0, v[1:2]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: raw_buffer_load_v4f16:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: buffer_load_b64 v[1:2], off, s[0:3], 0
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ds_store_b64 v0, v[1:2]
+; GFX11-NEXT: s_endpgm
main_body:
%val = call <4 x half> @llvm.amdgcn.raw.buffer.load.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
store <4 x half> %val, ptr addrspace(3) %ptr
ret void
}
-;CHECK-LABEL: {{^}}raw_buffer_load_v2i16:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: buffer_load_{{dword|b32}} [[VAL:v[0-9]+]], off, s[0:3], 0
-;CHECK: s_waitcnt vmcnt(0)
-;CHECK: ds_{{write|store}}_b32 v0, [[VAL]]
define amdgpu_ps void @raw_buffer_load_v2i16(<4 x i32> inreg %rsrc, ptr addrspace(3) %ptr) {
+; PREGFX10-LABEL: raw_buffer_load_v2i16:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_dword v1, off, s[0:3], 0
+; PREGFX10-NEXT: s_mov_b32 m0, -1
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ds_write_b32 v0, v1
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: raw_buffer_load_v2i16:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], 0
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ds_write_b32 v0, v1
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: raw_buffer_load_v2i16:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: buffer_load_b32 v1, off, s[0:3], 0
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ds_store_b32 v0, v1
+; GFX11-NEXT: s_endpgm
main_body:
%val = call <2 x i16> @llvm.amdgcn.raw.buffer.load.v2i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
store <2 x i16> %val, ptr addrspace(3) %ptr
ret void
}
-;CHECK-LABEL: {{^}}raw_buffer_load_v4i16:
-;CHECK-NEXT: %bb.
-;CHECK-NEXT: buffer_load_{{dwordx2|b64}} [[VAL:v\[[0-9]+:[0-9]+\]]], off, s[0:3], 0
-;CHECK: s_waitcnt vmcnt(0)
-;CHECK: ds_{{write|store}}_b64 v0, [[VAL]]
define amdgpu_ps void @raw_buffer_load_v4i16(<4 x i32> inreg %rsrc, ptr addrspace(3) %ptr) {
+; PREGFX10-LABEL: raw_buffer_load_v4i16:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_dwordx2 v[1:2], off, s[0:3], 0
+; PREGFX10-NEXT: s_mov_b32 m0, -1
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ds_write_b64 v0, v[1:2]
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: raw_buffer_load_v4i16:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: buffer_load_dwordx2 v[1:2], off, s[0:3], 0
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ds_write_b64 v0, v[1:2]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: raw_buffer_load_v4i16:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: buffer_load_b64 v[1:2], off, s[0:3], 0
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ds_store_b64 v0, v[1:2]
+; GFX11-NEXT: s_endpgm
main_body:
%val = call <4 x i16> @llvm.amdgcn.raw.buffer.load.v4i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0)
store <4 x i16> %val, ptr addrspace(3) %ptr
ret void
}
-;CHECK-LABEL: {{^}}raw_buffer_load_x1_offset_merged:
-;CHECK-NEXT: %bb.
-;GFX10-NEXT: s_clause
-;CHECK-NEXT: buffer_load_{{dwordx4|b128}} v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:4
-;CHECK-NEXT: buffer_load_{{dwordx2|b64}} v[{{[0-9]}}:{{[0-9]}}], off, s[0:3], 0 offset:28
-;CHECK: s_waitcnt
define amdgpu_ps void @raw_buffer_load_x1_offset_merged(<4 x i32> inreg %rsrc) {
+; PREGFX10-LABEL: raw_buffer_load_x1_offset_merged:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4
+; PREGFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28
+; PREGFX10-NEXT: s_waitcnt vmcnt(1)
+; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: raw_buffer_load_x1_offset_merged:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: s_clause 0x1
+; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4
+; GFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28
+; GFX10-NEXT: s_waitcnt vmcnt(1)
+; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: raw_buffer_load_x1_offset_merged:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0 offset:4
+; GFX11-NEXT: buffer_load_b64 v[4:5], off, s[0:3], 0 offset:28
+; GFX11-NEXT: s_waitcnt vmcnt(1)
+; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: exp mrt0 v4, v5, v0, v0 done
+; GFX11-NEXT: s_endpgm
main_body:
%r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4, i32 0, i32 0)
%r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 8, i32 0, i32 0)
@@ -424,17 +907,50 @@ main_body:
ret void
}
-;CHECK-LABEL: {{^}}raw_buffer_load_x1_offset_swizzled_not_merged:
-;CHECK-NEXT: %bb.
-;GFX10-NEXT: s_clause
-;CHECK-NEXT: buffer_load_{{dword|b32}} v{{[0-9]}}, off, s[0:3], 0 offset:4
-;CHECK-NEXT: buffer_load_{{dword|b32}} v{{[0-9]}}, off, s[0:3], 0 offset:8
-;CHECK-NEXT: buffer_load_{{dword|b32}} v{{[0-9]}}, off, s[0:3], 0 offset:12
-;CHECK-NEXT: buffer_load_{{dword|b32}} v{{[0-9]}}, off, s[0:3], 0 offset:16
-;CHECK-NEXT: buffer_load_{{dword|b32}} v{{[0-9]}}, off, s[0:3], 0 offset:28
-;CHECK-NEXT: buffer_load_{{dword|b32}} v{{[0-9]}}, off, s[0:3], 0 offset:32
-;CHECK: s_waitcnt
define amdgpu_ps void @raw_buffer_load_x1_offset_swizzled_not_merged(<4 x i32> inreg %rsrc) {
+; PREGFX10-LABEL: raw_buffer_load_x1_offset_swizzled_not_merged:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:4
+; PREGFX10-NEXT: buffer_load_dword v1, off, s[0:3], 0 offset:8
+; PREGFX10-NEXT: buffer_load_dword v2, off, s[0:3], 0 offset:12
+; PREGFX10-NEXT: buffer_load_dword v3, off, s[0:3], 0 offset:16
+; PREGFX10-NEXT: buffer_load_dword v4, off, s[0:3], 0 offset:28
+; PREGFX10-NEXT: buffer_load_dword v5, off, s[0:3], 0 offset:32
+; PREGFX10-NEXT: s_waitcnt vmcnt(2)
+; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: raw_buffer_load_x1_offset_swizzled_not_merged:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: s_clause 0x5
+; GFX10-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:4
+; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], 0 offset:8
+; GFX10-NEXT: buffer_load_dword v2, off, s[0:3], 0 offset:12
+; GFX10-NEXT: buffer_load_dword v3, off, s[0:3], 0 offset:16
+; GFX10-NEXT: buffer_load_dword v4, off, s[0:3], 0 offset:28
+; GFX10-NEXT: buffer_load_dword v5, off, s[0:3], 0 offset:32
+; GFX10-NEXT: s_waitcnt vmcnt(2)
+; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: raw_buffer_load_x1_offset_swizzled_not_merged:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: s_clause 0x5
+; GFX11-NEXT: buffer_load_b32 v0, off, s[0:3], 0 offset:4
+; GFX11-NEXT: buffer_load_b32 v1, off, s[0:3], 0 offset:8
+; GFX11-NEXT: buffer_load_b32 v2, off, s[0:3], 0 offset:12
+; GFX11-NEXT: buffer_load_b32 v3, off, s[0:3], 0 offset:16
+; GFX11-NEXT: buffer_load_b32 v4, off, s[0:3], 0 offset:28
+; GFX11-NEXT: buffer_load_b32 v5, off, s[0:3], 0 offset:32
+; GFX11-NEXT: s_waitcnt vmcnt(2)
+; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: exp mrt0 v4, v5, v0, v0 done
+; GFX11-NEXT: s_endpgm
main_body:
%r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4, i32 0, i32 8)
%r2 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 8, i32 0, i32 8)
@@ -461,5 +977,4 @@ declare <4 x i16> @llvm.amdgcn.raw.buffer.load.v4i16(<4 x i32>, i32, i32, i32) #
declare half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32>, i32, i32, i32) #0
declare <2 x half> @llvm.amdgcn.raw.buffer.load.v2f16(<4 x i32>, i32, i32, i32) #0
declare <4 x half> @llvm.amdgcn.raw.buffer.load.v4f16(<4 x i32>, i32, i32, i32) #0
-
attributes #0 = { nounwind readonly }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll
index c9eec415c6a89..43dd2f43b03b0 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll
@@ -1,56 +1,135 @@
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefixes=GCN,UNPACKED,PREGFX10,PREGFX10-UNPACKED %s
-; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GCN,PACKED,PREGFX10,PREGFX10-PACKED %s
-; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GCN,PACKED,PREGFX10,PREGFX10-PACKED %s
-; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GCN,PACKED,GFX10,GFX10-PACKED %s
-; RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GCN,PACKED,GFX10,GFX10-PACKED %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefixes=PREGFX10-UNPACKED %s
+; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PREGFX10-PACKED %s
+; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PREGFX10-PACKED %s
+; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX10-PACKED %s
+; RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED %s
-; GCN-LABEL: {{^}}tbuffer_load_d16_x:
-; PREGFX10: tbuffer_load_format_d16_x v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
-; GFX10: tbuffer_load_{{format_d16|d16_format}}_x v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT]
define amdgpu_ps half @tbuffer_load_d16_x(<4 x i32> inreg %rsrc) {
+; PREGFX10-UNPACKED-LABEL: tbuffer_load_d16_x:
+; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
+; PREGFX10-UNPACKED-NEXT: tbuffer_load_format_d16_x v0, off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; encoding: [0x00,0x00,0xb4,0xe8,0x00,0x00,0x00,0x80]
+; PREGFX10-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
+; PREGFX10-UNPACKED-NEXT: ; return to shader part epilog
+;
+; PREGFX10-PACKED-LABEL: tbuffer_load_d16_x:
+; PREGFX10-PACKED: ; %bb.0: ; %main_body
+; PREGFX10-PACKED-NEXT: tbuffer_load_format_d16_x v0, off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
+; PREGFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-PACKED-NEXT: ; return to shader part epilog
+;
+; GFX10-PACKED-LABEL: tbuffer_load_d16_x:
+; GFX10-PACKED: ; %bb.0: ; %main_body
+; GFX10-PACKED-NEXT: tbuffer_load_format_d16_x v0, off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
+; GFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
+; GFX10-PACKED-NEXT: ; return to shader part epilog
+;
+; GFX11-PACKED-LABEL: tbuffer_load_d16_x:
+; GFX11-PACKED: ; %bb.0: ; %main_body
+; GFX11-PACKED-NEXT: tbuffer_load_d16_format_x v0, off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
+; GFX11-PACKED-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PACKED-NEXT: ; return to shader part epilog
main_body:
%data = call half @llvm.amdgcn.raw.tbuffer.load.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 22, i32 0)
ret half %data
}
-; GCN-LABEL: {{^}}tbuffer_load_d16_xy:
-; PREGFX10-UNPACKED: tbuffer_load_format_d16_xy v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
-; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
-
-; PREGFX10-PACKED: tbuffer_load_format_d16_xy v[[FULL:[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
-; GFX10-PACKED: tbuffer_load_{{format_d16|d16_format}}_xy v[[FULL:[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT]
-; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[FULL]]
define amdgpu_ps half @tbuffer_load_d16_xy(<4 x i32> inreg %rsrc) {
+; PREGFX10-UNPACKED-LABEL: tbuffer_load_d16_xy:
+; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
+; PREGFX10-UNPACKED-NEXT: tbuffer_load_format_d16_xy v[0:1], off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; encoding: [0x00,0x80,0xb4,0xe8,0x00,0x00,0x00,0x80]
+; PREGFX10-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, v1 ; encoding: [0x01,0x03,0x00,0x7e]
+; PREGFX10-UNPACKED-NEXT: ; return to shader part epilog
+;
+; PREGFX10-PACKED-LABEL: tbuffer_load_d16_xy:
+; PREGFX10-PACKED: ; %bb.0: ; %main_body
+; PREGFX10-PACKED-NEXT: tbuffer_load_format_d16_xy v0, off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
+; PREGFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; PREGFX10-PACKED-NEXT: ; return to shader part epilog
+;
+; GFX10-PACKED-LABEL: tbuffer_load_d16_xy:
+; GFX10-PACKED: ; %bb.0: ; %main_body
+; GFX10-PACKED-NEXT: tbuffer_load_format_d16_xy v0, off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
+; GFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
+; GFX10-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX10-PACKED-NEXT: ; return to shader part epilog
+;
+; GFX11-PACKED-LABEL: tbuffer_load_d16_xy:
+; GFX11-PACKED: ; %bb.0: ; %main_body
+; GFX11-PACKED-NEXT: tbuffer_load_d16_format_xy v0, off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
+; GFX11-PACKED-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-PACKED-NEXT: ; return to shader part epilog
main_body:
%data = call <2 x half> @llvm.amdgcn.raw.tbuffer.load.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i32 22, i32 0)
%elt = extractelement <2 x half> %data, i32 1
ret half %elt
}
-; GCN-LABEL: {{^}}tbuffer_load_d16_xyz:
-; PREGFX10-UNPACKED: tbuffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
-; GFX10-UNPACKED: tbuffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT]
-; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
-
-; PREGFX10-PACKED: tbuffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
-; GFX10-PACKED: tbuffer_load_{{format_d16|d16_format}}_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT]
-; PACKED: v_mov_b{{16|32}}_e32 v{{[0-9]+(\.(l|h))?}}, v[[HI]]{{(\.(l,h))?}}
define amdgpu_ps half @tbuffer_load_d16_xyz(<4 x i32> inreg %rsrc) {
+; PREGFX10-UNPACKED-LABEL: tbuffer_load_d16_xyz:
+; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
+; PREGFX10-UNPACKED-NEXT: tbuffer_load_format_d16_xyz v[0:2], off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; encoding: [0x00,0x00,0xb5,0xe8,0x00,0x00,0x00,0x80]
+; PREGFX10-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, v2 ; encoding: [0x02,0x03,0x00,0x7e]
+; PREGFX10-UNPACKED-NEXT: ; return to shader part epilog
+;
+; PREGFX10-PACKED-LABEL: tbuffer_load_d16_xyz:
+; PREGFX10-PACKED: ; %bb.0: ; %main_body
+; PREGFX10-PACKED-NEXT: tbuffer_load_format_d16_xyz v[0:1], off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
+; PREGFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v0, v1
+; PREGFX10-PACKED-NEXT: ; return to shader part epilog
+;
+; GFX10-PACKED-LABEL: tbuffer_load_d16_xyz:
+; GFX10-PACKED: ; %bb.0: ; %main_body
+; GFX10-PACKED-NEXT: tbuffer_load_format_d16_xyz v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
+; GFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
+; GFX10-PACKED-NEXT: v_mov_b32_e32 v0, v1
+; GFX10-PACKED-NEXT: ; return to shader part epilog
+;
+; GFX11-PACKED-LABEL: tbuffer_load_d16_xyz:
+; GFX11-PACKED: ; %bb.0: ; %main_body
+; GFX11-PACKED-NEXT: tbuffer_load_d16_format_xyz v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
+; GFX11-PACKED-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, v1
+; GFX11-PACKED-NEXT: ; return to shader part epilog
main_body:
%data = call <3 x half> @llvm.amdgcn.raw.tbuffer.load.v3f16(<4 x i32> %rsrc, i32 0, i32 0, i32 22, i32 0)
%elt = extractelement <3 x half> %data, i32 2
ret half %elt
}
-; GCN-LABEL: {{^}}tbuffer_load_d16_xyzw:
-; PREGFX10-UNPACKED: tbuffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
-; GFX10-UNPACKED: tbuffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT]
-; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
-
-; PREGFX10-PACKED: tbuffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
-; GFX10-PACKED: tbuffer_load_{{format_d16|d16_format}}_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT]
-; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]]
define amdgpu_ps half @tbuffer_load_d16_xyzw(<4 x i32> inreg %rsrc) {
+; PREGFX10-UNPACKED-LABEL: tbuffer_load_d16_xyzw:
+; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
+; PREGFX10-UNPACKED-NEXT: tbuffer_load_format_d16_xyzw v[0:3], off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] ; encoding: [0x00,0x80,0xb5,0xe8,0x00,0x00,0x00,0x80]
+; PREGFX10-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, v3 ; encoding: [0x03,0x03,0x00,0x7e]
+; PREGFX10-UNPACKED-NEXT: ; return to shader part epilog
+;
+; PREGFX10-PACKED-LABEL: tbuffer_load_d16_xyzw:
+; PREGFX10-PACKED: ; %bb.0: ; %main_body
+; PREGFX10-PACKED-NEXT: tbuffer_load_format_d16_xyzw v[0:1], off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM]
+; PREGFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; PREGFX10-PACKED-NEXT: ; return to shader part epilog
+;
+; GFX10-PACKED-LABEL: tbuffer_load_d16_xyzw:
+; GFX10-PACKED: ; %bb.0: ; %main_body
+; GFX10-PACKED-NEXT: tbuffer_load_format_d16_xyzw v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
+; GFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
+; GFX10-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX10-PACKED-NEXT: ; return to shader part epilog
+;
+; GFX11-PACKED-LABEL: tbuffer_load_d16_xyzw:
+; GFX11-PACKED: ; %bb.0: ; %main_body
+; GFX11-PACKED-NEXT: tbuffer_load_d16_format_xyzw v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT]
+; GFX11-PACKED-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX11-PACKED-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x half> @llvm.amdgcn.raw.tbuffer.load.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 22, i32 0)
%elt = extractelement <4 x half> %data, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll
index ff1001dd980f2..c1d08a1fc97cf 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll
@@ -1,23 +1,38 @@
-;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=GCN -check-prefix=PREGFX10 %s
-;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=GCN -check-prefix=PREGFX10 %s
-;RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GCN -check-prefix=GFX10 %s
-;RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck -check-prefix=GCN -check-prefix=GFX11 %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=PREGFX10 %s
+;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=PREGFX10 %s
+;RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GFX10 %s
+;RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck -check-prefix=GFX11 %s
-; GCN-LABEL: {{^}}tbuffer_load:
-; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT]
-; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] glc
-; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] slc
-; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] glc
-; GFX10-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 format:78
-; GFX10-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_FMT_32_32_SINT] glc
-; GFX10-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_FMT_32_FLOAT] slc
-; GFX10-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_FMT_32_FLOAT] glc dlc
-; GFX11-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 format:78
-; GFX11-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_FMT_32_32_32_32_FLOAT] glc
-; GFX11-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_FMT_32_FLOAT] slc
-; GFX11-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_FMT_32_FLOAT] glc dlc
-; GCN: s_waitcnt
define amdgpu_vs {<4 x float>, <4 x float>, <4 x float>, <4 x float>} @tbuffer_load(<4 x i32> inreg) {
+; PREGFX10-LABEL: tbuffer_load:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], off, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT]
+; PREGFX10-NEXT: tbuffer_load_format_xyzw v[4:7], off, s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] glc
+; PREGFX10-NEXT: tbuffer_load_format_xyzw v[8:11], off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] slc
+; PREGFX10-NEXT: tbuffer_load_format_xyzw v[12:15], off, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] glc
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: tbuffer_load:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: s_clause 0x3
+; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], off, s[0:3], 0 format:78
+; GFX10-NEXT: tbuffer_load_format_xyzw v[4:7], off, s[0:3], 0 format:[BUF_FMT_32_32_SINT] glc
+; GFX10-NEXT: tbuffer_load_format_xyzw v[8:11], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT] slc
+; GFX10-NEXT: tbuffer_load_format_xyzw v[12:15], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT] glc dlc
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: tbuffer_load:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: s_clause 0x3
+; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], off, s[0:3], 0 format:78
+; GFX11-NEXT: tbuffer_load_format_xyzw v[4:7], off, s[0:3], 0 format:[BUF_FMT_32_32_32_32_FLOAT] glc
+; GFX11-NEXT: tbuffer_load_format_xyzw v[8:11], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT] slc
+; GFX11-NEXT: tbuffer_load_format_xyzw v[12:15], off, s[0:3], 0 format:[BUF_FMT_32_FLOAT] glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%vdata = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 78, i32 0)
%vdata_glc = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 63, i32 1)
@@ -33,29 +48,56 @@ main_body:
ret {<4 x float>, <4 x float>, <4 x float>, <4 x float>} %r3
}
-; GCN-LABEL: {{^}}tbuffer_load_immoffs:
-; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] offset:42
-; GFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 format:78 offset:42
-; GFX11: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 format:78 offset:42
define amdgpu_vs <4 x float> @tbuffer_load_immoffs(<4 x i32> inreg) {
+; PREGFX10-LABEL: tbuffer_load_immoffs:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], off, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] offset:42
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: tbuffer_load_immoffs:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], off, s[0:3], 0 format:78 offset:42
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: tbuffer_load_immoffs:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], off, s[0:3], 0 format:78 offset:42
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%vdata = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 42, i32 0, i32 78, i32 0)
%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
ret <4 x float> %vdata.f
}
-; GCN-LABEL: {{^}}tbuffer_load_immoffs_large
-; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 61 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_USCALED] offset:4095
-; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_SSCALED] offset:73
-; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] offset:1
-; GFX10-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 61 format:[BUF_FMT_10_10_10_2_SSCALED] offset:4095
-; GFX10-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} format:[BUF_FMT_32_32_UINT] offset:73
-; GFX10-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} format:[BUF_FMT_32_32_32_32_FLOAT] offset:1
-; GFX11-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 61 format:[BUF_FMT_8_8_8_8_SINT] offset:4095
-; GFX11-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} format:[BUF_FMT_32_32_32_32_SINT] offset:73
-; GFX11-DAG: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} format:77 offset:1
-; GCN: s_waitcnt
define amdgpu_vs {<4 x float>, <4 x float>, <4 x float>} @tbuffer_load_immoffs_large(<4 x i32> inreg, i32 inreg %soffs) {
+; PREGFX10-LABEL: tbuffer_load_immoffs_large:
+; PREGFX10: ; %bb.0:
+; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], off, s[0:3], 61 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_USCALED] offset:4095
+; PREGFX10-NEXT: tbuffer_load_format_xyzw v[4:7], off, s[0:3], s4 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_SSCALED] offset:73
+; PREGFX10-NEXT: tbuffer_load_format_xyzw v[8:11], off, s[0:3], s4 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] offset:1
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: tbuffer_load_immoffs_large:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_clause 0x2
+; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], off, s[0:3], 61 format:[BUF_FMT_10_10_10_2_SSCALED] offset:4095
+; GFX10-NEXT: tbuffer_load_format_xyzw v[4:7], off, s[0:3], s4 format:[BUF_FMT_32_32_UINT] offset:73
+; GFX10-NEXT: tbuffer_load_format_xyzw v[8:11], off, s[0:3], s4 format:[BUF_FMT_32_32_32_32_FLOAT] offset:1
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: tbuffer_load_immoffs_large:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x2
+; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], off, s[0:3], 61 format:[BUF_FMT_8_8_8_8_SINT] offset:4095
+; GFX11-NEXT: tbuffer_load_format_xyzw v[4:7], off, s[0:3], s4 format:[BUF_FMT_32_32_32_32_SINT] offset:73
+; GFX11-NEXT: tbuffer_load_format_xyzw v[8:11], off, s[0:3], s4 format:77 offset:1
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
%vdata = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 4095, i32 61, i32 47, i32 0)
%vdata_glc = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 73, i32 %soffs, i32 62, i32 0)
%vdata_slc = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 1, i32 %soffs, i32 77, i32 0)
@@ -68,21 +110,48 @@ define amdgpu_vs {<4 x float>, <4 x float>, <4 x float>} @tbuffer_load_immoffs_l
ret {<4 x float>, <4 x float>, <4 x float>} %r2
}
-; GCN-LABEL: {{^}}tbuffer_load_ofs:
-; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] offen
-; GFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:78 offen
-; GFX11: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:78 offen
define amdgpu_vs <4 x float> @tbuffer_load_ofs(<4 x i32> inreg, i32 %voffs) {
+; PREGFX10-LABEL: tbuffer_load_ofs:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] offen
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: tbuffer_load_ofs:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:78 offen
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: tbuffer_load_ofs:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:78 offen
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%vdata = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 %voffs, i32 0, i32 78, i32 0)
%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
ret <4 x float> %vdata.f
}
-; GCN-LABEL: {{^}}tbuffer_load_ofs_imm:
-; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] offen offset:52
-; GFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:78 offen offset:52
define amdgpu_vs <4 x float> @tbuffer_load_ofs_imm(<4 x i32> inreg, i32 %voffs) {
+; PREGFX10-LABEL: tbuffer_load_ofs_imm:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] offen offset:52
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: tbuffer_load_ofs_imm:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:78 offen offset:52
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: tbuffer_load_ofs_imm:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:78 offen offset:52
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%ofs = add i32 %voffs, 52
%vdata = call <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32> %0, i32 %ofs, i32 0, i32 78, i32 0)
@@ -90,21 +159,47 @@ main_body:
ret <4 x float> %vdata.f
}
-; GCN-LABEL: {{^}}buffer_load_xy:
-; PREGFX10: tbuffer_load_format_xy {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT]
-; GFX10: tbuffer_load_format_xy {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_FMT_32_32_32_32_FLOAT]
-; GFX11: tbuffer_load_format_xy {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 format:77
define amdgpu_vs <2 x float> @buffer_load_xy(<4 x i32> inreg %rsrc) {
+; PREGFX10-LABEL: buffer_load_xy:
+; PREGFX10: ; %bb.0:
+; PREGFX10-NEXT: tbuffer_load_format_xy v[0:1], off, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT]
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: buffer_load_xy:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: tbuffer_load_format_xy v[0:1], off, s[0:3], 0 format:[BUF_FMT_32_32_32_32_FLOAT]
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_xy:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: tbuffer_load_format_xy v[0:1], off, s[0:3], 0 format:77
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
%vdata = call <2 x i32> @llvm.amdgcn.raw.tbuffer.load.v2i32(<4 x i32> %rsrc, i32 0, i32 0, i32 77, i32 0)
%vdata.f = bitcast <2 x i32> %vdata to <2 x float>
ret <2 x float> %vdata.f
}
-; GCN-LABEL: {{^}}buffer_load_x:
-; PREGFX10: tbuffer_load_format_x {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT]
-; GFX10: tbuffer_load_format_x {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_FMT_32_32_32_32_FLOAT]
-; GFX11: tbuffer_load_format_x {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 format:77
define amdgpu_vs float @buffer_load_x(<4 x i32> inreg %rsrc) {
+; PREGFX10-LABEL: buffer_load_x:
+; PREGFX10: ; %bb.0:
+; PREGFX10-NEXT: tbuffer_load_format_x v0, off, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT]
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: buffer_load_x:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: tbuffer_load_format_x v0, off, s[0:3], 0 format:[BUF_FMT_32_32_32_32_FLOAT]
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_x:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: tbuffer_load_format_x v0, off, s[0:3], 0 format:77
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
%vdata = call i32 @llvm.amdgcn.raw.tbuffer.load.i32(<4 x i32> %rsrc, i32 0, i32 0, i32 77, i32 0)
%vdata.f = bitcast i32 %vdata to float
ret float %vdata.f
@@ -114,4 +209,3 @@ declare i32 @llvm.amdgcn.raw.tbuffer.load.i32(<4 x i32>, i32, i32, i32, i32)
declare <2 x i32> @llvm.amdgcn.raw.tbuffer.load.v2i32(<4 x i32>, i32, i32, i32, i32)
declare <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32>, i32, i32, i32, i32)
declare <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32>, i32, i32, i32, i32)
-
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
index f3490f4511157..7b6c43f9ed013 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
@@ -1,79 +1,206 @@
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=GCN,UNPACKED,PREGFX10,PREGFX10-UNPACKED %s
-; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -check-prefixes=GCN,PACKED,PREGFX10,PREGFX10-PACKED %s
-; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefixes=GCN,PACKED,PREGFX10,PREGFX10-PACKED %s
-; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GCN,PACKED,GFX10,GFX10-PACKED %s
-; RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GCN,PACKED,GFX10,GFX10-PACKED %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=PREGFX10-UNPACKED %s
+; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -check-prefixes=PREGFX10-PACKED %s
+; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -check-prefixes=PREGFX10-PACKED %s
+; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GFX10-PACKED %s
+; RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck -check-prefixes=GFX11-PACKED %s
-; GCN-LABEL: {{^}}tbuffer_store_d16_x:
-; GCN-DAG: s_load_{{dwordx4|b128}}
-; GCN-DAG: s_load_{{dword|b32}} s[[S_LO:[0-9]+]]
-; GCN-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[S_LO]]
-; PREGFX10: tbuffer_store_format_d16_x v[[V_LO]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED]
-; GFX10: tbuffer_store_{{format_d16|d16_format}}_x v[[V_LO]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_{{.*}}]
define amdgpu_kernel void @tbuffer_store_d16_x(<4 x i32> %rsrc, half %data) {
+; PREGFX10-UNPACKED-LABEL: tbuffer_store_d16_x:
+; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
+; PREGFX10-UNPACKED-NEXT: s_load_dword s4, s[0:1], 0x34
+; PREGFX10-UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; PREGFX10-UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, s4
+; PREGFX10-UNPACKED-NEXT: tbuffer_store_format_d16_x v0, off, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED]
+; PREGFX10-UNPACKED-NEXT: s_endpgm
+;
+; PREGFX10-PACKED-LABEL: tbuffer_store_d16_x:
+; PREGFX10-PACKED: ; %bb.0: ; %main_body
+; PREGFX10-PACKED-NEXT: s_load_dword s2, s[0:1], 0x34
+; PREGFX10-PACKED-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; PREGFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v0, s2
+; PREGFX10-PACKED-NEXT: tbuffer_store_format_d16_x v0, off, s[4:7], 0 format:[BUF_NUM_FORMAT_USCALED]
+; PREGFX10-PACKED-NEXT: s_endpgm
+;
+; GFX10-PACKED-LABEL: tbuffer_store_d16_x:
+; GFX10-PACKED: ; %bb.0: ; %main_body
+; GFX10-PACKED-NEXT: s_clause 0x1
+; GFX10-PACKED-NEXT: s_load_dword s2, s[0:1], 0x34
+; GFX10-PACKED-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-PACKED-NEXT: v_mov_b32_e32 v0, s2
+; GFX10-PACKED-NEXT: tbuffer_store_format_d16_x v0, off, s[4:7], 0 format:[BUF_FMT_10_11_11_SSCALED]
+; GFX10-PACKED-NEXT: s_endpgm
+;
+; GFX11-PACKED-LABEL: tbuffer_store_d16_x:
+; GFX11-PACKED: ; %bb.0: ; %main_body
+; GFX11-PACKED-NEXT: s_clause 0x1
+; GFX11-PACKED-NEXT: s_load_b32 s4, s[0:1], 0x34
+; GFX11-PACKED-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
+; GFX11-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, s4
+; GFX11-PACKED-NEXT: tbuffer_store_d16_format_x v0, off, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM]
+; GFX11-PACKED-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-PACKED-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.tbuffer.store.f16(half %data, <4 x i32> %rsrc, i32 0, i32 0, i32 33, i32 0)
ret void
}
-; GCN-LABEL: {{^}}tbuffer_store_d16_xy:
-; GCN: s_load_{{dword|b32}} [[S_DATA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}},
-; UNPACKED-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[S_DATA]], 16
-; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], [[S_DATA]], 0xffff{{$}}
-; UNPACKED-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[MASKED]]
-; UNPACKED-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], [[SHR]]
-; PREGFX10-UNPACKED: tbuffer_store_format_d16_xy v[[[V_LO]]:[[V_HI]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED]
-
-; PREGFX10-PACKED: tbuffer_store_format_d16_xy v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED]
-; GFX10-PACKED: tbuffer_store_{{format_d16|d16_format}}_xy v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_{{.*}}]
define amdgpu_kernel void @tbuffer_store_d16_xy(<4 x i32> %rsrc, <2 x half> %data) {
+; PREGFX10-UNPACKED-LABEL: tbuffer_store_d16_xy:
+; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
+; PREGFX10-UNPACKED-NEXT: s_load_dword s4, s[0:1], 0x34
+; PREGFX10-UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; PREGFX10-UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
+; PREGFX10-UNPACKED-NEXT: s_lshr_b32 s5, s4, 16
+; PREGFX10-UNPACKED-NEXT: s_and_b32 s4, s4, 0xffff
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, s4
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v1, s5
+; PREGFX10-UNPACKED-NEXT: tbuffer_store_format_d16_xy v[0:1], off, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED]
+; PREGFX10-UNPACKED-NEXT: s_endpgm
+;
+; PREGFX10-PACKED-LABEL: tbuffer_store_d16_xy:
+; PREGFX10-PACKED: ; %bb.0: ; %main_body
+; PREGFX10-PACKED-NEXT: s_load_dword s2, s[0:1], 0x34
+; PREGFX10-PACKED-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; PREGFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v0, s2
+; PREGFX10-PACKED-NEXT: tbuffer_store_format_d16_xy v0, off, s[4:7], 0 format:[BUF_NUM_FORMAT_USCALED]
+; PREGFX10-PACKED-NEXT: s_endpgm
+;
+; GFX10-PACKED-LABEL: tbuffer_store_d16_xy:
+; GFX10-PACKED: ; %bb.0: ; %main_body
+; GFX10-PACKED-NEXT: s_clause 0x1
+; GFX10-PACKED-NEXT: s_load_dword s2, s[0:1], 0x34
+; GFX10-PACKED-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-PACKED-NEXT: v_mov_b32_e32 v0, s2
+; GFX10-PACKED-NEXT: tbuffer_store_format_d16_xy v0, off, s[4:7], 0 format:[BUF_FMT_10_11_11_SSCALED]
+; GFX10-PACKED-NEXT: s_endpgm
+;
+; GFX11-PACKED-LABEL: tbuffer_store_d16_xy:
+; GFX11-PACKED: ; %bb.0: ; %main_body
+; GFX11-PACKED-NEXT: s_clause 0x1
+; GFX11-PACKED-NEXT: s_load_b32 s4, s[0:1], 0x34
+; GFX11-PACKED-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
+; GFX11-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, s4
+; GFX11-PACKED-NEXT: tbuffer_store_d16_format_xy v0, off, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM]
+; GFX11-PACKED-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-PACKED-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.tbuffer.store.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 0, i32 0, i32 33, i32 0)
ret void
}
-; GCN-LABEL: {{^}}tbuffer_store_d16_xyz:
-; GCN-DAG: s_load_{{dwordx2|b64}} s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}},
-
-; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
-; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], 0xffff{{$}}
-; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
-
-; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
-; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED1]]
-; PREGFX10-UNPACKED: tbuffer_store_format_d16_xyz v[[[LO]]:[[HI]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED]
-
-
-; PACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
-; PACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
-; PACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED0]]
-; PREGFX10-PACKED: tbuffer_store_format_d16_xyz v[[[LO]]:[[HI]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED]
-; GFX10-PACKED: tbuffer_store_{{format_d16|d16_format}}_xyz v[[[LO]]:[[HI]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_{{.*}}]
define amdgpu_kernel void @tbuffer_store_d16_xyz(<4 x i32> %rsrc, <4 x half> %data) {
+; PREGFX10-UNPACKED-LABEL: tbuffer_store_d16_xyz:
+; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
+; PREGFX10-UNPACKED-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
+; PREGFX10-UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; PREGFX10-UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
+; PREGFX10-UNPACKED-NEXT: s_and_b32 s5, s5, 0xffff
+; PREGFX10-UNPACKED-NEXT: s_lshr_b32 s6, s4, 16
+; PREGFX10-UNPACKED-NEXT: s_and_b32 s4, s4, 0xffff
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, s4
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v1, s6
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v2, s5
+; PREGFX10-UNPACKED-NEXT: tbuffer_store_format_d16_xyz v[0:2], off, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED]
+; PREGFX10-UNPACKED-NEXT: s_endpgm
+;
+; PREGFX10-PACKED-LABEL: tbuffer_store_d16_xyz:
+; PREGFX10-PACKED: ; %bb.0: ; %main_body
+; PREGFX10-PACKED-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
+; PREGFX10-PACKED-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; PREGFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; PREGFX10-PACKED-NEXT: s_and_b32 s0, s3, 0xffff
+; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v0, s2
+; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v1, s0
+; PREGFX10-PACKED-NEXT: tbuffer_store_format_d16_xyz v[0:1], off, s[4:7], 0 format:[BUF_NUM_FORMAT_USCALED]
+; PREGFX10-PACKED-NEXT: s_endpgm
+;
+; GFX10-PACKED-LABEL: tbuffer_store_d16_xyz:
+; GFX10-PACKED: ; %bb.0: ; %main_body
+; GFX10-PACKED-NEXT: s_clause 0x1
+; GFX10-PACKED-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
+; GFX10-PACKED-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-PACKED-NEXT: s_and_b32 s0, s3, 0xffff
+; GFX10-PACKED-NEXT: v_mov_b32_e32 v0, s2
+; GFX10-PACKED-NEXT: v_mov_b32_e32 v1, s0
+; GFX10-PACKED-NEXT: tbuffer_store_format_d16_xyz v[0:1], off, s[4:7], 0 format:[BUF_FMT_10_11_11_SSCALED]
+; GFX10-PACKED-NEXT: s_endpgm
+;
+; GFX11-PACKED-LABEL: tbuffer_store_d16_xyz:
+; GFX11-PACKED: ; %bb.0: ; %main_body
+; GFX11-PACKED-NEXT: s_clause 0x1
+; GFX11-PACKED-NEXT: s_load_b64 s[4:5], s[0:1], 0x34
+; GFX11-PACKED-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
+; GFX11-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-PACKED-NEXT: s_and_b32 s5, s5, 0xffff
+; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, s4
+; GFX11-PACKED-NEXT: v_mov_b32_e32 v1, s5
+; GFX11-PACKED-NEXT: tbuffer_store_d16_format_xyz v[0:1], off, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM]
+; GFX11-PACKED-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-PACKED-NEXT: s_endpgm
main_body:
%data_subvec = shufflevector <4 x half> %data, <4 x half> undef, <3 x i32> <i32 0, i32 1, i32 2>
call void @llvm.amdgcn.raw.tbuffer.store.v3f16(<3 x half> %data_subvec, <4 x i32> %rsrc, i32 0, i32 0, i32 33, i32 0)
ret void
}
-; GCN-LABEL: {{^}}tbuffer_store_d16_xyzw:
-; GCN-DAG: s_load_{{dwordx2|b64}} s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}},
-
-; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
-; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], 0xffff{{$}}
-; UNPACKED-DAG: s_lshr_b32 [[SHR1:s[0-9]+]], s[[S_DATA_1]], 16
-; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
-
-; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
-; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHR1]]
-; PREGFX10-UNPACKED: tbuffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED]
-
-
-; PACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
-; PACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], s[[S_DATA_1]]
-; PREGFX10-PACKED: tbuffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED]
-; GFX10-PACKED: tbuffer_store_{{format_d16|d16_format}}_xyzw v[[[LO]]:[[HI]]], off, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_{{.*}}]
define amdgpu_kernel void @tbuffer_store_d16_xyzw(<4 x i32> %rsrc, <4 x half> %data) {
+; PREGFX10-UNPACKED-LABEL: tbuffer_store_d16_xyzw:
+; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
+; PREGFX10-UNPACKED-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
+; PREGFX10-UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; PREGFX10-UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
+; PREGFX10-UNPACKED-NEXT: s_lshr_b32 s6, s5, 16
+; PREGFX10-UNPACKED-NEXT: s_and_b32 s5, s5, 0xffff
+; PREGFX10-UNPACKED-NEXT: s_lshr_b32 s7, s4, 16
+; PREGFX10-UNPACKED-NEXT: s_and_b32 s4, s4, 0xffff
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, s4
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v1, s7
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v2, s5
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v3, s6
+; PREGFX10-UNPACKED-NEXT: tbuffer_store_format_d16_xyzw v[0:3], off, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED]
+; PREGFX10-UNPACKED-NEXT: s_endpgm
+;
+; PREGFX10-PACKED-LABEL: tbuffer_store_d16_xyzw:
+; PREGFX10-PACKED: ; %bb.0: ; %main_body
+; PREGFX10-PACKED-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
+; PREGFX10-PACKED-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; PREGFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v0, s2
+; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v1, s3
+; PREGFX10-PACKED-NEXT: tbuffer_store_format_d16_xyzw v[0:1], off, s[4:7], 0 format:[BUF_NUM_FORMAT_USCALED]
+; PREGFX10-PACKED-NEXT: s_endpgm
+;
+; GFX10-PACKED-LABEL: tbuffer_store_d16_xyzw:
+; GFX10-PACKED: ; %bb.0: ; %main_body
+; GFX10-PACKED-NEXT: s_clause 0x1
+; GFX10-PACKED-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
+; GFX10-PACKED-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-PACKED-NEXT: v_mov_b32_e32 v0, s2
+; GFX10-PACKED-NEXT: v_mov_b32_e32 v1, s3
+; GFX10-PACKED-NEXT: tbuffer_store_format_d16_xyzw v[0:1], off, s[4:7], 0 format:[BUF_FMT_10_11_11_SSCALED]
+; GFX10-PACKED-NEXT: s_endpgm
+;
+; GFX11-PACKED-LABEL: tbuffer_store_d16_xyzw:
+; GFX11-PACKED: ; %bb.0: ; %main_body
+; GFX11-PACKED-NEXT: s_clause 0x1
+; GFX11-PACKED-NEXT: s_load_b64 s[4:5], s[0:1], 0x34
+; GFX11-PACKED-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
+; GFX11-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, s4
+; GFX11-PACKED-NEXT: v_mov_b32_e32 v1, s5
+; GFX11-PACKED-NEXT: tbuffer_store_d16_format_xyzw v[0:1], off, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM]
+; GFX11-PACKED-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-PACKED-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.tbuffer.store.v4f16(<4 x half> %data, <4 x i32> %rsrc, i32 0, i32 0, i32 33, i32 0)
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.ll
index c58807d7588b3..6e995b0c8234e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.ll
@@ -1,22 +1,35 @@
-;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefixes=GCN,PREGFX10 %s
-;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=GCN,PREGFX10 %s
-;RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GCN,GFX10 %s
-;RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck -check-prefixes=GCN,GFX11 %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefixes=PREGFX10 %s
+;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=PREGFX10 %s
+;RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GFX10 %s
+;RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck -check-prefixes=GFX11 %s
-; GCN-LABEL: {{^}}tbuffer_store:
-; PREGFX10: tbuffer_store_format_xyzw v[0:3], off, s[0:3], 0 format:[BUF_DATA_FORMAT_16_16_16_16,BUF_NUM_FORMAT_USCALED]
-; PREGFX10: tbuffer_store_format_xyzw v[4:7], off, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_SSCALED] glc
-; PREGFX10: tbuffer_store_format_xyzw v[8:11], off, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] slc
-; PREGFX10: tbuffer_store_format_xyzw v[8:11], off, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] glc
-; GFX10: tbuffer_store_format_xyzw v[0:3], off, s[0:3], 0 format:[BUF_FMT_10_10_10_2_UNORM]
-; GFX10: tbuffer_store_format_xyzw v[4:7], off, s[0:3], 0 format:[BUF_FMT_8_8_8_8_SINT] glc
-; GFX10: tbuffer_store_format_xyzw v[8:11], off, s[0:3], 0 format:78 slc
-; GFX10: tbuffer_store_format_xyzw v[8:11], off, s[0:3], 0 format:78 glc dlc
-; GFX11: tbuffer_store_format_xyzw v[0:3], off, s[0:3], 0 format:[BUF_FMT_8_8_8_8_USCALED]
-; GFX11: tbuffer_store_format_xyzw v[4:7], off, s[0:3], 0 format:[BUF_FMT_32_32_32_32_UINT] glc
-; GFX11: tbuffer_store_format_xyzw v[8:11], off, s[0:3], 0 format:78 slc
-; GFX11: tbuffer_store_format_xyzw v[8:11], off, s[0:3], 0 format:78 glc dlc
define amdgpu_ps void @tbuffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <4 x float>) {
+; PREGFX10-LABEL: tbuffer_store:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], off, s[0:3], 0 format:[BUF_DATA_FORMAT_16_16_16_16,BUF_NUM_FORMAT_USCALED]
+; PREGFX10-NEXT: tbuffer_store_format_xyzw v[4:7], off, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_SSCALED] glc
+; PREGFX10-NEXT: tbuffer_store_format_xyzw v[8:11], off, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] slc
+; PREGFX10-NEXT: tbuffer_store_format_xyzw v[8:11], off, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] glc
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: tbuffer_store:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], off, s[0:3], 0 format:[BUF_FMT_10_10_10_2_UNORM]
+; GFX10-NEXT: tbuffer_store_format_xyzw v[4:7], off, s[0:3], 0 format:[BUF_FMT_8_8_8_8_SINT] glc
+; GFX10-NEXT: tbuffer_store_format_xyzw v[8:11], off, s[0:3], 0 format:78 slc
+; GFX10-NEXT: tbuffer_store_format_xyzw v[8:11], off, s[0:3], 0 format:78 glc dlc
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: tbuffer_store:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: s_clause 0x3
+; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], off, s[0:3], 0 format:[BUF_FMT_8_8_8_8_USCALED]
+; GFX11-NEXT: tbuffer_store_format_xyzw v[4:7], off, s[0:3], 0 format:[BUF_FMT_32_32_32_32_UINT] glc
+; GFX11-NEXT: tbuffer_store_format_xyzw v[8:11], off, s[0:3], 0 format:78 slc
+; GFX11-NEXT: tbuffer_store_format_xyzw v[8:11], off, s[0:3], 0 format:78 glc dlc
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
main_body:
%in1 = bitcast <4 x float> %1 to <4 x i32>
%in2 = bitcast <4 x float> %2 to <4 x i32>
@@ -28,55 +41,110 @@ main_body:
ret void
}
-; GCN-LABEL: {{^}}tbuffer_store_immoffs:
-; PREGFX10: tbuffer_store_format_xyzw v[0:3], off, s[0:3], 0 format:[BUF_DATA_FORMAT_16_16,BUF_NUM_FORMAT_FLOAT] offset:42
-; GFX10: tbuffer_store_format_xyzw v[0:3], off, s[0:3], 0 format:117 offset:42
-; GFX11: tbuffer_store_format_xyzw v[0:3], off, s[0:3], 0 format:117 offset:42
define amdgpu_ps void @tbuffer_store_immoffs(<4 x i32> inreg, <4 x float>) {
+; PREGFX10-LABEL: tbuffer_store_immoffs:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], off, s[0:3], 0 format:[BUF_DATA_FORMAT_16_16,BUF_NUM_FORMAT_FLOAT] offset:42
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: tbuffer_store_immoffs:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], off, s[0:3], 0 format:117 offset:42
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: tbuffer_store_immoffs:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], off, s[0:3], 0 format:117 offset:42
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
main_body:
%in1 = bitcast <4 x float> %1 to <4 x i32>
call void @llvm.amdgcn.raw.tbuffer.store.v4i32(<4 x i32> %in1, <4 x i32> %0, i32 42, i32 0, i32 117, i32 0)
ret void
}
-; GCN-LABEL: {{^}}tbuffer_store_scalar_and_imm_offs:
-; PREGFX10: tbuffer_store_format_xyzw v[0:3], off, s[0:3], {{s[0-9]+}} format:[BUF_DATA_FORMAT_16_16,BUF_NUM_FORMAT_FLOAT] offset:42
-; GFX10: tbuffer_store_format_xyzw v[0:3], off, s[0:3], {{s[0-9]+}} format:117 offset:42
-; GFX11: tbuffer_store_format_xyzw v[0:3], off, s[0:3], {{s[0-9]+}} format:117 offset:42
define amdgpu_ps void @tbuffer_store_scalar_and_imm_offs(<4 x i32> inreg, <4 x float> %vdata, i32 inreg %soffset) {
+; PREGFX10-LABEL: tbuffer_store_scalar_and_imm_offs:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], off, s[0:3], s4 format:[BUF_DATA_FORMAT_16_16,BUF_NUM_FORMAT_FLOAT] offset:42
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: tbuffer_store_scalar_and_imm_offs:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], off, s[0:3], s4 format:117 offset:42
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: tbuffer_store_scalar_and_imm_offs:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], off, s[0:3], s4 format:117 offset:42
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
main_body:
%in1 = bitcast <4 x float> %vdata to <4 x i32>
call void @llvm.amdgcn.raw.tbuffer.store.v4i32(<4 x i32> %in1, <4 x i32> %0, i32 42, i32 %soffset, i32 117, i32 0)
ret void
}
-; GCN-LABEL: {{^}}buffer_store_ofs:
-; PREGFX10: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_8_8,BUF_NUM_FORMAT_FLOAT] offen
-; GFX10: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:115 offen
-; GFX11: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:115 offen
define amdgpu_ps void @buffer_store_ofs(<4 x i32> inreg, <4 x float> %vdata, i32 %voffset) {
+; PREGFX10-LABEL: buffer_store_ofs:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_8_8,BUF_NUM_FORMAT_FLOAT] offen
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: buffer_store_ofs:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:115 offen
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: buffer_store_ofs:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:115 offen
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
main_body:
%in1 = bitcast <4 x float> %vdata to <4 x i32>
call void @llvm.amdgcn.raw.tbuffer.store.v4i32(<4 x i32> %in1, <4 x i32> %0, i32 %voffset, i32 0, i32 115, i32 0)
ret void
}
-; GCN-LABEL: {{^}}buffer_store_x1:
-; PREGFX10: tbuffer_store_format_x v0, off, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_FLOAT]
-; GFX10: tbuffer_store_format_x v0, off, s[0:3], 0 format:125
-; GFX11: tbuffer_store_format_x v0, off, s[0:3], 0 format:125
define amdgpu_ps void @buffer_store_x1(<4 x i32> inreg %rsrc, float %data) {
+; PREGFX10-LABEL: buffer_store_x1:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: tbuffer_store_format_x v0, off, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_FLOAT]
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: buffer_store_x1:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: tbuffer_store_format_x v0, off, s[0:3], 0 format:125
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: buffer_store_x1:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: tbuffer_store_format_x v0, off, s[0:3], 0 format:125
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
main_body:
%data.i = bitcast float %data to i32
call void @llvm.amdgcn.raw.tbuffer.store.i32(i32 %data.i, <4 x i32> %rsrc, i32 0, i32 0, i32 125, i32 0)
ret void
}
-; GCN-LABEL: {{^}}buffer_store_x2:
-; PREGFX10: tbuffer_store_format_xy v[0:1], off, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED]
-; GFX10: tbuffer_store_format_xy v[0:1], off, s[0:3], 0 format:[BUF_FMT_10_11_11_SSCALED]
-; GFX11: tbuffer_store_format_xy v[0:1], off, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM]
define amdgpu_ps void @buffer_store_x2(<4 x i32> inreg %rsrc, <2 x float> %data) {
+; PREGFX10-LABEL: buffer_store_x2:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: tbuffer_store_format_xy v[0:1], off, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED]
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: buffer_store_x2:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: tbuffer_store_format_xy v[0:1], off, s[0:3], 0 format:[BUF_FMT_10_11_11_SSCALED]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: buffer_store_x2:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: tbuffer_store_format_xy v[0:1], off, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM]
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
main_body:
%data.i = bitcast <2 x float> %data to <2 x i32>
call void @llvm.amdgcn.raw.tbuffer.store.v2i32(<2 x i32> %data.i, <4 x i32> %rsrc, i32 0, i32 0, i32 33, i32 0)
@@ -87,6 +155,5 @@ declare void @llvm.amdgcn.raw.tbuffer.store.i32(i32, <4 x i32>, i32, i32, i32, i
declare void @llvm.amdgcn.raw.tbuffer.store.v2i32(<2 x i32>, <4 x i32>, i32, i32, i32, i32) #0
declare void @llvm.amdgcn.raw.tbuffer.store.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32, i32) #0
declare void @llvm.amdgcn.raw.tbuffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i32, i32) #0
-
attributes #0 = { nounwind }
attributes #1 = { nounwind readonly }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
index 3446dcd5f9454..cda6de4840aa3 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
@@ -1,13 +1,36 @@
-;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefixes=CHECK,GFX6 %s
-;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefixes=CHECK,GFX8PLUS %s
-;RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck --check-prefixes=CHECK,GFX8PLUS %s
-
-;CHECK-LABEL: {{^}}buffer_load:
-;CHECK: buffer_load_format_xyzw v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen
-;CHECK: buffer_load_format_xyzw v[4:7], {{v[0-9]+}}, s[0:3], 0 idxen glc
-;CHECK: buffer_load_format_xyzw v[8:11], {{v[0-9]+}}, s[0:3], 0 idxen slc
-;CHECK: s_waitcnt
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefixes=GFX6 %s
+;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefixes=GFX8PLUS %s
+;RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck --check-prefixes=GFX11 %s
+
define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) {
+; GFX6-LABEL: buffer_load:
+; GFX6: ; %bb.0: ; %main_body
+; GFX6-NEXT: v_mov_b32_e32 v8, 0
+; GFX6-NEXT: buffer_load_format_xyzw v[0:3], v8, s[0:3], 0 idxen
+; GFX6-NEXT: buffer_load_format_xyzw v[4:7], v8, s[0:3], 0 idxen glc
+; GFX6-NEXT: buffer_load_format_xyzw v[8:11], v8, s[0:3], 0 idxen slc
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8PLUS-LABEL: buffer_load:
+; GFX8PLUS: ; %bb.0: ; %main_body
+; GFX8PLUS-NEXT: v_mov_b32_e32 v8, 0
+; GFX8PLUS-NEXT: buffer_load_format_xyzw v[0:3], v8, s[0:3], 0 idxen
+; GFX8PLUS-NEXT: buffer_load_format_xyzw v[4:7], v8, s[0:3], 0 idxen glc
+; GFX8PLUS-NEXT: buffer_load_format_xyzw v[8:11], v8, s[0:3], 0 idxen slc
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: v_mov_b32_e32 v8, 0
+; GFX11-NEXT: s_clause 0x2
+; GFX11-NEXT: buffer_load_format_xyzw v[0:3], v8, s[0:3], 0 idxen
+; GFX11-NEXT: buffer_load_format_xyzw v[4:7], v8, s[0:3], 0 idxen glc
+; GFX11-NEXT: buffer_load_format_xyzw v[8:11], v8, s[0:3], 0 idxen slc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 0)
%data_glc = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 1)
@@ -18,23 +41,91 @@ main_body:
ret {<4 x float>, <4 x float>, <4 x float>} %r2
}
-;CHECK-LABEL: {{^}}buffer_load_immoffs:
-;CHECK: buffer_load_format_xyzw v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen offset:42
-;CHECK: s_waitcnt
define amdgpu_ps <4 x float> @buffer_load_immoffs(<4 x i32> inreg) {
+; GFX6-LABEL: buffer_load_immoffs:
+; GFX6: ; %bb.0: ; %main_body
+; GFX6-NEXT: v_mov_b32_e32 v0, 0
+; GFX6-NEXT: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 idxen offset:42
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8PLUS-LABEL: buffer_load_immoffs:
+; GFX8PLUS: ; %bb.0: ; %main_body
+; GFX8PLUS-NEXT: v_mov_b32_e32 v0, 0
+; GFX8PLUS-NEXT: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 idxen offset:42
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_immoffs:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-NEXT: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 idxen offset:42
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 42, i32 0, i32 0)
ret <4 x float> %data
}
-;CHECK-LABEL: {{^}}buffer_load_immoffs_large:
-;CHECK-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, s[0:3], 60 idxen offset:4092
-;CHECK-DAG: s_movk_i32 [[OFS1:s[0-9]+]], 0x7ffc
-;CHECK-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, s[0:3], [[OFS1]] idxen offset:4092
-;CHECK-DAG: s_mov_b32 [[OFS2:s[0-9]+]], 0x8ffc
-;CHECK-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, s[0:3], [[OFS2]] idxen offset:4
-;CHECK: s_waitcnt
define amdgpu_ps <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) {
+; GFX6-LABEL: buffer_load_immoffs_large:
+; GFX6: ; %bb.0: ; %main_body
+; GFX6-NEXT: v_mov_b32_e32 v8, 0
+; GFX6-NEXT: s_movk_i32 s4, 0x7ffc
+; GFX6-NEXT: buffer_load_format_xyzw v[0:3], v8, s[0:3], 60 idxen offset:4092
+; GFX6-NEXT: buffer_load_format_xyzw v[4:7], v8, s[0:3], s4 idxen offset:4092
+; GFX6-NEXT: s_mov_b32 s4, 0x8ffc
+; GFX6-NEXT: buffer_load_format_xyzw v[8:11], v8, s[0:3], s4 idxen offset:4
+; GFX6-NEXT: s_waitcnt vmcnt(1)
+; GFX6-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX6-NEXT: v_add_f32_e32 v2, v2, v6
+; GFX6-NEXT: v_add_f32_e32 v1, v1, v5
+; GFX6-NEXT: v_add_f32_e32 v0, v0, v4
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_add_f32_e32 v0, v8, v0
+; GFX6-NEXT: v_add_f32_e32 v1, v9, v1
+; GFX6-NEXT: v_add_f32_e32 v2, v10, v2
+; GFX6-NEXT: v_add_f32_e32 v3, v11, v3
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8PLUS-LABEL: buffer_load_immoffs_large:
+; GFX8PLUS: ; %bb.0: ; %main_body
+; GFX8PLUS-NEXT: v_mov_b32_e32 v8, 0
+; GFX8PLUS-NEXT: s_movk_i32 s4, 0x7ffc
+; GFX8PLUS-NEXT: buffer_load_format_xyzw v[0:3], v8, s[0:3], 60 idxen offset:4092
+; GFX8PLUS-NEXT: buffer_load_format_xyzw v[4:7], v8, s[0:3], s4 idxen offset:4092
+; GFX8PLUS-NEXT: s_mov_b32 s4, 0x8ffc
+; GFX8PLUS-NEXT: buffer_load_format_xyzw v[8:11], v8, s[0:3], s4 idxen offset:4
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(1)
+; GFX8PLUS-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX8PLUS-NEXT: v_add_f32_e32 v2, v2, v6
+; GFX8PLUS-NEXT: v_add_f32_e32 v1, v1, v5
+; GFX8PLUS-NEXT: v_add_f32_e32 v0, v0, v4
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: v_add_f32_e32 v0, v8, v0
+; GFX8PLUS-NEXT: v_add_f32_e32 v1, v9, v1
+; GFX8PLUS-NEXT: v_add_f32_e32 v2, v10, v2
+; GFX8PLUS-NEXT: v_add_f32_e32 v3, v11, v3
+; GFX8PLUS-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_immoffs_large:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: v_mov_b32_e32 v8, 0
+; GFX11-NEXT: s_movk_i32 s4, 0x7ffc
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: buffer_load_format_xyzw v[0:3], v8, s[0:3], 60 idxen offset:4092
+; GFX11-NEXT: buffer_load_format_xyzw v[4:7], v8, s[0:3], s4 idxen offset:4092
+; GFX11-NEXT: s_mov_b32 s4, 0x8ffc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_add_f32_e32 v1, v1, v5
+; GFX11-NEXT: buffer_load_format_xyzw v[8:11], v8, s[0:3], s4 idxen offset:4
+; GFX11-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_add_f32 v3, v3, v7
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v1, v9, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_add_f32 v0, v8, v0 :: v_dual_add_f32 v3, v11, v3
+; GFX11-NEXT: v_add_f32_e32 v2, v10, v2
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%d.0 = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4092, i32 60, i32 0)
%d.1 = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4092, i32 32764, i32 0)
@@ -44,85 +135,256 @@ main_body:
ret <4 x float> %data
}
-;CHECK-LABEL: {{^}}buffer_load_idx:
-;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 idxen
-;CHECK: s_waitcnt
define amdgpu_ps <4 x float> @buffer_load_idx(<4 x i32> inreg, i32) {
+; GFX6-LABEL: buffer_load_idx:
+; GFX6: ; %bb.0: ; %main_body
+; GFX6-NEXT: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 idxen
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8PLUS-LABEL: buffer_load_idx:
+; GFX8PLUS: ; %bb.0: ; %main_body
+; GFX8PLUS-NEXT: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 idxen
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_idx:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 idxen
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 %1, i32 0, i32 0, i32 0)
ret <4 x float> %data
}
-;CHECK-LABEL: {{^}}buffer_load_ofs:
-;CHECK: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen
-;CHECK: s_waitcnt
define amdgpu_ps <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) {
+; GFX6-LABEL: buffer_load_ofs:
+; GFX6: ; %bb.0: ; %main_body
+; GFX6-NEXT: s_mov_b32 s4, 0
+; GFX6-NEXT: v_mov_b32_e32 v1, v0
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8PLUS-LABEL: buffer_load_ofs:
+; GFX8PLUS: ; %bb.0: ; %main_body
+; GFX8PLUS-NEXT: s_mov_b32 s4, 0
+; GFX8PLUS-NEXT: v_mov_b32_e32 v1, v0
+; GFX8PLUS-NEXT: v_mov_b32_e32 v0, s4
+; GFX8PLUS-NEXT: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_ofs:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: s_mov_b32 s4, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v0, s4
+; GFX11-NEXT: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 %1, i32 0, i32 0)
ret <4 x float> %data
}
-;CHECK-LABEL: {{^}}buffer_load_ofs_imm:
-;CHECK: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen offset:60
-;CHECK: s_waitcnt
define amdgpu_ps <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) {
+; GFX6-LABEL: buffer_load_ofs_imm:
+; GFX6: ; %bb.0: ; %main_body
+; GFX6-NEXT: s_mov_b32 s4, 0
+; GFX6-NEXT: v_mov_b32_e32 v1, v0
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen offset:60
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8PLUS-LABEL: buffer_load_ofs_imm:
+; GFX8PLUS: ; %bb.0: ; %main_body
+; GFX8PLUS-NEXT: s_mov_b32 s4, 0
+; GFX8PLUS-NEXT: v_mov_b32_e32 v1, v0
+; GFX8PLUS-NEXT: v_mov_b32_e32 v0, s4
+; GFX8PLUS-NEXT: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen offset:60
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_ofs_imm:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: s_mov_b32 s4, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v0, s4
+; GFX11-NEXT: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen offset:60
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%ofs = add i32 %1, 60
%data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 %ofs, i32 0, i32 0)
ret <4 x float> %data
}
-;CHECK-LABEL: {{^}}buffer_load_both:
-;CHECK: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen
-;CHECK: s_waitcnt
define amdgpu_ps <4 x float> @buffer_load_both(<4 x i32> inreg, i32, i32) {
+; GFX6-LABEL: buffer_load_both:
+; GFX6: ; %bb.0: ; %main_body
+; GFX6-NEXT: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8PLUS-LABEL: buffer_load_both:
+; GFX8PLUS: ; %bb.0: ; %main_body
+; GFX8PLUS-NEXT: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_both:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 %1, i32 %2, i32 0, i32 0)
ret <4 x float> %data
}
-;CHECK-LABEL: {{^}}buffer_load_both_reversed:
-;CHECK: v_mov_b32_e32 v2, v0
-;CHECK: buffer_load_format_xyzw v[0:3], v[1:2], s[0:3], 0 idxen offen
-;CHECK: s_waitcnt
define amdgpu_ps <4 x float> @buffer_load_both_reversed(<4 x i32> inreg, i32, i32) {
+; GFX6-LABEL: buffer_load_both_reversed:
+; GFX6: ; %bb.0: ; %main_body
+; GFX6-NEXT: v_mov_b32_e32 v2, v0
+; GFX6-NEXT: buffer_load_format_xyzw v[0:3], v[1:2], s[0:3], 0 idxen offen
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8PLUS-LABEL: buffer_load_both_reversed:
+; GFX8PLUS: ; %bb.0: ; %main_body
+; GFX8PLUS-NEXT: v_mov_b32_e32 v2, v0
+; GFX8PLUS-NEXT: buffer_load_format_xyzw v[0:3], v[1:2], s[0:3], 0 idxen offen
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_both_reversed:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: v_mov_b32_e32 v2, v0
+; GFX11-NEXT: buffer_load_format_xyzw v[0:3], v[1:2], s[0:3], 0 idxen offen
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 %2, i32 %1, i32 0, i32 0)
ret <4 x float> %data
}
-;CHECK-LABEL: {{^}}buffer_load_x:
-;CHECK: buffer_load_format_x v0, {{v[0-9]+}}, s[0:3], 0 idxen
-;CHECK: s_waitcnt
define amdgpu_ps float @buffer_load_x(<4 x i32> inreg %rsrc) {
+; GFX6-LABEL: buffer_load_x:
+; GFX6: ; %bb.0: ; %main_body
+; GFX6-NEXT: v_mov_b32_e32 v0, 0
+; GFX6-NEXT: buffer_load_format_x v0, v0, s[0:3], 0 idxen
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8PLUS-LABEL: buffer_load_x:
+; GFX8PLUS: ; %bb.0: ; %main_body
+; GFX8PLUS-NEXT: v_mov_b32_e32 v0, 0
+; GFX8PLUS-NEXT: buffer_load_format_x v0, v0, s[0:3], 0 idxen
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_x:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-NEXT: buffer_load_format_x v0, v0, s[0:3], 0 idxen
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%data = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
ret float %data
}
-;CHECK-LABEL: {{^}}buffer_load_x_i32:
-;CHECK: buffer_load_format_x v0, {{v[0-9]+}}, s[0:3], 0 idxen
-;CHECK: s_waitcnt
define amdgpu_ps float @buffer_load_x_i32(<4 x i32> inreg %rsrc) {
+; GFX6-LABEL: buffer_load_x_i32:
+; GFX6: ; %bb.0: ; %main_body
+; GFX6-NEXT: v_mov_b32_e32 v0, 0
+; GFX6-NEXT: buffer_load_format_x v0, v0, s[0:3], 0 idxen
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8PLUS-LABEL: buffer_load_x_i32:
+; GFX8PLUS: ; %bb.0: ; %main_body
+; GFX8PLUS-NEXT: v_mov_b32_e32 v0, 0
+; GFX8PLUS-NEXT: buffer_load_format_x v0, v0, s[0:3], 0 idxen
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_x_i32:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-NEXT: buffer_load_format_x v0, v0, s[0:3], 0 idxen
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%data = call i32 @llvm.amdgcn.struct.buffer.load.format.i32(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
%fdata = bitcast i32 %data to float
ret float %fdata
}
-;CHECK-LABEL: {{^}}buffer_load_xy:
-;CHECK: buffer_load_format_xy v[0:1], {{v[0-9]+}}, s[0:3], 0 idxen
-;CHECK: s_waitcnt
define amdgpu_ps <2 x float> @buffer_load_xy(<4 x i32> inreg %rsrc) {
+; GFX6-LABEL: buffer_load_xy:
+; GFX6: ; %bb.0: ; %main_body
+; GFX6-NEXT: v_mov_b32_e32 v0, 0
+; GFX6-NEXT: buffer_load_format_xy v[0:1], v0, s[0:3], 0 idxen
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8PLUS-LABEL: buffer_load_xy:
+; GFX8PLUS: ; %bb.0: ; %main_body
+; GFX8PLUS-NEXT: v_mov_b32_e32 v0, 0
+; GFX8PLUS-NEXT: buffer_load_format_xy v[0:1], v0, s[0:3], 0 idxen
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_xy:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-NEXT: buffer_load_format_xy v[0:1], v0, s[0:3], 0 idxen
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%data = call <2 x float> @llvm.amdgcn.struct.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
ret <2 x float> %data
}
-;CHECK-LABEL: {{^}}buffer_load_v4i32_tfe:
-;CHECK: buffer_load_format_xyzw v[2:6], {{v[0-9]+}}, s[0:3], 0 idxen tfe
-;CHECK: s_waitcnt
define amdgpu_cs float @buffer_load_v4i32_tfe(<4 x i32> inreg %rsrc, ptr addrspace(1) %out) {
+; GFX6-LABEL: buffer_load_v4i32_tfe:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_mov_b32_e32 v2, 0
+; GFX6-NEXT: buffer_load_format_xyzw v[2:6], v2, s[0:3], 0 idxen tfe
+; GFX6-NEXT: s_mov_b32 s2, 0
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s0, s2
+; GFX6-NEXT: s_mov_b32 s1, s2
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: buffer_store_dwordx4 v[2:5], v[0:1], s[0:3], 0 addr64
+; GFX6-NEXT: v_mov_b32_e32 v0, v6
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8PLUS-LABEL: buffer_load_v4i32_tfe:
+; GFX8PLUS: ; %bb.0:
+; GFX8PLUS-NEXT: v_mov_b32_e32 v2, 0
+; GFX8PLUS-NEXT: buffer_load_format_xyzw v[2:6], v2, s[0:3], 0 idxen tfe
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: flat_store_dwordx4 v[0:1], v[2:5]
+; GFX8PLUS-NEXT: v_mov_b32_e32 v0, v6
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_v4i32_tfe:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: buffer_load_format_xyzw v[2:6], v2, s[0:3], 0 idxen tfe
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX11-NEXT: v_mov_b32_e32 v0, v6
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: ; return to shader part epilog
%load = call { <4 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v4i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
%data = extractvalue { <4 x i32>, i32 } %load, 0
store <4 x i32> %data, ptr addrspace(1) %out
@@ -131,10 +393,40 @@ define amdgpu_cs float @buffer_load_v4i32_tfe(<4 x i32> inreg %rsrc, ptr addrspa
ret float %fstatus
}
-;CHECK-LABEL: {{^}}buffer_load_v4f32_tfe:
-;CHECK: buffer_load_format_xyzw v[2:6], {{v[0-9]+}}, s[0:3], 0 idxen tfe
-;CHECK: s_waitcnt
define amdgpu_cs float @buffer_load_v4f32_tfe(<4 x i32> inreg %rsrc, ptr addrspace(1) %out) {
+; GFX6-LABEL: buffer_load_v4f32_tfe:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_mov_b32_e32 v2, 0
+; GFX6-NEXT: buffer_load_format_xyzw v[2:6], v2, s[0:3], 0 idxen tfe
+; GFX6-NEXT: s_mov_b32 s2, 0
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s0, s2
+; GFX6-NEXT: s_mov_b32 s1, s2
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: buffer_store_dwordx4 v[2:5], v[0:1], s[0:3], 0 addr64
+; GFX6-NEXT: v_mov_b32_e32 v0, v6
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8PLUS-LABEL: buffer_load_v4f32_tfe:
+; GFX8PLUS: ; %bb.0:
+; GFX8PLUS-NEXT: v_mov_b32_e32 v2, 0
+; GFX8PLUS-NEXT: buffer_load_format_xyzw v[2:6], v2, s[0:3], 0 idxen tfe
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: flat_store_dwordx4 v[0:1], v[2:5]
+; GFX8PLUS-NEXT: v_mov_b32_e32 v0, v6
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_v4f32_tfe:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: buffer_load_format_xyzw v[2:6], v2, s[0:3], 0 idxen tfe
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX11-NEXT: v_mov_b32_e32 v0, v6
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: ; return to shader part epilog
%load = call { <4 x float>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v4f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
%data = extractvalue { <4 x float>, i32 } %load, 0
store <4 x float> %data, ptr addrspace(1) %out
@@ -143,10 +435,41 @@ define amdgpu_cs float @buffer_load_v4f32_tfe(<4 x i32> inreg %rsrc, ptr addrspa
ret float %fstatus
}
-;CHECK-LABEL: {{^}}buffer_load_v3i32_tfe:
-;CHECK: buffer_load_format_xyz v[2:5], {{v[0-9]+}}, s[0:3], 0 idxen tfe
-;CHECK: s_waitcnt
define amdgpu_cs float @buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addrspace(1) %out) {
+; GFX6-LABEL: buffer_load_v3i32_tfe:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_mov_b32_e32 v2, 0
+; GFX6-NEXT: buffer_load_format_xyz v[2:5], v2, s[0:3], 0 idxen tfe
+; GFX6-NEXT: s_mov_b32 s2, 0
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s0, s2
+; GFX6-NEXT: s_mov_b32 s1, s2
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: buffer_store_dword v4, v[0:1], s[0:3], 0 addr64 offset:8
+; GFX6-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
+; GFX6-NEXT: v_mov_b32_e32 v0, v5
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8PLUS-LABEL: buffer_load_v3i32_tfe:
+; GFX8PLUS: ; %bb.0:
+; GFX8PLUS-NEXT: v_mov_b32_e32 v2, 0
+; GFX8PLUS-NEXT: buffer_load_format_xyz v[2:5], v2, s[0:3], 0 idxen tfe
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: flat_store_dwordx3 v[0:1], v[2:4]
+; GFX8PLUS-NEXT: v_mov_b32_e32 v0, v5
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_v3i32_tfe:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: buffer_load_format_xyz v[2:5], v2, s[0:3], 0 idxen tfe
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: global_store_b96 v[0:1], v[2:4], off
+; GFX11-NEXT: v_mov_b32_e32 v0, v5
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: ; return to shader part epilog
%load = call { <3 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v3i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
%data = extractvalue { <3 x i32>, i32 } %load, 0
store <3 x i32> %data, ptr addrspace(1) %out
@@ -155,10 +478,41 @@ define amdgpu_cs float @buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, ptr addrspa
ret float %fstatus
}
-;CHECK-LABEL: {{^}}buffer_load_v3f32_tfe:
-;CHECK: buffer_load_format_xyz v[2:5], {{v[0-9]+}}, s[0:3], 0 idxen tfe
-;CHECK: s_waitcnt
define amdgpu_cs float @buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addrspace(1) %out) {
+; GFX6-LABEL: buffer_load_v3f32_tfe:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_mov_b32_e32 v2, 0
+; GFX6-NEXT: buffer_load_format_xyz v[2:5], v2, s[0:3], 0 idxen tfe
+; GFX6-NEXT: s_mov_b32 s2, 0
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s0, s2
+; GFX6-NEXT: s_mov_b32 s1, s2
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: buffer_store_dword v4, v[0:1], s[0:3], 0 addr64 offset:8
+; GFX6-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
+; GFX6-NEXT: v_mov_b32_e32 v0, v5
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8PLUS-LABEL: buffer_load_v3f32_tfe:
+; GFX8PLUS: ; %bb.0:
+; GFX8PLUS-NEXT: v_mov_b32_e32 v2, 0
+; GFX8PLUS-NEXT: buffer_load_format_xyz v[2:5], v2, s[0:3], 0 idxen tfe
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: flat_store_dwordx3 v[0:1], v[2:4]
+; GFX8PLUS-NEXT: v_mov_b32_e32 v0, v5
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_v3f32_tfe:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: buffer_load_format_xyz v[2:5], v2, s[0:3], 0 idxen tfe
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: global_store_b96 v[0:1], v[2:4], off
+; GFX11-NEXT: v_mov_b32_e32 v0, v5
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: ; return to shader part epilog
%load = call { <3 x float>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v3f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
%data = extractvalue { <3 x float>, i32 } %load, 0
store <3 x float> %data, ptr addrspace(1) %out
@@ -167,11 +521,40 @@ define amdgpu_cs float @buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, ptr addrspa
ret float %fstatus
}
-;CHECK-LABEL: {{^}}buffer_load_v2i32_tfe:
-;GFX6: buffer_load_format_xyz v[2:5], {{v[0-9]+}}, s[0:3], 0 idxen tfe
-;GFX8PLUS: buffer_load_format_xy v[2:4], {{v[0-9]+}}, s[0:3], 0 idxen tfe
-;CHECK: s_waitcnt
define amdgpu_cs float @buffer_load_v2i32_tfe(<4 x i32> inreg %rsrc, ptr addrspace(1) %out) {
+; GFX6-LABEL: buffer_load_v2i32_tfe:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_mov_b32_e32 v2, 0
+; GFX6-NEXT: buffer_load_format_xyz v[2:5], v2, s[0:3], 0 idxen tfe
+; GFX6-NEXT: s_mov_b32 s2, 0
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s0, s2
+; GFX6-NEXT: s_mov_b32 s1, s2
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
+; GFX6-NEXT: v_mov_b32_e32 v0, v4
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8PLUS-LABEL: buffer_load_v2i32_tfe:
+; GFX8PLUS: ; %bb.0:
+; GFX8PLUS-NEXT: v_mov_b32_e32 v2, 0
+; GFX8PLUS-NEXT: buffer_load_format_xy v[2:4], v2, s[0:3], 0 idxen tfe
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8PLUS-NEXT: v_mov_b32_e32 v0, v4
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_v2i32_tfe:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: buffer_load_format_xy v[2:4], v2, s[0:3], 0 idxen tfe
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX11-NEXT: v_mov_b32_e32 v0, v4
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: ; return to shader part epilog
%load = call { <2 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v2i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
%data = extractvalue { <2 x i32>, i32 } %load, 0
store <2 x i32> %data, ptr addrspace(1) %out
@@ -180,11 +563,40 @@ define amdgpu_cs float @buffer_load_v2i32_tfe(<4 x i32> inreg %rsrc, ptr addrspa
ret float %fstatus
}
-;CHECK-LABEL: {{^}}buffer_load_v2f32_tfe:
-;GFX6: buffer_load_format_xyz v[2:5], {{v[0-9]+}}, s[0:3], 0 idxen tfe
-;GFX8PLUS: buffer_load_format_xy v[2:4], {{v[0-9]+}}, s[0:3], 0 idxen tfe
-;CHECK: s_waitcnt
define amdgpu_cs float @buffer_load_v2f32_tfe(<4 x i32> inreg %rsrc, ptr addrspace(1) %out) {
+; GFX6-LABEL: buffer_load_v2f32_tfe:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_mov_b32_e32 v2, 0
+; GFX6-NEXT: buffer_load_format_xyz v[2:5], v2, s[0:3], 0 idxen tfe
+; GFX6-NEXT: s_mov_b32 s2, 0
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s0, s2
+; GFX6-NEXT: s_mov_b32 s1, s2
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
+; GFX6-NEXT: v_mov_b32_e32 v0, v4
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8PLUS-LABEL: buffer_load_v2f32_tfe:
+; GFX8PLUS: ; %bb.0:
+; GFX8PLUS-NEXT: v_mov_b32_e32 v2, 0
+; GFX8PLUS-NEXT: buffer_load_format_xy v[2:4], v2, s[0:3], 0 idxen tfe
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8PLUS-NEXT: v_mov_b32_e32 v0, v4
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_v2f32_tfe:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: buffer_load_format_xy v[2:4], v2, s[0:3], 0 idxen tfe
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX11-NEXT: v_mov_b32_e32 v0, v4
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: ; return to shader part epilog
%load = call { <2 x float>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v2f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
%data = extractvalue { <2 x float>, i32 } %load, 0
store <2 x float> %data, ptr addrspace(1) %out
@@ -193,10 +605,40 @@ define amdgpu_cs float @buffer_load_v2f32_tfe(<4 x i32> inreg %rsrc, ptr addrspa
ret float %fstatus
}
-;CHECK-LABEL: {{^}}buffer_load_i32_tfe:
-;CHECK: buffer_load_format_x v[2:3], {{v[0-9]+}}, s[0:3], 0 idxen tfe
-;CHECK: s_waitcnt
define amdgpu_cs float @buffer_load_i32_tfe(<4 x i32> inreg %rsrc, ptr addrspace(1) %out) {
+; GFX6-LABEL: buffer_load_i32_tfe:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_mov_b32_e32 v2, 0
+; GFX6-NEXT: buffer_load_format_x v[2:3], v2, s[0:3], 0 idxen tfe
+; GFX6-NEXT: s_mov_b32 s2, 0
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s0, s2
+; GFX6-NEXT: s_mov_b32 s1, s2
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
+; GFX6-NEXT: v_mov_b32_e32 v0, v3
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8PLUS-LABEL: buffer_load_i32_tfe:
+; GFX8PLUS: ; %bb.0:
+; GFX8PLUS-NEXT: v_mov_b32_e32 v2, 0
+; GFX8PLUS-NEXT: buffer_load_format_x v[2:3], v2, s[0:3], 0 idxen tfe
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: flat_store_dword v[0:1], v2
+; GFX8PLUS-NEXT: v_mov_b32_e32 v0, v3
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_i32_tfe:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: buffer_load_format_x v[2:3], v2, s[0:3], 0 idxen tfe
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: global_store_b32 v[0:1], v2, off
+; GFX11-NEXT: v_mov_b32_e32 v0, v3
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: ; return to shader part epilog
%load = call { i32, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
%data = extractvalue { i32, i32 } %load, 0
store i32 %data, ptr addrspace(1) %out
@@ -205,10 +647,40 @@ define amdgpu_cs float @buffer_load_i32_tfe(<4 x i32> inreg %rsrc, ptr addrspace
ret float %fstatus
}
-;CHECK-LABEL: {{^}}buffer_load_f32_tfe:
-;CHECK: buffer_load_format_x v[2:3], {{v[0-9]+}}, s[0:3], 0 idxen tfe
-;CHECK: s_waitcnt
define amdgpu_cs float @buffer_load_f32_tfe(<4 x i32> inreg %rsrc, ptr addrspace(1) %out) {
+; GFX6-LABEL: buffer_load_f32_tfe:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: v_mov_b32_e32 v2, 0
+; GFX6-NEXT: buffer_load_format_x v[2:3], v2, s[0:3], 0 idxen tfe
+; GFX6-NEXT: s_mov_b32 s2, 0
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s0, s2
+; GFX6-NEXT: s_mov_b32 s1, s2
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
+; GFX6-NEXT: v_mov_b32_e32 v0, v3
+; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0)
+; GFX6-NEXT: ; return to shader part epilog
+;
+; GFX8PLUS-LABEL: buffer_load_f32_tfe:
+; GFX8PLUS: ; %bb.0:
+; GFX8PLUS-NEXT: v_mov_b32_e32 v2, 0
+; GFX8PLUS-NEXT: buffer_load_format_x v[2:3], v2, s[0:3], 0 idxen tfe
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: flat_store_dword v[0:1], v2
+; GFX8PLUS-NEXT: v_mov_b32_e32 v0, v3
+; GFX8PLUS-NEXT: s_waitcnt vmcnt(0)
+; GFX8PLUS-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_f32_tfe:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: buffer_load_format_x v[2:3], v2, s[0:3], 0 idxen tfe
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: global_store_b32 v[0:1], v2, off
+; GFX11-NEXT: v_mov_b32_e32 v0, v3
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: ; return to shader part epilog
%load = call { float, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0)
%data = extractvalue { float, i32 } %load, 0
store float %data, ptr addrspace(1) %out
@@ -229,5 +701,4 @@ declare { <2 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v2i32i32s(<
declare { <2 x float>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v2f32i32s(<4 x i32>, i32, i32, i32, i32 immarg) #0
declare { i32, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_i32i32s(<4 x i32>, i32, i32, i32, i32 immarg) #0
declare { float, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_f32i32s(<4 x i32>, i32, i32, i32, i32 immarg) #0
-
attributes #0 = { nounwind readonly }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
index 1a7fd5efb4870..ca77d5e41ca2a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
@@ -2,6 +2,7 @@
; RUN: llc -mcpu=gfx1010 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -mcpu=gfx900 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -mcpu=gfx810 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
+; RUN: llc -mcpu=gfx1100 -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11 %s
@esgs_ring = external addrspace(3) global [0 x i32], align 65536
define amdgpu_gs void @main(<4 x i32> %arg, i32 %arg1) {
@@ -84,6 +85,32 @@ define amdgpu_gs void @main(<4 x i32> %arg, i32 %arg1) {
; GFX8-NEXT: v_mov_b32_e32 v2, 0
; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: ds_write2_b32 v2, v0, v1 offset0:7 offset1:8
+;
+; GFX11-LABEL: main:
+; GFX11: ; %bb.0: ; %bb
+; GFX11-NEXT: s_mov_b32 s1, exec_lo
+; GFX11-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1
+; GFX11-NEXT: v_readfirstlane_b32 s4, v0
+; GFX11-NEXT: v_readfirstlane_b32 s5, v1
+; GFX11-NEXT: v_readfirstlane_b32 s6, v2
+; GFX11-NEXT: v_readfirstlane_b32 s7, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX11-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX11-NEXT: s_and_saveexec_b32 s0, s0
+; GFX11-NEXT: buffer_load_d16_format_xyz v[5:6], v4, s[4:7], 0 idxen
+; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
+; GFX11-NEXT: ; implicit-def: $vgpr4
+; GFX11-NEXT: s_xor_b32 exec_lo, exec_lo, s0
+; GFX11-NEXT: s_cbranch_execnz .LBB0_1
+; GFX11-NEXT: ; %bb.2:
+; GFX11-NEXT: s_mov_b32 exec_lo, s1
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v5
+; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v1, 0xffff, v6
+; GFX11-NEXT: ds_store_2addr_b32 v2, v0, v1 offset0:7 offset1:8
bb:
%i = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 undef)
%i2 = call nsz arcp <3 x half> @llvm.amdgcn.struct.buffer.load.format.v3f16(<4 x i32> %arg, i32 %arg1, i32 0, i32 0, i32 0)
@@ -101,12 +128,9 @@ bb:
store i32 %i8, ptr addrspace(3) %i12, align 4
unreachable
}
-
; Function Attrs: nounwind readnone willreturn
declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0
-
; Function Attrs: nounwind readonly willreturn
declare <3 x half> @llvm.amdgcn.struct.buffer.load.format.v3f16(<4 x i32>, i32, i32, i32, i32 immarg) #1
-
attributes #0 = { nounwind readnone willreturn }
attributes #1 = { nounwind readonly willreturn }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll
index 503a8c70c8302..c17ea09677465 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll
@@ -1,58 +1,151 @@
-; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefixes=GCN,PREGFX10,PREGFX10-UNPACKED %s
-; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GCN,PACKED,PREGFX10,PREGFX10-PACKED %s
-; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GCN,PACKED,PREGFX10,PREGFX10-PACKED %s
-; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GCN,PACKED,GFX10,GFX10-PACKED %s
-; RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GCN,PACKED,GFX10,GFX10-PACKED %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefixes=PREGFX10-UNPACKED %s
+; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PREGFX10-PACKED %s
+; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=PREGFX10-PACKED %s
+; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX10-PACKED %s
+; RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefixes=GFX11-PACKED %s
-; GCN-LABEL: {{^}}tbuffer_load_d16_x:
-; GCN: v_mov_b32_e32 [[ZEROREG:v[0-9]+]], 0
-; PREGFX10: tbuffer_load_format_d16_x v{{[0-9]+}}, [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
-; GFX10: tbuffer_load_{{format_d16|d16_format}}_x v{{[0-9]+}}, [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT] idxen
define amdgpu_ps half @tbuffer_load_d16_x(<4 x i32> inreg %rsrc) {
+; PREGFX10-UNPACKED-LABEL: tbuffer_load_d16_x:
+; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, 0 ; encoding: [0x80,0x02,0x00,0x7e]
+; PREGFX10-UNPACKED-NEXT: tbuffer_load_format_d16_x v0, v0, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen ; encoding: [0x00,0x20,0xb4,0xe8,0x00,0x00,0x00,0x80]
+; PREGFX10-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
+; PREGFX10-UNPACKED-NEXT: ; return to shader part epilog
+;
+; PREGFX10-PACKED-LABEL: tbuffer_load_d16_x:
+; PREGFX10-PACKED: ; %bb.0: ; %main_body
+; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v0, 0
+; PREGFX10-PACKED-NEXT: tbuffer_load_format_d16_x v0, v0, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
+; PREGFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-PACKED-NEXT: ; return to shader part epilog
+;
+; GFX10-PACKED-LABEL: tbuffer_load_d16_x:
+; GFX10-PACKED: ; %bb.0: ; %main_body
+; GFX10-PACKED-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-PACKED-NEXT: tbuffer_load_format_d16_x v0, v0, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen
+; GFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
+; GFX10-PACKED-NEXT: ; return to shader part epilog
+;
+; GFX11-PACKED-LABEL: tbuffer_load_d16_x:
+; GFX11-PACKED: ; %bb.0: ; %main_body
+; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-PACKED-NEXT: tbuffer_load_d16_format_x v0, v0, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen
+; GFX11-PACKED-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PACKED-NEXT: ; return to shader part epilog
main_body:
%data = call half @llvm.amdgcn.struct.tbuffer.load.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 22, i32 0)
ret half %data
}
-; GCN-LABEL: {{^}}tbuffer_load_d16_xy:
-; GCN: v_mov_b32_e32 [[ZEROREG:v[0-9]+]], 0
-; PREGFX10-UNPACKED: tbuffer_load_format_d16_xy v[{{[0-9]+}}:[[HI:[0-9]+]]], [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
-; PREGFX10-UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
-
-; PREGFX10-PACKED: tbuffer_load_format_d16_xy v[[FULL:[0-9]+]], [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
-; GFX10-PACKED: tbuffer_load_{{format_d16|d16_format}}_xy v[[FULL:[0-9]+]], [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT] idxen
-; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[FULL]]
define amdgpu_ps half @tbuffer_load_d16_xy(<4 x i32> inreg %rsrc) {
+; PREGFX10-UNPACKED-LABEL: tbuffer_load_d16_xy:
+; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, 0 ; encoding: [0x80,0x02,0x00,0x7e]
+; PREGFX10-UNPACKED-NEXT: tbuffer_load_format_d16_xy v[0:1], v0, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen ; encoding: [0x00,0xa0,0xb4,0xe8,0x00,0x00,0x00,0x80]
+; PREGFX10-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, v1 ; encoding: [0x01,0x03,0x00,0x7e]
+; PREGFX10-UNPACKED-NEXT: ; return to shader part epilog
+;
+; PREGFX10-PACKED-LABEL: tbuffer_load_d16_xy:
+; PREGFX10-PACKED: ; %bb.0: ; %main_body
+; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v0, 0
+; PREGFX10-PACKED-NEXT: tbuffer_load_format_d16_xy v0, v0, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
+; PREGFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; PREGFX10-PACKED-NEXT: ; return to shader part epilog
+;
+; GFX10-PACKED-LABEL: tbuffer_load_d16_xy:
+; GFX10-PACKED: ; %bb.0: ; %main_body
+; GFX10-PACKED-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-PACKED-NEXT: tbuffer_load_format_d16_xy v0, v0, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen
+; GFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
+; GFX10-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX10-PACKED-NEXT: ; return to shader part epilog
+;
+; GFX11-PACKED-LABEL: tbuffer_load_d16_xy:
+; GFX11-PACKED: ; %bb.0: ; %main_body
+; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-PACKED-NEXT: tbuffer_load_d16_format_xy v0, v0, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen
+; GFX11-PACKED-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-PACKED-NEXT: ; return to shader part epilog
main_body:
%data = call <2 x half> @llvm.amdgcn.struct.tbuffer.load.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 22, i32 0)
%elt = extractelement <2 x half> %data, i32 1
ret half %elt
}
-; GCN-LABEL: {{^}}tbuffer_load_d16_xyz:
-; GCN: v_mov_b32_e32 [[ZEROREG:v[0-9]+]], 0
-; PREGFX10-UNPACKED: tbuffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
-; PREGFX10-UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
-
-; PREGFX10-PACKED: tbuffer_load_format_d16_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
-; GFX10-PACKED: tbuffer_load_{{format_d16|d16_format}}_xyz v[{{[0-9]+}}:[[HI:[0-9]+]]], [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT] idxen
-; PACKED: v_mov_b{{16|32}}_e32 v{{[0-9]+(\.(l|h))?}}, v[[HI]]{{(\.(l,h))?}}
define amdgpu_ps half @tbuffer_load_d16_xyz(<4 x i32> inreg %rsrc) {
+; PREGFX10-UNPACKED-LABEL: tbuffer_load_d16_xyz:
+; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, 0 ; encoding: [0x80,0x02,0x00,0x7e]
+; PREGFX10-UNPACKED-NEXT: tbuffer_load_format_d16_xyz v[0:2], v0, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen ; encoding: [0x00,0x20,0xb5,0xe8,0x00,0x00,0x00,0x80]
+; PREGFX10-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, v2 ; encoding: [0x02,0x03,0x00,0x7e]
+; PREGFX10-UNPACKED-NEXT: ; return to shader part epilog
+;
+; PREGFX10-PACKED-LABEL: tbuffer_load_d16_xyz:
+; PREGFX10-PACKED: ; %bb.0: ; %main_body
+; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v0, 0
+; PREGFX10-PACKED-NEXT: tbuffer_load_format_d16_xyz v[0:1], v0, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
+; PREGFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v0, v1
+; PREGFX10-PACKED-NEXT: ; return to shader part epilog
+;
+; GFX10-PACKED-LABEL: tbuffer_load_d16_xyz:
+; GFX10-PACKED: ; %bb.0: ; %main_body
+; GFX10-PACKED-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-PACKED-NEXT: tbuffer_load_format_d16_xyz v[0:1], v0, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen
+; GFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
+; GFX10-PACKED-NEXT: v_mov_b32_e32 v0, v1
+; GFX10-PACKED-NEXT: ; return to shader part epilog
+;
+; GFX11-PACKED-LABEL: tbuffer_load_d16_xyz:
+; GFX11-PACKED: ; %bb.0: ; %main_body
+; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-PACKED-NEXT: tbuffer_load_d16_format_xyz v[0:1], v0, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen
+; GFX11-PACKED-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, v1
+; GFX11-PACKED-NEXT: ; return to shader part epilog
main_body:
%data = call <3 x half> @llvm.amdgcn.struct.tbuffer.load.v3f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 22, i32 0)
%elt = extractelement <3 x half> %data, i32 2
ret half %elt
}
-; GCN-LABEL: {{^}}tbuffer_load_d16_xyzw:
-; GCN: v_mov_b32_e32 [[ZEROREG:v[0-9]+]], 0
-; PREGFX10-UNPACKED: tbuffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
-; PREGFX10-UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]]
-
-; PREGFX10-PACKED: tbuffer_load_format_d16_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
-; GFX10-PACKED: tbuffer_load_{{format_d16|d16_format}}_xyzw v[{{[0-9]+}}:[[HI:[0-9]+]]], [[ZEROREG]], s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_32_FLOAT] idxen
-; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]]
define amdgpu_ps half @tbuffer_load_d16_xyzw(<4 x i32> inreg %rsrc) {
+; PREGFX10-UNPACKED-LABEL: tbuffer_load_d16_xyzw:
+; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, 0 ; encoding: [0x80,0x02,0x00,0x7e]
+; PREGFX10-UNPACKED-NEXT: tbuffer_load_format_d16_xyzw v[0:3], v0, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen ; encoding: [0x00,0xa0,0xb5,0xe8,0x00,0x00,0x00,0x80]
+; PREGFX10-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, v3 ; encoding: [0x03,0x03,0x00,0x7e]
+; PREGFX10-UNPACKED-NEXT: ; return to shader part epilog
+;
+; PREGFX10-PACKED-LABEL: tbuffer_load_d16_xyzw:
+; PREGFX10-PACKED: ; %bb.0: ; %main_body
+; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v0, 0
+; PREGFX10-PACKED-NEXT: tbuffer_load_format_d16_xyzw v[0:1], v0, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen
+; PREGFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; PREGFX10-PACKED-NEXT: ; return to shader part epilog
+;
+; GFX10-PACKED-LABEL: tbuffer_load_d16_xyzw:
+; GFX10-PACKED: ; %bb.0: ; %main_body
+; GFX10-PACKED-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-PACKED-NEXT: tbuffer_load_format_d16_xyzw v[0:1], v0, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen
+; GFX10-PACKED-NEXT: s_waitcnt vmcnt(0)
+; GFX10-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX10-PACKED-NEXT: ; return to shader part epilog
+;
+; GFX11-PACKED-LABEL: tbuffer_load_d16_xyzw:
+; GFX11-PACKED: ; %bb.0: ; %main_body
+; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-PACKED-NEXT: tbuffer_load_d16_format_xyzw v[0:1], v0, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen
+; GFX11-PACKED-NEXT: s_waitcnt vmcnt(0)
+; GFX11-PACKED-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX11-PACKED-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x half> @llvm.amdgcn.struct.tbuffer.load.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 22, i32 0)
%elt = extractelement <4 x half> %data, i32 3
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.ll
index abea30b384815..f38e7908b9afa 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.ll
@@ -1,24 +1,41 @@
-;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefixes=GCN,PREGFX10 %s
-;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=GCN,PREGFX10 %s
-;RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GCN,GFX10 %s
-;RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck -check-prefixes=GCN,GFX11 %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefixes=PREGFX10 %s
+;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=PREGFX10 %s
+;RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GFX10 %s
+;RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck -check-prefixes=GFX11 %s
-; GCN-LABEL: {{^}}tbuffer_load:
-; GCN: v_mov_b32_e32 [[ZEROREG:v[0-9]+]], 0
-; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen
-; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen glc
-; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen slc
-; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen glc
-; GFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:78 idxen
-; GFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_FMT_32_32_SINT] idxen glc
-; GFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_FMT_32_FLOAT] idxen slc
-; GFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_FMT_32_FLOAT] idxen glc dlc
-; GFX11: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:78 idxen
-; GFX11: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_FMT_32_32_32_32_FLOAT] idxen glc
-; GFX11: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_FMT_32_FLOAT] idxen slc
-; GFX11: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_FMT_32_FLOAT] idxen glc dlc
-; GCN: s_waitcnt
define amdgpu_vs {<4 x float>, <4 x float>, <4 x float>, <4 x float>} @tbuffer_load(<4 x i32> inreg) {
+; PREGFX10-LABEL: tbuffer_load:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: v_mov_b32_e32 v12, 0
+; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen
+; PREGFX10-NEXT: tbuffer_load_format_xyzw v[4:7], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen glc
+; PREGFX10-NEXT: tbuffer_load_format_xyzw v[8:11], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen slc
+; PREGFX10-NEXT: tbuffer_load_format_xyzw v[12:15], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_SNORM] idxen glc
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: tbuffer_load:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: v_mov_b32_e32 v16, 0
+; GFX10-NEXT: s_clause 0x3
+; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v16, s[0:3], 0 format:78 idxen
+; GFX10-NEXT: tbuffer_load_format_xyzw v[4:7], v16, s[0:3], 0 format:[BUF_FMT_32_32_SINT] idxen glc
+; GFX10-NEXT: tbuffer_load_format_xyzw v[8:11], v16, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen slc
+; GFX10-NEXT: tbuffer_load_format_xyzw v[12:15], v16, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen glc dlc
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: tbuffer_load:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: v_mov_b32_e32 v12, 0
+; GFX11-NEXT: s_clause 0x3
+; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], v12, s[0:3], 0 format:78 idxen
+; GFX11-NEXT: tbuffer_load_format_xyzw v[4:7], v12, s[0:3], 0 format:[BUF_FMT_32_32_32_32_FLOAT] idxen glc
+; GFX11-NEXT: tbuffer_load_format_xyzw v[8:11], v12, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen slc
+; GFX11-NEXT: tbuffer_load_format_xyzw v[12:15], v12, s[0:3], 0 format:[BUF_FMT_32_FLOAT] idxen glc dlc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%vdata = call <4 x i32> @llvm.amdgcn.struct.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 78, i32 0)
%vdata_glc = call <4 x i32> @llvm.amdgcn.struct.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 63, i32 1)
@@ -34,31 +51,62 @@ main_body:
ret {<4 x float>, <4 x float>, <4 x float>, <4 x float>} %r3
}
-; GCN-LABEL: {{^}}tbuffer_load_immoffs:
-; GCN: v_mov_b32_e32 [[ZEROREG:v[0-9]+]], 0
-; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen offset:42
-; GFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:78 idxen offset:42
-; GFX11: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 0 format:78 idxen offset:42
define amdgpu_vs <4 x float> @tbuffer_load_immoffs(<4 x i32> inreg) {
+; PREGFX10-LABEL: tbuffer_load_immoffs:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: v_mov_b32_e32 v0, 0
+; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen offset:42
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: tbuffer_load_immoffs:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:78 idxen offset:42
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: tbuffer_load_immoffs:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:78 idxen offset:42
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%vdata = call <4 x i32> @llvm.amdgcn.struct.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 42, i32 0, i32 78, i32 0)
%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
ret <4 x float> %vdata.f
}
-; GCN-LABEL: {{^}}tbuffer_load_immoffs_large
-; GCN: v_mov_b32_e32 [[ZEROREG:v[0-9]+]], 0
-; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 61 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_USCALED] idxen offset:4095
-; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_SSCALED] idxen offset:73
-; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen offset:1
-; GFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 61 format:[BUF_FMT_10_10_10_2_SSCALED] idxen offset:4095
-; GFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} format:[BUF_FMT_32_32_UINT] idxen offset:73
-; GFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} format:[BUF_FMT_32_32_32_32_FLOAT] idxen offset:1
-; GFX11: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, 61 format:[BUF_FMT_8_8_8_8_SINT] idxen offset:4095
-; GFX11: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} format:[BUF_FMT_32_32_32_32_SINT] idxen offset:73
-; GFX11: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} format:77 idxen offset:1
-; GCN: s_waitcnt
define amdgpu_vs {<4 x float>, <4 x float>, <4 x float>} @tbuffer_load_immoffs_large(<4 x i32> inreg, i32 inreg %soffs) {
+; PREGFX10-LABEL: tbuffer_load_immoffs_large:
+; PREGFX10: ; %bb.0:
+; PREGFX10-NEXT: v_mov_b32_e32 v8, 0
+; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v8, s[0:3], 61 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_USCALED] idxen offset:4095
+; PREGFX10-NEXT: tbuffer_load_format_xyzw v[4:7], v8, s[0:3], s4 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_SSCALED] idxen offset:73
+; PREGFX10-NEXT: tbuffer_load_format_xyzw v[8:11], v8, s[0:3], s4 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen offset:1
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: tbuffer_load_immoffs_large:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: v_mov_b32_e32 v12, 0
+; GFX10-NEXT: s_clause 0x2
+; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v12, s[0:3], 61 format:[BUF_FMT_10_10_10_2_SSCALED] idxen offset:4095
+; GFX10-NEXT: tbuffer_load_format_xyzw v[4:7], v12, s[0:3], s4 format:[BUF_FMT_32_32_UINT] idxen offset:73
+; GFX10-NEXT: tbuffer_load_format_xyzw v[8:11], v12, s[0:3], s4 format:[BUF_FMT_32_32_32_32_FLOAT] idxen offset:1
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: tbuffer_load_immoffs_large:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_mov_b32_e32 v8, 0
+; GFX11-NEXT: s_clause 0x2
+; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], v8, s[0:3], 61 format:[BUF_FMT_8_8_8_8_SINT] idxen offset:4095
+; GFX11-NEXT: tbuffer_load_format_xyzw v[4:7], v8, s[0:3], s4 format:[BUF_FMT_32_32_32_32_SINT] idxen offset:73
+; GFX11-NEXT: tbuffer_load_format_xyzw v[8:11], v8, s[0:3], s4 format:77 idxen offset:1
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
%vdata = call <4 x i32> @llvm.amdgcn.struct.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 4095, i32 61, i32 47, i32 0)
%vdata_glc = call <4 x i32> @llvm.amdgcn.struct.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 73, i32 %soffs, i32 62, i32 0)
%vdata_slc = call <4 x i32> @llvm.amdgcn.struct.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 1, i32 %soffs, i32 77, i32 0)
@@ -71,33 +119,90 @@ define amdgpu_vs {<4 x float>, <4 x float>, <4 x float>} @tbuffer_load_immoffs_l
ret {<4 x float>, <4 x float>, <4 x float>} %r2
}
-; GCN-LABEL: {{^}}tbuffer_load_idx:
-; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen
-; GFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:78 idxen
-; GFX11: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:78 idxen
define amdgpu_vs <4 x float> @tbuffer_load_idx(<4 x i32> inreg, i32 %vindex) {
+; PREGFX10-LABEL: tbuffer_load_idx:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: tbuffer_load_idx:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:78 idxen
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: tbuffer_load_idx:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], v0, s[0:3], 0 format:78 idxen
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%vdata = call <4 x i32> @llvm.amdgcn.struct.tbuffer.load.v4i32(<4 x i32> %0, i32 %vindex, i32 0, i32 0, i32 78, i32 0)
%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
ret <4 x float> %vdata.f
}
-; GCN-LABEL: {{^}}tbuffer_load_ofs:
-; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen offen
-; GFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:78 idxen offen
-; GFX11: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:78 idxen offen
define amdgpu_vs <4 x float> @tbuffer_load_ofs(<4 x i32> inreg, i32 %voffs) {
+; PREGFX10-LABEL: tbuffer_load_ofs:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: s_mov_b32 s4, 0
+; PREGFX10-NEXT: v_mov_b32_e32 v1, v0
+; PREGFX10-NEXT: v_mov_b32_e32 v0, s4
+; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen offen
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: tbuffer_load_ofs:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: s_mov_b32 s4, 0
+; GFX10-NEXT: v_mov_b32_e32 v1, v0
+; GFX10-NEXT: v_mov_b32_e32 v0, s4
+; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:78 idxen offen
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: tbuffer_load_ofs:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: s_mov_b32 s4, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v0, s4
+; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:78 idxen offen
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%vdata = call <4 x i32> @llvm.amdgcn.struct.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 %voffs, i32 0, i32 78, i32 0)
%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
ret <4 x float> %vdata.f
}
-; GCN-LABEL: {{^}}tbuffer_load_ofs_imm:
-; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen offen offset:52
-; GFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:78 idxen offen offset:52
-; GFX11: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:78 idxen offen offset:52
define amdgpu_vs <4 x float> @tbuffer_load_ofs_imm(<4 x i32> inreg, i32 %voffs) {
+; PREGFX10-LABEL: tbuffer_load_ofs_imm:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: s_mov_b32 s4, 0
+; PREGFX10-NEXT: v_mov_b32_e32 v1, v0
+; PREGFX10-NEXT: v_mov_b32_e32 v0, s4
+; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen offen offset:52
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: tbuffer_load_ofs_imm:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: s_mov_b32 s4, 0
+; GFX10-NEXT: v_mov_b32_e32 v1, v0
+; GFX10-NEXT: v_mov_b32_e32 v0, s4
+; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:78 idxen offen offset:52
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: tbuffer_load_ofs_imm:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: s_mov_b32 s4, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v0, s4
+; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:78 idxen offen offset:52
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%ofs = add i32 %voffs, 52
%vdata = call <4 x i32> @llvm.amdgcn.struct.tbuffer.load.v4i32(<4 x i32> %0, i32 0, i32 %ofs, i32 0, i32 78, i32 0)
@@ -105,33 +210,77 @@ main_body:
ret <4 x float> %vdata.f
}
-; GCN-LABEL: {{^}}tbuffer_load_both:
-; PREGFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen offen
-; GFX10: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:78 idxen offen
-; GFX11: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:78 idxen offen
define amdgpu_vs <4 x float> @tbuffer_load_both(<4 x i32> inreg, i32 %vindex, i32 %voffs) {
+; PREGFX10-LABEL: tbuffer_load_both:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen offen
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: tbuffer_load_both:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:78 idxen offen
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: tbuffer_load_both:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: tbuffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 format:78 idxen offen
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
main_body:
%vdata = call <4 x i32> @llvm.amdgcn.struct.tbuffer.load.v4i32(<4 x i32> %0, i32 %vindex, i32 %voffs, i32 0, i32 78, i32 0)
%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
ret <4 x float> %vdata.f
}
-
-; GCN-LABEL: {{^}}buffer_load_xy:
-; PREGFX10: tbuffer_load_format_xy {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen
-; GFX10: tbuffer_load_format_xy {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_FMT_32_32_32_32_FLOAT] idxen
-; GFX11: tbuffer_load_format_xy {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:77 idxen
define amdgpu_vs <2 x float> @buffer_load_xy(<4 x i32> inreg %rsrc) {
+; PREGFX10-LABEL: buffer_load_xy:
+; PREGFX10: ; %bb.0:
+; PREGFX10-NEXT: v_mov_b32_e32 v0, 0
+; PREGFX10-NEXT: tbuffer_load_format_xy v[0:1], v0, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: buffer_load_xy:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: tbuffer_load_format_xy v[0:1], v0, s[0:3], 0 format:[BUF_FMT_32_32_32_32_FLOAT] idxen
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_xy:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-NEXT: tbuffer_load_format_xy v[0:1], v0, s[0:3], 0 format:77 idxen
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
%vdata = call <2 x i32> @llvm.amdgcn.struct.tbuffer.load.v2i32(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 77, i32 0)
%vdata.f = bitcast <2 x i32> %vdata to <2 x float>
ret <2 x float> %vdata.f
}
-; GCN-LABEL: {{^}}buffer_load_x:
-; PREGFX10: tbuffer_load_format_x {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen
-; GFX10: tbuffer_load_format_x {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:[BUF_FMT_32_32_32_32_FLOAT] idxen
-; GFX11: tbuffer_load_format_x {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 format:77 idxen
define amdgpu_vs float @buffer_load_x(<4 x i32> inreg %rsrc) {
+; PREGFX10-LABEL: buffer_load_x:
+; PREGFX10: ; %bb.0:
+; PREGFX10-NEXT: v_mov_b32_e32 v0, 0
+; PREGFX10-NEXT: tbuffer_load_format_x v0, v0, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: ; return to shader part epilog
+;
+; GFX10-LABEL: buffer_load_x:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: tbuffer_load_format_x v0, v0, s[0:3], 0 format:[BUF_FMT_32_32_32_32_FLOAT] idxen
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: buffer_load_x:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-NEXT: tbuffer_load_format_x v0, v0, s[0:3], 0 format:77 idxen
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: ; return to shader part epilog
%vdata = call i32 @llvm.amdgcn.struct.tbuffer.load.i32(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 77, i32 0)
%vdata.f = bitcast i32 %vdata to float
ret float %vdata.f
@@ -141,4 +290,3 @@ declare i32 @llvm.amdgcn.struct.tbuffer.load.i32(<4 x i32>, i32, i32, i32, i32,
declare <2 x i32> @llvm.amdgcn.struct.tbuffer.load.v2i32(<4 x i32>, i32, i32, i32, i32, i32)
declare <4 x i32> @llvm.amdgcn.struct.tbuffer.load.v4i32(<4 x i32>, i32, i32, i32, i32, i32)
declare <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32>, i32, i32, i32, i32, i32)
-
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
index c85a21fc85eb1..720bbe923a6be 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
@@ -1,77 +1,230 @@
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,PREGFX10,UNPACKED,PREGFX10-UNPACKED %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx810 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,PREGFX10,PACKED,PREGFX10-PACKED %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,PREGFX10,PACKED,PREGFX10-PACKED %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,PACKED,GFX10-PACKED %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,PACKED,GFX10-PACKED %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=PREGFX10-UNPACKED %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx810 -verify-machineinstrs < %s | FileCheck -check-prefixes=PREGFX10-PACKED %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=PREGFX10-PACKED %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10-PACKED %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11-PACKED %s
-; GCN-LABEL: {{^}}tbuffer_store_d16_x:
-; GCN-DAG: s_load_{{dwordx4|b128}}
-; GCN-DAG: s_load_{{dwordx2|b64}} s[[[S_LO:[0-9]+]]
-; GCN-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[S_LO]]
-; PREGFX10: tbuffer_store_format_d16_x v[[V_LO]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
-; GFX10: tbuffer_store_{{format_d16|d16_format}}_x v[[V_LO]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_{{.*}}] idxen
define amdgpu_kernel void @tbuffer_store_d16_x(<4 x i32> %rsrc, half %data, i32 %vindex) {
+; PREGFX10-UNPACKED-LABEL: tbuffer_store_d16_x:
+; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
+; PREGFX10-UNPACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
+; PREGFX10-UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; PREGFX10-UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, s6
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v1, s7
+; PREGFX10-UNPACKED-NEXT: tbuffer_store_format_d16_x v0, v1, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
+; PREGFX10-UNPACKED-NEXT: s_endpgm
+;
+; PREGFX10-PACKED-LABEL: tbuffer_store_d16_x:
+; PREGFX10-PACKED: ; %bb.0: ; %main_body
+; PREGFX10-PACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
+; PREGFX10-PACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; PREGFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v0, s6
+; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v1, s7
+; PREGFX10-PACKED-NEXT: tbuffer_store_format_d16_x v0, v1, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
+; PREGFX10-PACKED-NEXT: s_endpgm
+;
+; GFX10-PACKED-LABEL: tbuffer_store_d16_x:
+; GFX10-PACKED: ; %bb.0: ; %main_body
+; GFX10-PACKED-NEXT: s_clause 0x1
+; GFX10-PACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
+; GFX10-PACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-PACKED-NEXT: v_mov_b32_e32 v0, s6
+; GFX10-PACKED-NEXT: v_mov_b32_e32 v1, s7
+; GFX10-PACKED-NEXT: tbuffer_store_format_d16_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
+; GFX10-PACKED-NEXT: s_endpgm
+;
+; GFX11-PACKED-LABEL: tbuffer_store_d16_x:
+; GFX11-PACKED: ; %bb.0: ; %main_body
+; GFX11-PACKED-NEXT: s_clause 0x1
+; GFX11-PACKED-NEXT: s_load_b64 s[4:5], s[0:1], 0x10
+; GFX11-PACKED-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
+; GFX11-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, s4
+; GFX11-PACKED-NEXT: v_mov_b32_e32 v1, s5
+; GFX11-PACKED-NEXT: tbuffer_store_d16_format_x v0, v1, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] idxen
+; GFX11-PACKED-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-PACKED-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.tbuffer.store.f16(half %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 33, i32 0)
ret void
}
-; GCN-LABEL: {{^}}tbuffer_store_d16_xy:
-; GCN: s_load_{{dwordx2|b64}} s[[[S_DATA:[0-9]+]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 0x10
-; UNPACKED-DAG: s_lshr_b32 [[SHR:s[0-9]+]], s[[S_DATA]], 16
-; UNPACKED-DAG: s_and_b32 [[MASKED:s[0-9]+]], s[[S_DATA]], 0xffff{{$}}
-; UNPACKED-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[MASKED]]
-; UNPACKED-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], [[SHR]]
-; PREGFX10-UNPACKED: tbuffer_store_format_d16_xy v[[[V_LO]]:[[V_HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
-
-; PREGFX10-PACKED: tbuffer_store_format_d16_xy v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
-; GFX10-PACKED: tbuffer_store_{{format_d16|d16_format}}_xy v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_{{.*}}] idxen
define amdgpu_kernel void @tbuffer_store_d16_xy(<4 x i32> %rsrc, <2 x half> %data, i32 %vindex) {
+; PREGFX10-UNPACKED-LABEL: tbuffer_store_d16_xy:
+; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
+; PREGFX10-UNPACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
+; PREGFX10-UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; PREGFX10-UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
+; PREGFX10-UNPACKED-NEXT: s_lshr_b32 s4, s6, 16
+; PREGFX10-UNPACKED-NEXT: s_and_b32 s5, s6, 0xffff
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, s5
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v1, s4
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v2, s7
+; PREGFX10-UNPACKED-NEXT: tbuffer_store_format_d16_xy v[0:1], v2, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
+; PREGFX10-UNPACKED-NEXT: s_endpgm
+;
+; PREGFX10-PACKED-LABEL: tbuffer_store_d16_xy:
+; PREGFX10-PACKED: ; %bb.0: ; %main_body
+; PREGFX10-PACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
+; PREGFX10-PACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; PREGFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v0, s6
+; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v1, s7
+; PREGFX10-PACKED-NEXT: tbuffer_store_format_d16_xy v0, v1, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
+; PREGFX10-PACKED-NEXT: s_endpgm
+;
+; GFX10-PACKED-LABEL: tbuffer_store_d16_xy:
+; GFX10-PACKED: ; %bb.0: ; %main_body
+; GFX10-PACKED-NEXT: s_clause 0x1
+; GFX10-PACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
+; GFX10-PACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-PACKED-NEXT: v_mov_b32_e32 v0, s6
+; GFX10-PACKED-NEXT: v_mov_b32_e32 v1, s7
+; GFX10-PACKED-NEXT: tbuffer_store_format_d16_xy v0, v1, s[0:3], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
+; GFX10-PACKED-NEXT: s_endpgm
+;
+; GFX11-PACKED-LABEL: tbuffer_store_d16_xy:
+; GFX11-PACKED: ; %bb.0: ; %main_body
+; GFX11-PACKED-NEXT: s_clause 0x1
+; GFX11-PACKED-NEXT: s_load_b64 s[4:5], s[0:1], 0x10
+; GFX11-PACKED-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
+; GFX11-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, s4
+; GFX11-PACKED-NEXT: v_mov_b32_e32 v1, s5
+; GFX11-PACKED-NEXT: tbuffer_store_d16_format_xy v0, v1, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] idxen
+; GFX11-PACKED-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-PACKED-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.tbuffer.store.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 33, i32 0)
ret void
}
-; GCN-LABEL: {{^}}tbuffer_store_d16_xyz:
-; GCN-DAG: s_load_{{dwordx2|b64}} s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
-
-; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
-; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], 0xffff{{$}}
-; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
-
-; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
-; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED1]]
-; PREGFX10-UNPACKED: tbuffer_store_format_d16_xyz v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
-
-; PACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
-; PACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
-; PACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[MASKED0]]
-; PREGFX10-PACKED: tbuffer_store_format_d16_xyz v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
-; GFX10-PACKED: tbuffer_store_{{format_d16|d16_format}}_xyz v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_{{.*}}] idxen
define amdgpu_kernel void @tbuffer_store_d16_xyz(<4 x i32> %rsrc, <4 x half> %data, i32 %vindex) {
+; PREGFX10-UNPACKED-LABEL: tbuffer_store_d16_xyz:
+; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
+; PREGFX10-UNPACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
+; PREGFX10-UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; PREGFX10-UNPACKED-NEXT: s_load_dword s4, s[4:5], 0x18
+; PREGFX10-UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
+; PREGFX10-UNPACKED-NEXT: s_and_b32 s5, s7, 0xffff
+; PREGFX10-UNPACKED-NEXT: s_lshr_b32 s7, s6, 16
+; PREGFX10-UNPACKED-NEXT: s_and_b32 s6, s6, 0xffff
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, s6
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v1, s7
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v2, s5
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v3, s4
+; PREGFX10-UNPACKED-NEXT: tbuffer_store_format_d16_xyz v[0:2], v3, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
+; PREGFX10-UNPACKED-NEXT: s_endpgm
+;
+; PREGFX10-PACKED-LABEL: tbuffer_store_d16_xyz:
+; PREGFX10-PACKED: ; %bb.0: ; %main_body
+; PREGFX10-PACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
+; PREGFX10-PACKED-NEXT: s_load_dword s8, s[4:5], 0x18
+; PREGFX10-PACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; PREGFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; PREGFX10-PACKED-NEXT: s_and_b32 s4, s7, 0xffff
+; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v0, s6
+; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v1, s4
+; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v2, s8
+; PREGFX10-PACKED-NEXT: tbuffer_store_format_d16_xyz v[0:1], v2, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
+; PREGFX10-PACKED-NEXT: s_endpgm
+;
+; GFX10-PACKED-LABEL: tbuffer_store_d16_xyz:
+; GFX10-PACKED: ; %bb.0: ; %main_body
+; GFX10-PACKED-NEXT: s_clause 0x2
+; GFX10-PACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
+; GFX10-PACKED-NEXT: s_load_dword s8, s[4:5], 0x18
+; GFX10-PACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-PACKED-NEXT: s_and_b32 s4, s7, 0xffff
+; GFX10-PACKED-NEXT: v_mov_b32_e32 v0, s6
+; GFX10-PACKED-NEXT: v_mov_b32_e32 v1, s4
+; GFX10-PACKED-NEXT: v_mov_b32_e32 v2, s8
+; GFX10-PACKED-NEXT: tbuffer_store_format_d16_xyz v[0:1], v2, s[0:3], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
+; GFX10-PACKED-NEXT: s_endpgm
+;
+; GFX11-PACKED-LABEL: tbuffer_store_d16_xyz:
+; GFX11-PACKED: ; %bb.0: ; %main_body
+; GFX11-PACKED-NEXT: s_clause 0x2
+; GFX11-PACKED-NEXT: s_load_b64 s[4:5], s[0:1], 0x10
+; GFX11-PACKED-NEXT: s_load_b32 s6, s[0:1], 0x18
+; GFX11-PACKED-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
+; GFX11-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-PACKED-NEXT: s_and_b32 s5, s5, 0xffff
+; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, s4
+; GFX11-PACKED-NEXT: v_mov_b32_e32 v1, s5
+; GFX11-PACKED-NEXT: v_mov_b32_e32 v2, s6
+; GFX11-PACKED-NEXT: tbuffer_store_d16_format_xyz v[0:1], v2, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] idxen
+; GFX11-PACKED-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-PACKED-NEXT: s_endpgm
main_body:
%data_subvec = shufflevector <4 x half> %data, <4 x half> undef, <3 x i32> <i32 0, i32 1, i32 2>
call void @llvm.amdgcn.struct.tbuffer.store.v3f16(<3 x half> %data_subvec, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 33, i32 0)
ret void
}
-; GCN-LABEL: {{^}}tbuffer_store_d16_xyzw:
-; GCN-DAG: s_load_{{dwordx2|b64}} s[[[S_DATA_0:[0-9]+]]:[[S_DATA_1:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, 0x10
-
-; UNPACKED-DAG: s_lshr_b32 [[SHR0:s[0-9]+]], s[[S_DATA_0]], 16
-; UNPACKED-DAG: s_and_b32 [[MASKED0:s[0-9]+]], s[[S_DATA_0]], 0xffff{{$}}
-; UNPACKED-DAG: s_lshr_b32 [[SHR1:s[0-9]+]], s[[S_DATA_1]], 16
-; UNPACKED-DAG: s_and_b32 [[MASKED1:s[0-9]+]], s[[S_DATA_1]], 0xffff{{$}}
-
-; UNPACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], [[MASKED0]]
-; UNPACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SHR1]]
-; PREGFX10-UNPACKED: tbuffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
-
-; PACKED-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s[[S_DATA_0]]
-; PACKED-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], s[[S_DATA_1]]
-; PREGFX10-PACKED: tbuffer_store_format_d16_xyzw v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
-; GFX10-PACKED: tbuffer_store_{{format_d16|d16_format}}_xyzw v[[[LO]]:[[HI]]], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 format:[BUF_FMT_{{.*}}] idxen
define amdgpu_kernel void @tbuffer_store_d16_xyzw(<4 x i32> %rsrc, <4 x half> %data, i32 %vindex) {
+; PREGFX10-UNPACKED-LABEL: tbuffer_store_d16_xyzw:
+; PREGFX10-UNPACKED: ; %bb.0: ; %main_body
+; PREGFX10-UNPACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
+; PREGFX10-UNPACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; PREGFX10-UNPACKED-NEXT: s_load_dword s4, s[4:5], 0x18
+; PREGFX10-UNPACKED-NEXT: s_waitcnt lgkmcnt(0)
+; PREGFX10-UNPACKED-NEXT: s_lshr_b32 s5, s7, 16
+; PREGFX10-UNPACKED-NEXT: s_and_b32 s7, s7, 0xffff
+; PREGFX10-UNPACKED-NEXT: s_lshr_b32 s8, s6, 16
+; PREGFX10-UNPACKED-NEXT: s_and_b32 s6, s6, 0xffff
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v0, s6
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v1, s8
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v2, s7
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v3, s5
+; PREGFX10-UNPACKED-NEXT: v_mov_b32_e32 v4, s4
+; PREGFX10-UNPACKED-NEXT: tbuffer_store_format_d16_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
+; PREGFX10-UNPACKED-NEXT: s_endpgm
+;
+; PREGFX10-PACKED-LABEL: tbuffer_store_d16_xyzw:
+; PREGFX10-PACKED: ; %bb.0: ; %main_body
+; PREGFX10-PACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
+; PREGFX10-PACKED-NEXT: s_load_dword s8, s[4:5], 0x18
+; PREGFX10-PACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; PREGFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v0, s6
+; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v1, s7
+; PREGFX10-PACKED-NEXT: v_mov_b32_e32 v2, s8
+; PREGFX10-PACKED-NEXT: tbuffer_store_format_d16_xyzw v[0:1], v2, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
+; PREGFX10-PACKED-NEXT: s_endpgm
+;
+; GFX10-PACKED-LABEL: tbuffer_store_d16_xyzw:
+; GFX10-PACKED: ; %bb.0: ; %main_body
+; GFX10-PACKED-NEXT: s_clause 0x2
+; GFX10-PACKED-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10
+; GFX10-PACKED-NEXT: s_load_dword s8, s[4:5], 0x18
+; GFX10-PACKED-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX10-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-PACKED-NEXT: v_mov_b32_e32 v0, s6
+; GFX10-PACKED-NEXT: v_mov_b32_e32 v1, s7
+; GFX10-PACKED-NEXT: v_mov_b32_e32 v2, s8
+; GFX10-PACKED-NEXT: tbuffer_store_format_d16_xyzw v[0:1], v2, s[0:3], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
+; GFX10-PACKED-NEXT: s_endpgm
+;
+; GFX11-PACKED-LABEL: tbuffer_store_d16_xyzw:
+; GFX11-PACKED: ; %bb.0: ; %main_body
+; GFX11-PACKED-NEXT: s_clause 0x2
+; GFX11-PACKED-NEXT: s_load_b64 s[4:5], s[0:1], 0x10
+; GFX11-PACKED-NEXT: s_load_b32 s6, s[0:1], 0x18
+; GFX11-PACKED-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
+; GFX11-PACKED-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-PACKED-NEXT: v_mov_b32_e32 v0, s4
+; GFX11-PACKED-NEXT: v_mov_b32_e32 v1, s5
+; GFX11-PACKED-NEXT: v_mov_b32_e32 v2, s6
+; GFX11-PACKED-NEXT: tbuffer_store_d16_format_xyzw v[0:1], v2, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] idxen
+; GFX11-PACKED-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-PACKED-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.struct.tbuffer.store.v4f16(<4 x half> %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 33, i32 0)
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.ll
index d2cb42d1c719f..885cb470a64f2 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.ll
@@ -1,23 +1,47 @@
-;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefixes=GCN,VERDE,PREGFX10 %s
-;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=GCN,PREGFX10 %s
-;RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GCN,GFX10 %s
-;RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck -check-prefixes=GCN,GFX11 %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefixes=VERDE %s
+;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefixes=PREGFX10 %s
+;RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefixes=GFX10 %s
+;RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck -check-prefixes=GFX11 %s
-; GCN-LABEL: {{^}}tbuffer_store:
-; GCN: v_mov_b32_e32 [[ZEROREG:v[0-9]+]], 0
-; PREGFX10: tbuffer_store_format_xyzw v[0:3], [[ZEROREG]], s[0:3], 0 format:[BUF_DATA_FORMAT_16_16_16_16,BUF_NUM_FORMAT_USCALED] idxen
-; PREGFX10: tbuffer_store_format_xyzw v[4:7], [[ZEROREG]], s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_SSCALED] idxen glc
-; PREGFX10: tbuffer_store_format_xyzw v[8:11], [[ZEROREG]], s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen slc
-; PREGFX10: tbuffer_store_format_xyzw v[8:11], [[ZEROREG]], s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen glc
-; GFX10: tbuffer_store_format_xyzw v[0:3], [[ZEROREG]], s[0:3], 0 format:[BUF_FMT_10_10_10_2_UNORM] idxen
-; GFX10: tbuffer_store_format_xyzw v[4:7], [[ZEROREG]], s[0:3], 0 format:[BUF_FMT_8_8_8_8_SINT] idxen glc
-; GFX10: tbuffer_store_format_xyzw v[8:11], [[ZEROREG]], s[0:3], 0 format:78 idxen slc
-; GFX10: tbuffer_store_format_xyzw v[8:11], [[ZEROREG]], s[0:3], 0 format:78 idxen glc dlc
-; GFX11: tbuffer_store_format_xyzw v[0:3], [[ZEROREG]], s[0:3], 0 format:[BUF_FMT_8_8_8_8_USCALED] idxen
-; GFX11: tbuffer_store_format_xyzw v[4:7], [[ZEROREG]], s[0:3], 0 format:[BUF_FMT_32_32_32_32_UINT] idxen glc
-; GFX11: tbuffer_store_format_xyzw v[8:11], [[ZEROREG]], s[0:3], 0 format:78 idxen slc
-; GFX11: tbuffer_store_format_xyzw v[8:11], [[ZEROREG]], s[0:3], 0 format:78 idxen glc dlc
define amdgpu_ps void @tbuffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <4 x float>) {
+; VERDE-LABEL: tbuffer_store:
+; VERDE: ; %bb.0: ; %main_body
+; VERDE-NEXT: v_mov_b32_e32 v12, 0
+; VERDE-NEXT: tbuffer_store_format_xyzw v[0:3], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_16_16_16_16,BUF_NUM_FORMAT_USCALED] idxen
+; VERDE-NEXT: tbuffer_store_format_xyzw v[4:7], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_SSCALED] idxen glc
+; VERDE-NEXT: tbuffer_store_format_xyzw v[8:11], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen slc
+; VERDE-NEXT: tbuffer_store_format_xyzw v[8:11], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen glc
+; VERDE-NEXT: s_endpgm
+;
+; PREGFX10-LABEL: tbuffer_store:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: v_mov_b32_e32 v12, 0
+; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_16_16_16_16,BUF_NUM_FORMAT_USCALED] idxen
+; PREGFX10-NEXT: tbuffer_store_format_xyzw v[4:7], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_SSCALED] idxen glc
+; PREGFX10-NEXT: tbuffer_store_format_xyzw v[8:11], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen slc
+; PREGFX10-NEXT: tbuffer_store_format_xyzw v[8:11], v12, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_UINT] idxen glc
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: tbuffer_store:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: v_mov_b32_e32 v12, 0
+; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v12, s[0:3], 0 format:[BUF_FMT_10_10_10_2_UNORM] idxen
+; GFX10-NEXT: tbuffer_store_format_xyzw v[4:7], v12, s[0:3], 0 format:[BUF_FMT_8_8_8_8_SINT] idxen glc
+; GFX10-NEXT: tbuffer_store_format_xyzw v[8:11], v12, s[0:3], 0 format:78 idxen slc
+; GFX10-NEXT: tbuffer_store_format_xyzw v[8:11], v12, s[0:3], 0 format:78 idxen glc dlc
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: tbuffer_store:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: v_mov_b32_e32 v12, 0
+; GFX11-NEXT: s_clause 0x3
+; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], v12, s[0:3], 0 format:[BUF_FMT_8_8_8_8_USCALED] idxen
+; GFX11-NEXT: tbuffer_store_format_xyzw v[4:7], v12, s[0:3], 0 format:[BUF_FMT_32_32_32_32_UINT] idxen glc
+; GFX11-NEXT: tbuffer_store_format_xyzw v[8:11], v12, s[0:3], 0 format:78 idxen slc
+; GFX11-NEXT: tbuffer_store_format_xyzw v[8:11], v12, s[0:3], 0 format:78 idxen glc dlc
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
main_body:
%in1 = bitcast <4 x float> %1 to <4 x i32>
%in2 = bitcast <4 x float> %2 to <4 x i32>
@@ -29,76 +53,195 @@ main_body:
ret void
}
-; GCN-LABEL: {{^}}tbuffer_store_immoffs:
-; GCN: v_mov_b32_e32 [[ZEROREG:v[0-9]+]], 0
-; PREGFX10: tbuffer_store_format_xyzw v[0:3], [[ZEROREG]], s[0:3], 0 format:[BUF_DATA_FORMAT_16_16,BUF_NUM_FORMAT_FLOAT] idxen offset:42
-; GFX10: tbuffer_store_format_xyzw v[0:3], [[ZEROREG]], s[0:3], 0 format:117 idxen offset:42
-; GFX11: tbuffer_store_format_xyzw v[0:3], [[ZEROREG]], s[0:3], 0 format:117 idxen offset:42
define amdgpu_ps void @tbuffer_store_immoffs(<4 x i32> inreg, <4 x float>) {
+; VERDE-LABEL: tbuffer_store_immoffs:
+; VERDE: ; %bb.0: ; %main_body
+; VERDE-NEXT: v_mov_b32_e32 v4, 0
+; VERDE-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_16_16,BUF_NUM_FORMAT_FLOAT] idxen offset:42
+; VERDE-NEXT: s_endpgm
+;
+; PREGFX10-LABEL: tbuffer_store_immoffs:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: v_mov_b32_e32 v4, 0
+; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_16_16,BUF_NUM_FORMAT_FLOAT] idxen offset:42
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: tbuffer_store_immoffs:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: v_mov_b32_e32 v4, 0
+; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:117 idxen offset:42
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: tbuffer_store_immoffs:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: v_mov_b32_e32 v4, 0
+; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:117 idxen offset:42
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
main_body:
%in1 = bitcast <4 x float> %1 to <4 x i32>
call void @llvm.amdgcn.struct.tbuffer.store.v4i32(<4 x i32> %in1, <4 x i32> %0, i32 0, i32 42, i32 0, i32 117, i32 0)
ret void
}
-; GCN-LABEL: {{^}}tbuffer_store_scalar_and_imm_offs:
-; GCN: v_mov_b32_e32 [[ZEROREG:v[0-9]+]], 0
-; PREGFX10: tbuffer_store_format_xyzw v[0:3], [[ZEROREG]], s[0:3], {{s[0-9]+}} format:[BUF_DATA_FORMAT_16_16,BUF_NUM_FORMAT_FLOAT] idxen offset:42
-; GFX10: tbuffer_store_format_xyzw v[0:3], [[ZEROREG]], s[0:3], {{s[0-9]+}} format:117 idxen offset:42
-; GFX11: tbuffer_store_format_xyzw v[0:3], [[ZEROREG]], s[0:3], {{s[0-9]+}} format:117 idxen offset:42
define amdgpu_ps void @tbuffer_store_scalar_and_imm_offs(<4 x i32> inreg, <4 x float> %vdata, i32 inreg %soffset) {
+; VERDE-LABEL: tbuffer_store_scalar_and_imm_offs:
+; VERDE: ; %bb.0: ; %main_body
+; VERDE-NEXT: v_mov_b32_e32 v4, 0
+; VERDE-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], s4 format:[BUF_DATA_FORMAT_16_16,BUF_NUM_FORMAT_FLOAT] idxen offset:42
+; VERDE-NEXT: s_endpgm
+;
+; PREGFX10-LABEL: tbuffer_store_scalar_and_imm_offs:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: v_mov_b32_e32 v4, 0
+; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], s4 format:[BUF_DATA_FORMAT_16_16,BUF_NUM_FORMAT_FLOAT] idxen offset:42
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: tbuffer_store_scalar_and_imm_offs:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: v_mov_b32_e32 v4, 0
+; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], s4 format:117 idxen offset:42
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: tbuffer_store_scalar_and_imm_offs:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: v_mov_b32_e32 v4, 0
+; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], s4 format:117 idxen offset:42
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
main_body:
%in1 = bitcast <4 x float> %vdata to <4 x i32>
call void @llvm.amdgcn.struct.tbuffer.store.v4i32(<4 x i32> %in1, <4 x i32> %0, i32 0, i32 42, i32 %soffset, i32 117, i32 0)
ret void
}
-; GCN-LABEL: {{^}}buffer_store_idx:
-; PREGFX10: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_USCALED] idxen
-; GFX10: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SSCALED] idxen
-; GFX11: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_FMT_8_8_8_8_SINT] idxen
define amdgpu_ps void @buffer_store_idx(<4 x i32> inreg, <4 x float> %vdata, i32 %vindex) {
+; VERDE-LABEL: buffer_store_idx:
+; VERDE: ; %bb.0: ; %main_body
+; VERDE-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_USCALED] idxen
+; VERDE-NEXT: s_endpgm
+;
+; PREGFX10-LABEL: buffer_store_idx:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_USCALED] idxen
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: buffer_store_idx:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SSCALED] idxen
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: buffer_store_idx:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_FMT_8_8_8_8_SINT] idxen
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
main_body:
%in1 = bitcast <4 x float> %vdata to <4 x i32>
call void @llvm.amdgcn.struct.tbuffer.store.v4i32(<4 x i32> %in1, <4 x i32> %0, i32 %vindex, i32 0, i32 0, i32 47, i32 0)
ret void
}
-; GCN-LABEL: {{^}}buffer_store_ofs:
-; PREGFX10: tbuffer_store_format_xyzw v[0:3], {{v\[[0-9]+:[0-9]+\]}}, s[0:3], 0 format:[BUF_DATA_FORMAT_8_8,BUF_NUM_FORMAT_FLOAT] idxen offen
-; GFX10: tbuffer_store_format_xyzw v[0:3], {{v\[[0-9]+:[0-9]+\]}}, s[0:3], 0 format:115 idxen offen
-; GFX11: tbuffer_store_format_xyzw v[0:3], {{v\[[0-9]+:[0-9]+\]}}, s[0:3], 0 format:115 idxen offen
define amdgpu_ps void @buffer_store_ofs(<4 x i32> inreg, <4 x float> %vdata, i32 %voffset) {
+; VERDE-LABEL: buffer_store_ofs:
+; VERDE: ; %bb.0: ; %main_body
+; VERDE-NEXT: s_mov_b32 s4, 0
+; VERDE-NEXT: v_mov_b32_e32 v5, v4
+; VERDE-NEXT: v_mov_b32_e32 v4, s4
+; VERDE-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_DATA_FORMAT_8_8,BUF_NUM_FORMAT_FLOAT] idxen offen
+; VERDE-NEXT: s_endpgm
+;
+; PREGFX10-LABEL: buffer_store_ofs:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: s_mov_b32 s4, 0
+; PREGFX10-NEXT: v_mov_b32_e32 v5, v4
+; PREGFX10-NEXT: v_mov_b32_e32 v4, s4
+; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_DATA_FORMAT_8_8,BUF_NUM_FORMAT_FLOAT] idxen offen
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: buffer_store_ofs:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: s_mov_b32 s4, 0
+; GFX10-NEXT: v_mov_b32_e32 v5, v4
+; GFX10-NEXT: v_mov_b32_e32 v4, s4
+; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:115 idxen offen
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: buffer_store_ofs:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: s_mov_b32 s4, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, s4
+; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:115 idxen offen
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
main_body:
%in1 = bitcast <4 x float> %vdata to <4 x i32>
call void @llvm.amdgcn.struct.tbuffer.store.v4i32(<4 x i32> %in1, <4 x i32> %0, i32 0, i32 %voffset, i32 0, i32 115, i32 0)
ret void
}
-; GCN-LABEL: {{^}}buffer_store_both:
-; PREGFX10: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_UINT] idxen offen
-; GFX10: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_FMT_16_16_16_16_SINT] idxen offen
-; GFX11: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:70 idxen offen
define amdgpu_ps void @buffer_store_both(<4 x i32> inreg, <4 x float> %vdata, i32 %vindex, i32 %voffset) {
+; VERDE-LABEL: buffer_store_both:
+; VERDE: ; %bb.0: ; %main_body
+; VERDE-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_UINT] idxen offen
+; VERDE-NEXT: s_endpgm
+;
+; PREGFX10-LABEL: buffer_store_both:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_DATA_FORMAT_10_11_11,BUF_NUM_FORMAT_UINT] idxen offen
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: buffer_store_both:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:[BUF_FMT_16_16_16_16_SINT] idxen offen
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: buffer_store_both:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 format:70 idxen offen
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
main_body:
%in1 = bitcast <4 x float> %vdata to <4 x i32>
call void @llvm.amdgcn.struct.tbuffer.store.v4i32(<4 x i32> %in1, <4 x i32> %0, i32 %vindex, i32 %voffset, i32 0, i32 70, i32 0)
ret void
}
-; Ideally, the register allocator would avoid the wait here
-;
-; GCN-LABEL: {{^}}buffer_store_wait:
-; PREGFX10: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen
-; GFX10: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_FMT_32_32_SINT] idxen
-; GFX11: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_FMT_32_32_32_32_FLOAT] idxen
-; VERDE: s_waitcnt expcnt(0)
-; GCN: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen
-; GCN: s_waitcnt vmcnt(0)
-; PREGFX10: tbuffer_store_format_xyzw v[0:3], v6, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_USCALED] idxen
-; GFX10: tbuffer_store_format_xyzw v[0:3], v6, s[0:3], 0 format:[BUF_FMT_10_10_10_2_USCALED] idxen
-; GFX11: tbuffer_store_format_xyzw v[0:3], v6, s[0:3], 0 format:[BUF_FMT_8_8_8_8_UINT] idxen
define amdgpu_ps void @buffer_store_wait(<4 x i32> inreg, <4 x float> %vdata, i32 %vindex.1, i32 %vindex.2, i32 %vindex.3) {
+; VERDE-LABEL: buffer_store_wait:
+; VERDE: ; %bb.0: ; %main_body
+; VERDE-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen
+; VERDE-NEXT: s_waitcnt expcnt(0)
+; VERDE-NEXT: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen
+; VERDE-NEXT: s_waitcnt vmcnt(0)
+; VERDE-NEXT: tbuffer_store_format_xyzw v[0:3], v6, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_USCALED] idxen
+; VERDE-NEXT: s_endpgm
+;
+; PREGFX10-LABEL: buffer_store_wait:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_RESERVED_15,BUF_NUM_FORMAT_SSCALED] idxen
+; PREGFX10-NEXT: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen
+; PREGFX10-NEXT: s_waitcnt vmcnt(0)
+; PREGFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v6, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_USCALED] idxen
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: buffer_store_wait:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_FMT_32_32_SINT] idxen
+; GFX10-NEXT: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: tbuffer_store_format_xyzw v[0:3], v6, s[0:3], 0 format:[BUF_FMT_10_10_10_2_USCALED] idxen
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: buffer_store_wait:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_FMT_32_32_32_32_FLOAT] idxen
+; GFX11-NEXT: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: tbuffer_store_format_xyzw v[0:3], v6, s[0:3], 0 format:[BUF_FMT_8_8_8_8_UINT] idxen
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
main_body:
%in1 = bitcast <4 x float> %vdata to <4 x i32>
call void @llvm.amdgcn.struct.tbuffer.store.v4i32(<4 x i32> %in1, <4 x i32> %0, i32 %vindex.1, i32 0, i32 0, i32 63, i32 0)
@@ -108,22 +251,54 @@ main_body:
ret void
}
-; GCN-LABEL: {{^}}buffer_store_x1:
-; PREGFX10: tbuffer_store_format_x v0, v1, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_FLOAT] idxen
-; GFX10: tbuffer_store_format_x v0, v1, s[0:3], 0 format:125 idxen
-; GFX11: tbuffer_store_format_x v0, v1, s[0:3], 0 format:125 idxen
define amdgpu_ps void @buffer_store_x1(<4 x i32> inreg %rsrc, float %data, i32 %vindex) {
+; VERDE-LABEL: buffer_store_x1:
+; VERDE: ; %bb.0: ; %main_body
+; VERDE-NEXT: tbuffer_store_format_x v0, v1, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_FLOAT] idxen
+; VERDE-NEXT: s_endpgm
+;
+; PREGFX10-LABEL: buffer_store_x1:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: tbuffer_store_format_x v0, v1, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_FLOAT] idxen
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: buffer_store_x1:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: tbuffer_store_format_x v0, v1, s[0:3], 0 format:125 idxen
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: buffer_store_x1:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: tbuffer_store_format_x v0, v1, s[0:3], 0 format:125 idxen
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
main_body:
%data.i = bitcast float %data to i32
call void @llvm.amdgcn.struct.tbuffer.store.i32(i32 %data.i, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 125, i32 0)
ret void
}
-; GCN-LABEL: {{^}}buffer_store_x2:
-; PREGFX10: tbuffer_store_format_xy v[0:1], v2, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
-; GFX10: tbuffer_store_format_xy v[0:1], v2, s[0:3], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
-; GFX11: tbuffer_store_format_xy v[0:1], v2, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] idxen
define amdgpu_ps void @buffer_store_x2(<4 x i32> inreg %rsrc, <2 x float> %data, i32 %vindex) {
+; VERDE-LABEL: buffer_store_x2:
+; VERDE: ; %bb.0: ; %main_body
+; VERDE-NEXT: tbuffer_store_format_xy v[0:1], v2, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
+; VERDE-NEXT: s_endpgm
+;
+; PREGFX10-LABEL: buffer_store_x2:
+; PREGFX10: ; %bb.0: ; %main_body
+; PREGFX10-NEXT: tbuffer_store_format_xy v[0:1], v2, s[0:3], 0 format:[BUF_NUM_FORMAT_USCALED] idxen
+; PREGFX10-NEXT: s_endpgm
+;
+; GFX10-LABEL: buffer_store_x2:
+; GFX10: ; %bb.0: ; %main_body
+; GFX10-NEXT: tbuffer_store_format_xy v[0:1], v2, s[0:3], 0 format:[BUF_FMT_10_11_11_SSCALED] idxen
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: buffer_store_x2:
+; GFX11: ; %bb.0: ; %main_body
+; GFX11-NEXT: tbuffer_store_format_xy v[0:1], v2, s[0:3], 0 format:[BUF_FMT_10_10_10_2_SNORM] idxen
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
main_body:
%data.i = bitcast <2 x float> %data to <2 x i32>
call void @llvm.amdgcn.struct.tbuffer.store.v2i32(<2 x i32> %data.i, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 33, i32 0)
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