[PATCH] D144458: [RISCV] Pre-commit test case for ordered reduction, NFC

[Philip Reames via Phabricator via llvm-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM w/comment addressed before landing.



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Comment at: llvm/test/Transforms/LoopVectorize/RISCV/ordered-reduction.ll:3
+; RUN: opt -passes=loop-vectorize -hints-allow-reordering=false -S < %s | FileCheck %s --check-prefix=CHECK-NOT-VECTORIZED
+; RUN: opt -passes=loop-vectorize -S < %s | FileCheck %s --check-prefix=CHECK-UNORDERED
+; RUN: opt -passes=loop-vectorize -force-ordered-reductions=false -hints-allow-reordering=false -S < %s | FileCheck %s --check-prefix=CHECK-NOT-VECTORIZED
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Please add a check line for the configuration: -force-ordered-reductions=true -hints-allow-reordering=false.

This allows you to test the codegen for ordered reductions in this change and next becomes only changing which check prefixes one line uses.  


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D144458/new/

https://reviews.llvm.org/D144458