[PATCH] D144249: [RISCV] Add vendor-defined XTheadMemIdx (Indexed Memory Operations) extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:758
+  // The constants that can be encoded in the THeadMemIdx instructions
+  // are of the form (sign_extend(imm5) << imm2).
+  for (Shift = 0; Shift < 4; Shift++)
----------------
Declare `Shift` before this loop. It adds a line, but the declaration is barely noticeable where it is now.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:2779
+
+    auto Ty = N->getValueType(0);
+    Simm5 = CurDAG->getTargetConstant(Offset >> Shift, SDLoc(N), Ty);
----------------
Use EVT instead of `auto`. It didn't save any characters.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144249/new/

https://reviews.llvm.org/D144249