[PATCH] D144571: [DAGCombine] Fix an ICE in combineMinNumMaxNum(...)

[Cameron McInally via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
cameron.mcinally marked an inline comment as done.
Closed by commit rGaf4c4f4e2143: [DAGCombine] Fix an ICE in combineMinNumMaxNum(...) (authored by cameron.mcinally).

Changed prior to commit:
  https://reviews.llvm.org/D144571?vs=499576&id=499588#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144571/new/

https://reviews.llvm.org/D144571

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/X86/2023-02-22-combineMinNumMaxNum.ll


Index: llvm/test/CodeGen/X86/2023-02-22-combineMinNumMaxNum.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/2023-02-22-combineMinNumMaxNum.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skylake
+
+; Checking for a DAGCombine ICE.
+
+define float @test_combinemaxnum(float %sub) #0 {
+L.entry:
+  %maxnum1 = call float @llvm.maxnum.f32(float 0.000000e+00, float 0.000000e+00)
+  br label %L.LB21_850
+
+L.LB21_850:
+  %neg1 = fneg fast float %maxnum1
+  %neg2 = fneg fast float %sub
+  %mask = fcmp fast ule float %maxnum1, %neg2
+  %maxnum2 = select i1 %mask, float %neg1, float %sub
+  ret float %maxnum2
+}
+
+declare float @llvm.maxnum.f32(float, float) 
+
+attributes #0 = { "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" }
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10815,7 +10815,8 @@
       if (NegRHS == False) {
         SDValue Combined = combineMinNumMaxNumImpl(DL, VT, LHS, RHS, NegTrue,
                                                    False, CC, TLI, DAG);
-        return DAG.getNode(ISD::FNEG, DL, VT, Combined);
+        if (Combined)
+          return DAG.getNode(ISD::FNEG, DL, VT, Combined);
       }
     }
   }


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