[PATCH] D144571: [DAGCombine] Fix an ICE in combineMinNumMaxNum(...)

[Cameron McInally via Phabricator via llvm-commits]

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65420c8041f4 <https://reviews.llvm.org/rG65420c8041f4ca44a3a14c5f7faf426ee6a7c6a4> introduced an ICE in combineMinNumMaxNum(...) when combineMinNumMaxNumImpl(...) returns an SDValue(). Make sure to check that a value is returned before trying to perform an FNEG on it.

Note that this ICE occurs in the release/16.x branch as well, so it will need to be backported. @tstellar


https://reviews.llvm.org/D144571

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/X86/2023-02-22-combineMinNumMaxNum.ll


Index: llvm/test/CodeGen/X86/2023-02-22-combineMinNumMaxNum.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/2023-02-22-combineMinNumMaxNum.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skylake
+
+; Checking for a DAGCombine ICE.
+
+define float @test_combinemaxnum() local_unnamed_addr #0 {
+L.entry:
+  %0 = tail call float @llvm.maxnum.f32(float 0.000000e+00, float 0.000000e+00) 
+  %1 = fsub fast float poison, poison
+  br label %L.LB21_850
+
+L.LB21_850:
+  %2 = fneg fast float %1
+  %3 = fcmp fast ule float %0, %2
+  %4 = fneg fast float %0
+  %5 = select i1 %3, float %4, float %1
+  ret float %5
+}
+
+declare dso_local float @llvm.maxnum.f32(float, float) 
+
+attributes #0 = { "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" }
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10815,7 +10815,8 @@
       if (NegRHS == False) {
         SDValue Combined = combineMinNumMaxNumImpl(DL, VT, LHS, RHS, NegTrue,
                                                    False, CC, TLI, DAG);
-        return DAG.getNode(ISD::FNEG, DL, VT, Combined);
+        if (Combined)
+          return DAG.getNode(ISD::FNEG, DL, VT, Combined);
       }
     }
   }


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