[PATCH] D144249: [RISCV] Add vendor-defined XTheadMemIdx (Indexed Memory Operations) extension

[Manolis Tsamis via Phabricator via llvm-commits]

mtsamis updated this revision to Diff 499537.
mtsamis added a comment.

Restrict shift amount to 2 bits
Only re-arrange ADDI if is simm12
Introduce Complex pattern simm5shl2 for StoreUpdate constants.
Introduce negative constants in StoreUpdate tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144249/new/

https://reviews.llvm.org/D144249

Files:
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/xtheadmemidx.ll
  llvm/test/MC/RISCV/rv32xtheadmemidx-invalid.s
  llvm/test/MC/RISCV/rv32xtheadmemidx-valid.s
  llvm/test/MC/RISCV/rv64xtheadmemidx-invalid.s
  llvm/test/MC/RISCV/rv64xtheadmemidx-valid.s

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