[PATCH] D136861: [IR] Add LLVM IR support for target("aarch64.svcount") type.

[Nikita Popov via Phabricator via llvm-commits]

nikic added inline comments.


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Comment at: llvm/include/llvm/IR/Type.h:216
+    return getTypeID() == ScalableVectorTyID || isScalableTargetExtTy();
+  }
+
----------------
It doesn't look like these new methods are actually used?


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Comment at: llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp:1705
   // decomposeBitTestICmp() might help.
-  {
+  if (TrueVal->getType()->isIntOrIntVectorTy()) {
     unsigned BitWidth =
----------------
This could be committed separately.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136861/new/

https://reviews.llvm.org/D136861