[PATCH] D136861: [IR] Add LLVM IR support for target("aarch64.svcount") type.
Nikita Popov via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 22 07:57:55 PST 2023
nikic added inline comments.
================
Comment at: llvm/include/llvm/IR/Type.h:216
+ return getTypeID() == ScalableVectorTyID || isScalableTargetExtTy();
+ }
+
----------------
It doesn't look like these new methods are actually used?
================
Comment at: llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp:1705
// decomposeBitTestICmp() might help.
- {
+ if (TrueVal->getType()->isIntOrIntVectorTy()) {
unsigned BitWidth =
----------------
This could be committed separately.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D136861/new/
https://reviews.llvm.org/D136861
More information about the llvm-commits
mailing list